Scribd
Upload
57 views1 page

A Aes-Core Development by Using Verilog

The document discusses the Advanced Encryption Standard (AES) and a proposed FPGA design using Verilog HDL to implement AES. AES is a symmetric-key algorithm adopted by the US government that supersedes the Data Encryption Standard (DES). The proposed design contains five modules - key generation, shift rows, mix columns, xoring, and a top module - implemented in Verilog HDL to perform the AES algorithm.

Uploaded by

mdwalunjkar3095
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
57 views1 page

A Aes-Core Development by Using Verilog

The document discusses the Advanced Encryption Standard (AES) and a proposed FPGA design using Verilog HDL to implement AES. AES is a symmetric-key algorithm adopted by the US government that supersedes the Data Encryption Standard (DES). The proposed design contains five modules - key generation, shift rows, mix columns, xoring, and a top module - implemented in Verilog HDL to perform the AES algorithm.

Uploaded by

mdwalunjkar3095
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

A AES-CORE DEVELOPMENT BY USING VERILOG Modern cryptography is heavily based on mathematical theory and computer science practice; cryptographic

algorithms are designed around computational hardness assumptions, making such algorithms hard to break in practice by any adversary. It is theoretically possible to break such a system but it is infeasible to do so by any known practical means. These schemes are therefore termed computationally secure; theoretical advances, e.g., improvements in integer factorization algorithms, and faster computing technology require these solutions to be continually adapted. There exist information-theoretically secure schemes that provably cannot be broken even with unlimited computing poweran example is the one-time padbut these schemes are more difficult to implement than the best theoretically breakable but computationally secure mechanisms. Modern cryptography intersects the disciplines of mathematics, computer science, and electrical engineering. Applications of cryptography include ATM cards, computer passwords, and electronic commerce. The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001.It is based on the Rijndael cipher developed by two Belgian cryptographers, Joan Daemen and Vincent Rijmen, who submitted a proposal which was evaluated by the NIST during the AES selection process. AES has been adopted by the U.S. government and is now used worldwide. It supersedes the Data Encryption Standard (DES), which was published in 1977. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data.AES is included in the ISO/IEC 18033-3 standard. AES is available in many different encryption packages, and is the first publicly accessible and open cipher approved by the National Security Agency (NSA) for top secret information when used in an NSA approved cryptographic module. We proposed a new FPGA design using verilog HDL. Mainly the project contains 5 modules like, key_generation, shift_rows, mix_columns, xoring_module and top module integration. All these modules are authorized in verilog HDL language. The key_generation module generates required keys from the given key. The left circular shift operation is pereformed by shift_rows. The mix_columns performs the matrix multiplication with constant matrix. Xoring module specifies the xroing the text_data with the key. The top modules indicates the integration of all modules and it is treated as the AES_Core.

You might also like