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Ee101 Reso RLC 1.sqproj: Description

This document describes a series RLC circuit driven by a sinusoidal source. It provides the following key details: 1) The total impedance of the circuit is minimum and equal to R at the resonant frequency f0 = 1/2π√LC Hz, resulting in maximum current |I|max = Vs/R. 2) The bandwidth of the circuit, where |I| is reduced to |I|max/2, is given by B = f2 - f1 = R/L Hz. 3) The quality factor Q = 1/RC determines the sharpness of the |I| versus frequency curve, with higher Q indicating a sharper peak near the resonant frequency f

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Sayani Ghosh
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65 views

Ee101 Reso RLC 1.sqproj: Description

This document describes a series RLC circuit driven by a sinusoidal source. It provides the following key details: 1) The total impedance of the circuit is minimum and equal to R at the resonant frequency f0 = 1/2π√LC Hz, resulting in maximum current |I|max = Vs/R. 2) The bandwidth of the circuit, where |I| is reduced to |I|max/2, is given by B = f2 - f1 = R/L Hz. 3) The quality factor Q = 1/RC determines the sharpness of the |I| versus frequency curve, with higher Q indicating a sharper peak near the resonant frequency f

Uploaded by

Sayani Ghosh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ee101 reso rlc 1.

sqproj
VR
R

VL I
L C

Vs

VC

Figure 1: Series RLC circuit driven by a sinusoidal source.

Description
The current I in the series RLC circuit shown in Fig. 1 is given by I= Vs . R + j (L 1/C ) (1)

The following results hold for this circuit in the sinusoidal steady state: (a) The total impedance seen by the source is minimum at 0 = 1/ LC rad/s, and is equal to R, giving |I|max = Vs /R. (b) The bandwidth of the circuit (i.e., B = 2 1 , where 1 and 2 are frequencies at which |I| = |I|max / 2) is given by B = R/L. (c) The quality Q = 1 L 0 = is a measure of the sharpness of the |I| versus frequency B R C curve. The quality of the circuit can be visually judged by plotting |I| versus log (or

log f ). (d) For 0 , the total impedance is dominated by the capacitor, i.e., Z 1/jC . Almost

the entire source voltage appears across the capacitor, i.e., VC Vs , and the current I has a phase of +/2. (e) For 0 , the total impedance is dominated by the inductor, i.e., Z jL. Almost

the entire source voltage appears across the inductor, i.e., VL Vs , and the current I has a phase of /2.

Exercise Set
1

1. For R = 1 , L = 1 mH , and C = 1 F , calculate f0 and B . Verify with simulation. 2. What happens to the bandwidth if R is doubled? Plot |I| versus log f for R = 1 and R = 2 on the same graph. 3. What is |VC | for 0 , = 0 , and 0 ? Make an approximate sketch of |VC |

versus log , using the above information. Check with simulation. 4. What will happen to the |VC | versus log curve if R is doubled? Relate your answer to the Q of the circuit. 5. Sketch |VL | and |VC | versus log together. Verify with simulation. 6. Sketch VL and VC versus log together. Verify with simulation.

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