G

NARAYANAMMA INSTITUTE OF
(FOR WOMEN) HYDERABAD

TECHNOLOGY & SCIENCE

SHAIKPET, 500008

DIGITAL IC LABORATORY MANUAL

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING MARCH - 2006

G NARAYANAMMA INSTITUTE OF TECHNOLOGY & SCIENCE

(FOR WOMEN) SHAIKPET, HYDERABAD 500008

GNITS LAB WISE-LABMANUALS

GNITS-D / ECE / LLM / 023(g) / 01 DEPARTMENT : ECE

DIGITAL IC LABORATORY MANUAL

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING MARCH - 2006

INDEX
S.NO 1.
2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

NAME OF THE EXPERIMENT

LOGIC GATES.

PAGE NO
1

D FLIP-FLOP -IC7474. DECADE COUNTER-IC7490. 4-BIT COUNTER IC7493. SHIFT REGISTER-IC7495. UNIVERSAL SHIFT REGISTER-IC74194/195. 3-8 DECODER-IC74138. 4 BIT COM PARATOR-IC7485. 8X1 MULTIPLEXER-IC74151. 16X1 MULTIPLEXER-IC74138. RAM (16X4-74189)(READ &WRITE OPERATIONS). STACK & QUEUE IMPLEMENTATION USING RAM.

9 15 19 24 28 34 38 41 46 50

12.

55

LOGIC GATES
Aim: 1) Study of logic gates using ICs & discrete components. 2) Realization of basic gates using NAND & NOR gates (Universal gates). Apparatus: 1. Logic gates (IC) trainer kit.

2. Trainer kit for discrete circuit of gates

3. Connecting patch chords.

I. Verifying the logic gates using ICs: S.NO 1. GATE NAND IC 7400 NOR IC 7402 AND IC 7408 SYMBOL INPUTS A A B C= A B 0 0 1 1 0 0 1 1 0 0 1 C=AB B 4. OR IC 7432 A 1 0 0 1 1 5. NOT IC 7404 EX-OR IC 7486 A C=A+B B C= A 1 0 0 0 1 1 Fig (1) B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT C 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 1 0

2.

A B

C= A + B

3.

6.

Realization of all gates using NOR gate: NOT GATE

C=A

OR GATE

AND GATE
A

A AB B

NAND GATE

Fig (2.1)

Realization using NAND gate: NOT GATE: A A

AND GATE: A B AB AB

OR GATE: A A

A+B B B

NOR GATE:

A+B

A+B

B B

Fig (2.2) Realization of basic ex-or gate using nand & nor gate:
Basic configuration of EX-OR gate: A

AB

A B

C=

AB + A B

B B EX-OR USING ONLY NAND GATES: A A

AB
A+B

C = AB + A B
B B

A+B

EX-OR USING ONLY NOR GATES:

II.Verifying the logic gates using discrete components:

AND GATE: +V(5V) 4.7K A B C IN4007 IN4007 IN4007 Y=A.B.C

OR GATE:

NOT GATE:

NAND GATE: +V(5V) 4.7K IN4007 A IN4007 B IN4007 C IN4007 4.7K 2.2K IN4007 Y=A.B.C BC547

Procedure: 1. 2. 3. 4. 5. 6. Connect the logic gates as shown in the figure1. Feed the logic signals 0 or 1 from the logic input switches at the inputs A & B. Monitor the output using logic output LED indicators. Repeat steps 1 to 3 for NOT, AND, OR & NOR operations. Connect the logic gates as shown in figure 2.1 & 2.2 and repeat the steps 2 through 3. Connect the logic gates as shown in figure 3 and repeat the steps 2 and 3 Verify the truth table for EX OR gate. 7. Implement the logic gates using discrete components (fig 4) and verify the truth tables. Result: Truth tables of all logic gates have been verified.

Questions: 1. Why NAND & NOR gates are called universal gates? 2. Realize the EX OR gates using minimum number of NAND gates? 3. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates?

4. Realize the given logic function using NAND and also using
NOR gates?

f = A BC + A B C + AB C
5. Explain the operation of NAND gate when realized using discrete components? 6. In what regions does the transistor is operated such that it behaves like a Switch? 7. What are the logic low and High levels of TTL ICs and CMOS ICs? 8. Compare TTL logic family with CMOS family? 9. Which logic family is called fastest and which logic family is called low power dissipated?. 10. Explain the operation of OR, NOR gates when realized using discrete Components? 11. Why the transistor operates as NOT gate?

RS, JK , D AND T FLIP FLOP

Aim: To verify the truth table of a) RS Flip Flop using Logicgates b) JK Flip Flop-IC 7476 c) D Flip Flop-IC 7474 d) T Flip Flop using JKFlip-Flop.

Apparatus :1. 2. RS, JK, D and T flip-flops Trainer Kit. Set of Patch chords.

RS Flip-Flop:

Fig1. RS Flip-Flop

RS Flip-Flop Clocked version:

S Q

CLK

Q R Truth table 1 for RS Flip Flop INPUTS S 0 1 0 1 OUTPUT Q 1 0 Set 1 1 0 1 Reset Indeterminate No change COMMENT

R 0 0

Q 1 1

Indetermine nt

Procedure: 1. 2. Construct the RS flip flop as shown in figure. Feed the logic signals from the logic input switches observe the logic outputs on the logic level LED indicators. Verify the truth table of clocked RS flip-flops. JK Flip Flop:

Truth Table-2 for JK flip-flop: INPUTS Set(s) Reset(R) 0 0 1 1 1 1 1 0 1 0 1 1 1 1 Clock J X X X X X X X X 0 0 1 1 X X 0 1 0 1 K OUTPUTS Q 1 1 0 Q0 0 1 Q 1 0 1 Q0 1 0

|

COMMENT

Indeterminent Set Reset Previ ous Reset set Race around

Toggle

Procedure: 1. Connect S , R, J and K terminals to the logic input switches. 2. 3. 4. Connect the clock terminals to bounceless pulser high or low. Connect Q and Q terminals to logic output indicators. Set the S, R, J and K Signals by means of the switches as per the truth table2 verify the Q and Q outputs .

D-Flip -Flop:

D-flip-flop using Nand gates :

S 0 0 1 1 1

R 0 1 0 1 1

CLOC K X X

D X X

Q 1 1 0

Q 1 0 1 0

COMMENT Ra ce S e t Reset Data

X 1

1 0

1 Transfer Data

Truth Table - 3

Procedure: 1. Connect S, R and D terminal to the logic input switches. 2. 3. 4. Connect the clock terminals to bounceless pulser high or low. Connect Q and Q terminals to logic output indicators. Set the S, R and D signals by means of the switches as per TruthTable3. Verify the Q and Q outputs. T Flip Flop:

J& K 1 1 1 1

S 0 0 1 1

R 0 1 0 1

CLO CK (X X

Q 1 1 0

Q 1 0 1 Q
n-1

COMMENT Ra ce S e t Res

Q
n-1

Truth Table - 4 Procedure: 1. 2. 3. 4. 5.

Connect S and R Terminals to the logic input switches. Set J and K permanently to high by means of input switches. Connect the clock terminals (T) to the bounceless pulser high or low. Connect Q and Q terminals to logic output indicators. Set the S and R signals by means of the switches as per Truth Table 4 verify the Q and Q outputs.

Result: Verified the truth tables of all Flip-Flops.

Questions:1. What is the difference between Flip-Flop & latch? 2. 3. 4. 5. 6. 7. 8. 9. Give examples for synchronous & asynchronous i/Ps? What are the applications of different Flip-Flops? What is universal flip-flop? What is the advantage of Edge triggering over level triggering? What is the relation between propagation delay & clock frequency of flip-flop? What is race around in flip-flop & how to over come it? What are not allowed inputs for RS flip flop using NAND & NOR gates? Connect the J K Flip-Flop into D flip-flop and T flip-flop?

10. List the functions of asynchronous inputs?

IC7490 DECADE COUNTER

Aim: To construct and verify the working of a single digit decade counter using IC 7490. 1) IC7490 Decade counter kit 2) Connecting patch cards. Apparatus:

Circuit Diagram :-

OUTPUTS

Procedure:
1. 2. 3. 4. 5. 6. 7. 8. Wire the circuit diagram shown in figure 1. Connect the 1Hz clock to pin CPO.(14)

Fig:1

Connect the reset terminals (MR1 & MR2) to high and set terminals (MS1 & MS2) to zero and observe the output. Now connect set and reset inputs to zero and observe the outputs. Record the counter states for each clock pulse. Design mod 6 counter using IC 7490 as shown in fig 2. Record the counter states for each clock pulse. Now Construct decade counter using J K F/Fs and record the counter states.

MOD 6 COUNTER

A3 Msb 0 0 0 0 0 0 0

A2 0 0 0 0 1 1 1

A1 0 0 1 1 0 0 1

A0 Lsb 0 1 0 1 0 1 0

Truth Table:-

0000

Expected Wave Forms:-

Result:- Verified the working of a single digit decade counter using IC 7490. Questions:1. 2. 3. 4. 5. 6. 7. 8. 9. Design Mod 7 and Mod 5 counter using IC 7490?`1`1 Design Mod 6 counter using JK F/Fs? What is the modulus counter? How many numbers of flip-flops are there in decade counter? What is up down counter? What is the difference between Register &counter? What is BCD counter? If the counter has n-flip-flops. What is the maximum count? Which flip- flops are used in counter?

10. Design a divide by-96 counter using 7490Ics?

4 BIT BINARY RIPPLE COUNTER

Aim: To study the operation and working of a 4 bit binary ripple counter using IC 7493

Apparatus:1. 2. Theory: 4 Bit binary ripple counter trainer kit. Set of Patch chords The ripple counter is simple and straightforward in operation and construction and usually flip-flop is triggered by the

requires a minimum of hardware. It does, however, have a speed limitation. Each asynchronous.

previous flip-flop, and thus the counter has a cumulative settling time. Counters such as these are called serial or The output Q0 must be externally connected to the input CP1. The input count pulses are applied to input CP0. Simultaneous divisions of 2, 4, 8 and 16 are performed at the Q0, Q1, Q2 and Q3 outputs as shown in the truth table. A ripple counter can be constructed by use of clocked JK flip-flops. Fig shows four Master-Slaves, JK flip-flops connected in cascade. The system clock, a square wave, drives flip-flop A. the output of A drives B, and output of B drives flip-flop C and output of C drives flip-flop D. All the J and K inputs are tied to +V
cc.

This means that each flip-flop will change state (toggle) with a negative transition at its clock input. When the output of a flip-flop is used as the clock input for the next flip-flop, we call the counter a ripple counter, or asynchronous counter. The A flip-flop must change states before it can trigger the B flip-flop, and the B flipflop has to change states before it can trigger the C flip-flop. And the C flip-flop has to change states before it can trigger the D flip-flop the triggers move through the flip-flops like a ripple in water.

The waveforms given in fig show the action of the counter as the clock runs.

Every

time there is a negative clock transition, flip-flop A change state., Notice that the waveform at the output of flip-flop A is one half the clock frequency. Since A acts as a clock for B, each time the waveform at A goes low, flip-flop B will toggle. notice that the waveform at the output of flip-flop B is one half the frequency of A and one fourth the clock frequency. Since B acts as the clock for C, each time the waveform at B goes low, flip-flop C will toggle .The frequency of the waveform at C is one half that at B, but it is only one eight the clock frequency. Now C acts as a clock for D. Each time the wave form at C goes low,flip-flop D will toggle . The frequency of the waveform at D is one half that at C, but it is only one sixteenth the clock frequency.

Procedure: 1. 2. 3. Switch ON the experimental board by connecting power chord to the AC mains. Connect the Bounceless pulser output to the clock input of 7493 counter. Verify the given mode selection table. Mod selection table RESET INPUTS MR
1

OUTP UT Q
0

MR
2

Q
1

Q
2

Q
3

H L L 4. . COUNT

H H HL L

L COU NT COU

Table - 1 Verify the truth table of the 7493 Ripple counter. OUTP UT

Q3 0 1 2 3 4 5 6 7 L L L L L L L L

Q2 L L L L H H H H

Q1 L L H H L L H H

Q0 L H L H L H L H

4-bit Ripple counter pin diagram :

Fig:1

4-bit Ripple counter Logic diagram :

Fig:2

Expected wave forms:-

RESULT :- The operation and working of a 4 bit binary ripple counter using IC 7493 is verified .

Questions :1. 2. 3. 4. 5. 6. 7. 8. 9. What is meant by a Ripple Counter? What is the other name for ripple counter? What is the difference between serial & parallel counter? What is ring counter? What are the applications of presettable counters? What is modulus of counter? What are the applications of counters? What is the difference between Counter and Register? Design a 4-bit binary UP/DOWN ripple counter using T F/Fs?

10. What is the primary disadvantage of asynchronous counters?

IC 7495 SHIFT REGISTER

Aim : To study the operation of the shift register using IC7495 . Apparatus : 1.Shift register kit 2. Connecting wires.

Q0(MSB) 1 1 1 1 0

Q1 1 1 1 0 0

Q2 1 1 0 0 0

Q3(LSB) 1 0 0 0 0

Y 15 14 12 8 0

Truth table for left shift register:

Truth table for right shift register : Q0(MSB) 0 0 0 0 Q1 1 0 0 0 Q2 1 1 0 0 Q3(LSB) 1 1 1 0 Y 7 3 1 0

Right shift logic diagra m:-

Procedure: 1. 2. Construct 4 bit left shift register as shown in fig. Connect the output logic level indicators to the outputs of each stage of shift register. Apply 1 Hz CLOCK CP input to 9. Output. 4. Switch ON 5th pin some time and after off it. 5. 6. Put the 6th pin in high and 1st pin in low position. Observe the left shifting through the shift register.

3. In left shift register 2&12, 3&11,4&10 pins shorted and given to the

For right shift : 7. 8. 9. Apply 1 Hz CLOCK CP input to 8. Connect the pin nos. 1,2,3,4,5,6 to the logic inputs. Put the 6th pin low position, 2, 3, 4, 5 pin nos. in high position.

10. Switch ON 1st pin some time and after off it. 11. Observe the Right shifting through the shift register. Result:The operation of the Right shift &left shiftregister using IC7495 has been verified.

Questions :1. 2. 3. 4. 5. 6. 7. 8. 9. What are the applications of shift registers? Which flip flop is used in shift register? What is universal shift register? What are different types of shift registers? Which shift gives multiplication by 2? Which shift gives division by 2? Can we use shift register as counter? How timing sequences can be generated using shift registers? Explain the working of 4-bit SIPOshift register?

10. What are glitches in digital circuits?

UNIVERSAL SHIFT REGISTER

Aim :- To study the following applications of the Universal shift register using IC 74194.
a . Shift Right Logic

b . Shift Left Logic

c . Parallel Load

Apparatus :-

1. Universal Shift Register using IC 74194 Trainer boards.

Circuit Diagram:-

2. 5v fixed DC power supply.

Procedure:STEP : 1. MASTER RESET

Set the inputs as below and observe the out puts as per table 1 MR S1 S0 DS DS CP P0 P1 P2 R L 0 X X X X X X X X Truth table 1

P3 X

Q0 0

Q1 0

Q2 0

Q3 0

A logic 0 on MR resets all outputs to logic 0 irrespective of other inputs. STEP :2 PARALLEL LOAD In this step we load the data parallel. Set the inputs as below and observe the outputs. MR 1 S1 1 S0 1 DS R x DS L x CP CL K P0 1 P1 1 P2 1 P3 1 Q0 1 Q1 1 Q2 1 Q3 1

Truth Table 2

Here when S1 & S0 are both logic 1 the input data is transferred parallely to output at the clock positive transition change the input data and observe the change at the output .
STEP : 3 . SHIFT LEFT LOGIC 0 . Set Q0 , Q1 , Q2 , Q3 to 1 1 1 1 by putting DSL to Logic 1 . While running the above step, change the logic input DSL to logic 0 And S to logic 0 in the same sequence .Observe the following outputs after each clock pulse and verify .
0

CONDITION MR = S0 S1 = 1 1 0

n CLOCK PULSES 0 1 2 3 4 Truth Table 3

Q0
1 1 1 1 0

Q1
1 1 1 0 0

Q2
1 1 0 0 0

Q3
1 0 0 0 0

= 0

DSL =

DSR = X

In the sequence 4 clock pulses logic o s are shifted left successively with each clock pulse . STEP : 4 . SHIFT LEFT LOGIC 1 S Set the Q0 Q1 Q2 Q3 to 0 0 0 0 by setting DSL input to logic 0 . Now switch DSL input to logic 1 and observe the shifting of logic 1 s to left as below . Observe the following outputs after each clock pulse and verify.

CONDITION MR = S0 S1 = 1 1 1

n CLOCK PULSES 0 1 2 3 4

Q0
0 0 0 0 1 Truth Table 4

Q1
0 0 0 1 1

Q2
0 0 1 1 1

Q3
0 1 1 1 1

= 0

DSL =

DSR = X

STEP : 5 . SHIFT RIGHT LOGIC 0 Set the Q0 Q1 Q2 Q3 to 1 1 1 1 by setting DSR input to logic 1 . Repeat step 4 and parallel load logic 1 s in all the 4 outputs . Change the logic inputs of DSR to logic 0 and then of S1 to logic 0 in the same sequence . Observe the following outpus after each clock pulse and verify . CONDITION MR = S0 S1 = 1 0 n CLOCK PULSES 0 1 2 3 4 = 1

Q0
1 0 0 0 0 Truth Table 5

Q1
1 1 0 0 0

Q2
1 1 1 0 0

Q3
1 1 1 1 0

DSL = X DSR = 0

STEP : 6 SHIFT RIGHT LOGIC 1 s Now at this condition of all 0 at the outputs switch DSR to logic 1 this will enable all logic as serial data and logic 1 s will be shifted successively with each clock pulse as shown below .Observe the following table and verify the outputs . CONDITION MR = S0 S1 = 1 0 n CLOCK PULSES 0 1 2 3 4 1 = 1

Q0
0 1 1 1

Q1
0 0 1 1 1

Q2
0 0 0 1 1

Q3
0 0 0 0 1

DSL = X DSR = 1

STEP : 7 . In the above steps for shift left or shift right operation ,(step 3 4 5 6 ) if both the S0 &S1 switches are forced to logic 0 , then shifting operation will cease and whatever is the output data it will freeze or hold . Observe this condition and verify .

CONDITION MR = S0 S1 = 1 0 0 = 0

n CLOCK PULSES 1 1 1 1 1 Truth Table 7

Q0

Q1 Q2 Q3

Previous data just before S0 &S1 both switched to logic 0 .

DSL =

DSR = 0

Result:- Verified the applications of the Universal shift register using IC 74194

Questions: 1. 2. 3. 4. 5. 6. 7. 8. 9. What is the universal shift register? In which circuits shifting and rotating circuits are used? Which flip-flops are used in shift registers? Which flip-flop is universal flip-flop? What is the difference between shifting and rotating data? What is register? What is meant by parallel in &parallel out Shift register? State various applications of Shift register? List the basic types of shift register in terms of data movement? held high?

10. Determine the output status of a 4-bit SIPO shift register, after 3 clock pulses if the I/P terminal is

3 TO 8 DECODER
Aim: To verify operation of the 3 to 8 decoder using Ic 74138. Apparatus : Theory: 1 .3 to 8 decoder Ic 74138 kit. 2 .Patch chords .

A decoder is a combinational circuit that connects the binary information from n input lines to a maximum of 2n unique out put lines .The IC 74138 accepts three binary inputs and when enable provides 8 individual active low outputs . The device has 3 enable inputs .Two active low and one active high. Circuit Diagram :

Truth Table: -

INPUTS ENABLES G1 x x 0 1 1 1 1 1 1 1 1 G2 A 1 x x 0 0 0 0 0 0 0 0 G2 B x 1 x 0 0 0 0 0 0 0 0 C x x x 0 0 0 0 1 1 1 1 B x x x 0 0 1 1 0 0 1 1 A Y0 x x x 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 Y 1 1 1 1 1 0 1 1 1 1 1 1 Y2 1 1 1 1 1 0 1 1 1 1 1 Y3 1 1 1 1 1 1 0 1 1 1 1 Y4 1 1 1 1 1 1 1 0 1 1 1

OUTPUTS

Y5 1 1 1 1 1 1 1 1 0 1 1

Y6 1 1 1 1 1 1 1 1 1 0 1

Y7 1 1 1 1 1 1 1 1 1 1 0

Logic Diagram:

Procedure :1. Make the connections as per the circuit diagram . 2. Change the values of G1,G2A,G2B,A,B,and C, using switches. 3. Observe status of Y0, to Y7 on LEDs. 4. Verify the truth table. Result:Verified the Operation of 3 to 8 Decoder.

Questions:1. 2. 3. 4. 5. 6. 7. 8. 9. What are the applications of decoder? What is the difference between decoder & encoder? For n- 2n decoder how many i/p lines & how many o/p lines? What are the different codes & their applications? What are code converters? What is even parity & odd parity? Which gate can be used as parity generator & checker? Using 3:8 decoder and associated logic, implement a full adder? Implement a full subtract or using IC 74138?

10. What is the difference between decoder and demux?

4 BIT COMPARATOR

Aim:- To study the operation of 4-bit Magnitude Comparator using Ic7485. Apparatus :- 1 . Power supply . Theory :Magnitude Comparator is a logical circuit , which compares two signals A and B and generates three logical outputs, whether A > B, A = B, or A < B . IC 7485 is a high speed 4-bit Magnitude comparator , which compares two 4-bit words . The A = B Input must be held high for proper compare operation. 2. IC7485 4-bit Comparator kit.

Procedure:1. Connect the circuit as shown in fig. Feed the 4-bit binary words A0, A1 , A2 , A3 and .from the logic input switches. 2 . Pin 3 of IC 7485 should be at logic 1 to enable compare operation. B0 , B1 , B2 , B3

3 . Observe the output A>B, A=B , and A<B on logic indicators. The outputs must be 1 or 0 respectively.
4 . Repeat the steps 1 ,2 and 3 for various inputs A0 ,A1 , A2 , A3 and B0 , B1 , B2 , B3 and observe the outputs at A>B , A=B and A<B .

Verification Table : A3 A2 A1 A0

OUTPUT

B3 B2 B1
1 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 1 0 1 0

B0 A>B

A=B
1

A<B

Result:- Verified the operation of 4-bit magnitude comparator using Ic 7485 .

Questions :1. What is Comparator? 2. What are the applications of Comparator? 3. Which logic is used as 1 bit comparator? 4. What are different arithmetic comparisons? 5. Can we use subtractor & divider as comparators? 6. What is the significance of 74 on ICs? 7. Design a 5 bit comparator using a single IC 7485, and one gate? 8. Design a 2 bit comparator using a single Logic gates? 9. Design a 8 bit comparator using a two numbers of IC 7485? 10. Design a 24 bit comparator using a six numbers of IC 7485? .

8:1 Multiplexer
Aim: To verify the truth table of a given 8 to 1 Multiplexer and 1 to 8 De-Multiplexer using IC 74151 and 74138 . Apparatus: 1. 2. Theory: Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output. By using control signals (select lines ) we can select any input to the output. Multiplexer is also called as data selector because the output bit depends on the input data bit that is selected. signal. The general idea about the multiplexing the circuit has N input signals, M control signals and 1 output 8 X 1 Multiplexer has 8 input signals and one output signal, three data control or select lines. These 8 to 1 Multiplexer Trainer kit . Connecting patch chords.

data control lines are nothing but 3-bit binary code on the data control signal inputs which will allow the data on the corresponding data input to pass through to the data output

Pin Diagram:-

Circuit Diagram:

.Truth Table: Q2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 I0 0 1 X X X X X X X X X X X X X X I1 X X 0 1 X X X X X X X X X X X X I2 X X X X 0 1 X X X X X X X X X X I3 X X X X X X 0 1 X X X X X X X X I4 X X X X X X X X 0 1 X X X X X X I5 X X X X X X X X X X 0 1 X X X X I6 X X X X X X X X X X X X 0 1 X X I7 X X X X X X X X X X X X X X 0 1 Y L H L H L H L H L H L H L H L H

Logic Diagram:-

Procedure: 1. 2. 3. 4. 5. 6. Result: Switch on the trainer by connecting power chord to the AC mains By using pulsar switch reset the control signals (Q2 Q1 Q0 ) to 0 0 0 Connect the output terminals (pin 5) to the output LEC indicator. Apply logic 1 to I0 input (pin 4) by using the switch. The output LED indicator glows Apply logic 0 to I0 input (pin 4) by using the switch. The output LEC indicator is off. Verify the truth table by changing the control 3 signal states using pulsar switch from 000 to 111 The truth table of 8 to 1 multiplexer has been verified. What is multiplexer? What are the applications of multiplexer? What is the difference between multiplexer & demultiplexer? In 2n to 1 multiplexer how many selection lines are there? How to get higher order multiplexers? Impliment full subtractor using demux?. Impliment a 8:1 mux using 4:1 muxes?. Design full adder using 8:1 Mux Ics?. Design a BCD-to- gry code connecter using 8:1 muxes?

Questions:1. 2. 3. 4. 5. 6. 7. 8. 9.

10. Draw and explain the design of a32:1 mux using 8:1 MUX and 4:1 MUX.?

16 LINE TO 1 LINE MULTIPLEXER

Aim: To study the circuit of 16 line to 1- line multiplexer using 74150 .

Apparatus:1. 2. 16 line to 1 line Multiplexer Trainer Set of Patch Chords and User Manual.

Theory:- Multiplex means Many to one . A multiplexer is a circuit with many inputs but only one out put by applying control signals. We can steer any input to the output. Multiplexer is also called a data selector. The input data bits are D0 (I0) to D15 (I15), only one of these is transmitted to the output. Control word ABCD (S3 S2 S1 S0) determines which data bit is passed to the out put. For example ABCD=0000 Output=D0(I0) when ABCD=1111 output =D15(I15). Procedure:1. 2. Switch ON the experimental board by connecting power chord to the A C mains. Connect the manual pulser output to the input of the scan signal generator and press the pulser switch until we get Q3, Q2, Q1, Q0, equal to 0000. 3. S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Verify the Table 2 by changing the counting sequence with pulser switch from 0000 to 1111. S1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y(Channel selected at o/p) I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

Circuit Diagram:16-LINE TO 1-LINE MULTIPLEXER

Function Table: H - High voltage level; L Low Voltage level X - Dont care INPU TS S
3

O / D
12

S
2

S
1

S
0

X X X XLL L L L L L LL L L H L L L H L L H LL L H LL L H HLL H HLH L L L H L LL H L H LH L H LH H L LH H L LH H H LH H HH L L LH L L LH L L H H L L H H L H L H L H L H L H H H L H H H HL LH H L LH H L H H HL

E H L L L L L L L L L L L L L L L L L L

D
0

D
1

D
2

D
3

D
4

D
5

D
6

D
7

D
8

D
9

D
10

D
11

D
13

D
14

D
15

X X X X X X X X X X X X X X X X L X X X X X X X X X X X X X X X H X X X X X X X X X X X X X X XX L X X X X X X X X X X X X X X X H X X X X X X X X X X X X X X X X L X X X X X X X X X X X X XX X H X X X X X X X X X X X X XX X X L X X X X X X X X X X X XX X X H X X X X X X X X X X X XX X X X L X X X X X X X X X X XX X X X H X X X X X X X X X X XX X X X X L X X X X X X X X X XX X X X X H X X X X X X X X X XX X X X X X L X X X X X X X X XX X X X X X H X X X X X X X X XX X X X X X X L X X X X X X X XX X X X X X X H X X X X X X X XX X X X X X X X L X X X X X X XX X X X X X X X H X X X X X X XX X X X X X X X X L X X X X X XX X X X X X X X X H X X X X X XX X X X X X X X X X L X X X X XX X X X X X X X X X H X X X X XX X X X X X X X X X X L X X X XX X X X X X X X X X X H X X X XX X X X X X X X X X X X L X X X X X X X X X X X X X X XH X X XX X X X X X

Y H H L H L H L H L H L H L H L H L H L

Result:- The circuit of 16 line to 1- line multiplexer using 74150 is verified.

Questions:1) What is meant by a multiplexer? 2) List the applications of multiplexer? 3) Why scan signal generator is required for Multiplexer?. 4) How many number of 8x1 multiplexers is required to have 16x1 mux?. 5) Impliment a 16:1 mux using 4:1 Mux Ics . 6) Draw the circuit diagram of a 1:4 demux using AND .Explain its operation? 7) Design a BCD-to-7 segment decoder with active low out puts using dual 4:1 muxs and some gates.? 8) Multiplexer is called universal logic gate Justify it?. 9) How can multiplexer work as a parallel to serial converter? 10) Design a 1:40 demux using BCD-to-decimal decoders?.

STUDY OF RAM IC 7489

Aim: - To study the operation of the RAM Ic7489. Apparatus: - 1. RAM IC 7489 Trainer kits. 2. Connecting wires. Pin Diagram: -

Operation: RAM IC 7489 is 16 words x 4-bit Read/WriteMemory.

The Truth Table for the RAM IC 7489 is given below. Memory Enable H L Write Enable X H Operation All data outputs are high Read mode (data outputs are compliment of the RAM content). L L Write mode (data inputs are written on to the memory; dataoutputs are compliment of the RAM content).

 The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select signal. For simply city, the memory enable pin is permanently held low. The address lines are given through an up /down counter with preset capability. The set address switch is held high to allow the user choose any location in the RAM, using the address bits. The address and data bits are used to set an address and enter the data. The Read/Write switch is used to write data on to the RAM. Procedure: This experiment has 3 stages Clearing the memory, data entry (Write operation) and data verification (Read operation).
Clearing the Memory: -The RAM IC 7489 is a volatile memory. This means that it will lose the data stored in it, on loss of power. However, this dose not means that the content of the memory becomes 0h, but not always. The RAM IC 7489 does not come with a Clear Memory signal. The memory has to be cleared manually. 1. Position the Stack/Queue switch in the Queue position. 2. Position the Set Address switch in the 1 position. 3. Set the address bits to 0h (first byte in the memory) 4. Position the Set Address switch in the 0 position to disable random access and enable the counter. 5. Position the Read/Write switch in the Write position to write data on to the memory. 6. Set the data bits to 0h (clearing the content)

7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h. Refer the truth table above and observe that the data outputs of the RAM will be compliments of the data inputs.
8. Position the Increment/Decrement switch in the Increment position. 9. Press the Clock to increment the counter to the next address. As the Read /Write switch is already in the Write position, and the data bits are set to the 0h, the content in the new location is also replaced with 0h. 10. Repeat step 8 until the data in all the memory locations have been cleared.

Write Operation: 1. Assume that the following data has to be written on to the RAM. The address and data are given in the hexadecimal format.

Address 0h - 0000
1h - 0001 2h - 0010 3h - 0011 4h - 0100 5h - 0101 6h - 0110 7h - 0111 8h - 1000 9h - 1001 10h - 1010 11h - 1011 12h - 1100 13h - 1101 14h - 1110 15h - 1111

Data Ah - 1010
Bh 4h 7h 1h 5h 8h 3h Eh 9h Dh 0h 2h 6h 1011 - 0100 - 0111 - 0001 1111 - 0101 - 1000 - 0011 - 1110 - 1001 - 1101 - 0000 - 0010 - 0110

Ch - 1100 Fh -

2. Position the Stack/Queue switch in the Queueposition.

3. Position the Read/Write switch in the Write position to enable the entry of data in to the RAM. 4. Position the Set Address switch in the 1 position to allow random access of memory. 5. Set the desired address (any address at random) using the address bit switches. 6. Set the desired data (refer table for the data to be entered in each location) using the data bit switches. 7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is written on to the RAM. 8. Also observe that the data is indicated by the data outputs is the compliment of the data input (refer truth table condition ME =L and WE=L) . 9. After each data entry, make a note of the location where data is entered. This is to make sure that we are not re entering data in the same location. 10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table 11. Position the Read/Write switch in the Read position, to disable data entry.

12. This completes data entry.

Read Operation: -

1. Position the Stack/Queue switch in the Queue position. 2. Position the Set Address switch in the 0 position to allow random access of memory.
3. Position Read/Write switch in the Read position, to disable unauthorized entry of data. 4. Set the desired address (any address at random). 5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This is because the data was written during the data entry procedure. 6. Also observe that the data indicated by the data out puts is the compliment of the data input (refer truth table condition ME=L and WE=H).

Result: - Operation of the RAM Ic7489 has been verified.

Questions: 1. What is the RAM? . 2. Give the applications of the RAM? . 3. What is the difference between RAM &ROM? . 4. What is the difference between static RAM &dynamic RAM? 5. Which can be used as 1-bit memory? 6. What are the different types of the ROM? . 7. What are the parameters of the RAM? 8. What is refreshing of memory? And where it is required? 9. What are sequential access memories? 10. What are charge-coupled devices?

UNIVERSAL SHIFT REGISTER

Aim :- To study the following applications of the Universal shift register using IC 74194.
a . Shift Right Logic

b . Shift Left Logic

c . Parallel Load

Apparatus :-

1. Universal Shift Register using IC 74194 Trainer boards.

Circuit Diagram:-

2. 5v fixed DC power supply.

Procedure:STEP : 1. MASTER RESET

Set the inputs as below and observe the out puts as per table 1 MR S1 S0 DS DS CP P0 P1 P2 R L 0 X X X X X X X X Truth table 1

P3 X

Q0 0

Q1 0

Q2 0

Q3 0

A logic 0 on MR resets all outputs to logic 0 irrespective of other inputs. STEP :2 PARALLEL LOAD In this step we load the data parallel. Set the inputs as below and observe the outputs. MR 1 S1 1 S0 1 DS R x DS L x CP CL K P0 1 P1 1 P2 1 P3 1 Q0 1 Q1 1 Q2 1 Q3 1

Truth Table 2

Here when S1 & S0 are both logic 1 the input data is transferred parallely to output at the clock positive transition change the input data and observe the change at the output .
STEP : 3 . SHIFT LEFT LOGIC 0 . Set Q0 , Q1 , Q2 , Q3 to 1 1 1 1 by putting DSL to Logic 1 . While running the above step, change the logic input DSL to logic 0 And S to logic 0 in the same sequence .Observe the following outputs after each clock pulse and verify .
0

CONDITION MR = S0 S1 = 1 1 0

n CLOCK PULSES 0 1 2 3 4 Truth Table 3

Q0
1 1 1 1 0

Q1
1 1 1 0 0

Q2
1 1 0 0 0

Q3
1 0 0 0 0

= 0

DSL =

DSR = X

In the sequence 4 clock pulses logic o s are shifted left successively with each clock pulse . STEP : 4 . SHIFT LEFT LOGIC 1 S Set the Q0 Q1 Q2 Q3 to 0 0 0 0 by setting DSL input to logic 0 . Now switch DSL input to logic 1 and observe the shifting of logic 1 s to left as below . Observe the following outputs after each clock pulse and verify.

CONDITION MR = S0 S1 = 1 1 1

n CLOCK PULSES 0 1 2 3 4

Q0
0 0 0 0 1 Truth Table 4

Q1
0 0 0 1 1

Q2
0 0 1 1 1

Q3
0 1 1 1 1

= 0

DSL =

DSR = X

STEP : 5 . SHIFT RIGHT LOGIC 0 Set the Q0 Q1 Q2 Q3 to 1 1 1 1 by setting DSR input to logic 1 . Repeat step 4 and parallel load logic 1 s in all the 4 outputs . Change the logic inputs of DSR to logic 0 and then of S1 to logic 0 in the same sequence . Observe the following outpus after each clock pulse and verify . CONDITION MR = S0 S1 = 1 0 n CLOCK PULSES 0 1 2 3 4 = 1

Q0
1 0 0 0 0 Truth Table 5

Q1
1 1 0 0 0

Q2
1 1 1 0 0

Q3
1 1 1 1 0

DSL = X DSR = 0

STEP : 6 SHIFT RIGHT LOGIC 1 s Now at this condition of all 0 at the outputs switch DSR to logic 1 this will enable all logic as serial data and logic 1 s will be shifted successively with each clock pulse as shown below .Observe the following table and verify the outputs . CONDITION MR = S0 S1 = 1 0 n CLOCK PULSES 0 1 2 3 4 1 = 1

Q0
0 1 1 1

Q1
0 0 1 1 1

Q2
0 0 0 1 1

Q3
0 0 0 0 1

DSL = X DSR = 1

STEP : 7 . In the above steps for shift left or shift right operation ,(step 3 4 5 6 ) if both the S0 &S1 switches are forced to logic 0 , then shifting operation will cease and whatever is the output data it will freeze or hold . Observe this condition and verify .

CONDITION MR = S0 S1 = 1 0 0 = 0

n CLOCK PULSES 1 1 1 1 1 Truth Table 7

Q0

Q1 Q2 Q3

Previous data just before S0 &S1 both switched to logic 0 .

DSL =

DSR = 0

Result:- Verified the applications of the Universal shift register using IC 74194

Questions: 11. What is the universal shift register? 12. In which circuits shifting and rotating circuits are used? 13. Which flip-flops are used in shift registers? 14. Which flip-flop is universal flip-flop? 15. What is the difference between shifting and rotating data? 16. What is register? 17. What is meant by parallel in &parallel out Shift register? 18. State various applications of Shift register? 19. List the basic types of shift register in terms of data movement? 20. Determine the output status of a 4-bit SIPO shift register, after 3 clock pulses if the I/P terminal is held high?

PIN CONFIGARATION OF DIGITAL ICS