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VHDL Quick Guide

This document provides a quick reference guide for VHDL including: - Allowed character for identifier names and rules for naming - Data types including signals, variables, integers, and generic parameters - Logic, relational, arithmetic, and shift operators - Program structure including entities, architectures, processes - Conditional statements like if and case statements - Looping constructs like for loops - Assignment operators and port mapping The guide summarizes the basic syntax and concepts for working with the VHDL hardware description language.

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Martín Vázquez
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
122 views

VHDL Quick Guide

This document provides a quick reference guide for VHDL including: - Allowed character for identifier names and rules for naming - Data types including signals, variables, integers, and generic parameters - Logic, relational, arithmetic, and shift operators - Program structure including entities, architectures, processes - Conditional statements like if and case statements - Looping constructs like for loops - Assignment operators and port mapping The guide summarizes the basic syntax and concepts for working with the VHDL hardware description language.

Uploaded by

Martín Vázquez
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL Quick Reference Guide

189

Appendix E

VHDL Quick Reference Guide


Category Identifer Names Definition Can contain any letter, digit, or underscore _ Must start with alphabetic letter Can not end with underscore or be a keyword Case insensitive 0 = logic value 0 1 = logic value 1 Z = high impedance X = unknown value <base>#xxx# B = binary X = hexadecimal O = octal Associates an identifer name with a value that can be overridden with the generic map statement Assigns a value to a generic parameter signal (used to connect one logic element to another) variable (variables assigned values in process) integer (useful for loop control variables)
library IEEE; use IEEE.STD_LOGIC_1164.all; entity <identifier> is port( <port interface list ); end <identifier>; architecture <identifier> of <entity_name> is begin process(clk, clr) begin {{concurrent_statement}} end<identifier>;

Example q0 Prime_number lteflg

Signal Values

Numbers and Bit Strings Generic statement generic map Signals and Variables Types

35 (default decimal) 16#C# = 1100 X3C = B00111100 O234 = B010011100 generic ( N:integer := 8);

generic map (N => 16)


signal d : std_logic_vector(0 to 3); signal led: std_logic; variable q: std_logic_vector(7 downto 0); variable k: integer;

Program structure

library IEEE; use IEEE.STD_LOGIC_1164.all; entity Dff port( clk clr D : q : end Dff; is : in STD_LOGIC; : in STD_LOGIC; in STD_LOGIC; out STD_LOGIC );

Logic operators

not and or nand nor xor xnor

architecture Dff of Dff is begin process(clk, clr) begin if(clr = '1') then q <= '0'; elsif(rising_edge(clk))then q <= D; end if; end process; end Dff; z <= not y; c <= a and b; z <= x or y; w <= u nand v; r <= s nor t; z <= x xor y; d <= a xnor b;

190

Appendix E

Arithmetic operators

Relational operators Shift operators process

VHDL Quick Reference Guide (cont.) count <= count + 1; + (addition) q <= q 1; - (subtraction) * (multiplication) / (division) (not synthesizable rem (remainder) if a <= b then =, /=, >, <, >=, <= if clr = 1 then c = shl(a,3); shl (arg,count) c = shr(a,4); shr (arg,count) process (a) [<id>] process(<sensitivity list>) variable j: integer; {{process declaration}} begin begin j := conv_integer(a); for i in 0 to 7 loop {{sequential statement}} if(i = j) then end process [<id>]
y(i) <= '1'; else y(i) <= '0'; end if; end loop; end process;

if statement

case statement

for loop

if(expression1) then {{statement;}} {{elsif (expression2) then {{statement;}} }} [[else {{statement;}} ]] end if; case expression is (( when choices => {sequential statement;}} )) {{ }} when others => {sequential statement;}} end case; for identifier in range loop {{sequential statement} end loop; := (variable) <= (signal) instance_name component_name map (port_association_list);

if(clr = '1') then q <= '0'; elsif(clk'event and clk = '1') then q <= D; end if;

case s is when "00" when "01" when "10" when "11" when others end case;

=> => => => =>

z z z z z

<= <= <= <= <=

c(0); c(1); c(2); c(3); c(0);

zv := x(1); for i in 2 to 4 loop zv := zv and x(i); end loop; z <= zv;

Assignment operator Port map

z := z + x(i); count <= count + 1; port


M1 : mux21a port map( a => c(0), b => c(1), s => s(0), y => v);

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