ECE 171 Digital Circuits: Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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Minh HoangECE 171 Digital Circuits: Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
Uploaded by
Minh HoangECE171 DigitalCircuits
Prof.MarkG.Faust MaseehCollegeofEngineering andComputerScience
Lecture12
Topics
ModularDesign g AdderandSubtractor Design MultiplierDesign ALUDesign
TheHalfAdder
A0 + B0 CO1 S0 A0 B0 C01 S0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
S 0 = A0 B0 + A0 B0 = A0 B0 CO1 = A0 B0
HalfSubtractor
A0 B0 BO1 D0 A0 B0 B01 D0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0
D0 = A0 B 0 + A0 B 0 = A0 B 0 BO1 = A0 B 0
TheFullAdder
Consideracircuittoaddtwo4bitnumbers: A3 A2 A1 A0 + B3 B2 B1 B0 CO4 S3 S2 S1 S0 Truth table would have 8 inputs (28 = 256 rows) and 5 outputs, requiring 5 minimized functions (5 8-variable K-maps). But operation at each bit position (after A0/B0) is identical: COi Ai Bi Si bitslice
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+ COi+1
FullAdderTruthTable
CI A B 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 CO S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1
RippleCarryAdder
A1 A0 + B1 B0 CO2 S1 S0
ModularTwoBitAdder/Subtractor
XORApplication:TwosComplement
PropagationDelayinRippleAdder
AssumingSis implementedusing AND,OR,NOT S:Tpd d =3tp CO:Tpd =2tp
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PartitionCarryOutLogic
Settlingtimefornstagerippleadder ST=3tp +(n1)(2tp)=(2n+1)tp
SofMSBstage Cofremainingearliern1stages
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UsingHAforLSBStage
IfweuseHAfor1st stage(noCI) ST=3tp +(n2)(2tp)+tp =(2n)tp
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CarryLookAheadAdder
Con+1 logicnotdependentuponentirepriorstage(COn)logic
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G(carrygenerate)isdependentuponpreviousstagesabilityto generate acarry. Gn = An Bn P (carrypropagate)isdependentuponpriorstagesabilityto propagate acarr carry. Pn = An + Bn Acarryisgeneratedatastagei ifitisgeneratedbystageis inputs(Ai,Bi)orbyanypriorstageandpropagatedbyeach succeedingstage.
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CO1 = G0 + CI 0 P0 = G0
CO3 = G2 + CI 2 P2 = G2 + CO2 P2 = G2 + (G1 + G0 P 1) P 2 = G2 + G1 P2 + G0 P 1P 2
CO4 = G3 + CI 3 P3 = G3 + CO3 P3 = G3 + (G2 + G1 P2 + G0 P 1P 2) P 3 = G3 + G2 P3 + G1 P2 P3 + G0 P 1P 2 P 3
Gn = An Bn Pn = An + Bn
CO2 = G1 + CI1 P 1 = G1 + CO1 P 1 = G1 + G0 P 1
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CarryLookAheadAdder
Con+1 logicnotdependentuponentirepriorstage(COn)logic Uses:G0 throughGn1 andP1 throughPn1 SettlingTime=6tp (constant)for3ormorestages
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SpeedUpImprovement
RippleCarryAdder(n)StagesusingHAforLSB (2n)Tp CarryLookAheadAdder(n)Stages(usingSOP) 6Tp Speedupfornstageadder ((2n)Tp6Tp)/(2nTp) Assume4stages (2x4 6)/(2 ( )/( x4) ) 2/8 25%
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Wecandoevenbetter!
CO1 = G0 + CI 0 P0 = G0
CO3 = G2 + CI 2 P2 = G2 + CO2 P2 = G2 + (G1 + G0 P 1) P 2 = G2 + G1 P2 + G0 P 1P 2
CO4 = G3 + CI 3 P3 = G3 + CO3 P3 = G3 + (G2 + G1 P2 + G0 P 1P 2) P 3 = G3 + G2 P3 + G1 P2 P3 + G0 P 1P 2 P 3
Gn = An Bn Pn = An + Bn
CO2 = G1 + CI1 P 1 = G1 + CO1 P 1 = G1 + G0 P 1
Substituteandsimplify
Remember,wecanimplementanyfunctionasSOP Inthiscasetherearenoinverters 2tp Sumstillrequires3tp
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SpeedUpImprovement
RippleCarryAdder(n)StagesusingHAforLSB (2n)Tp CarryLookAheadAdder(n)Stages(usingSOP) 5Tp Speedupfornstageadder ((2n)Tp5Tp)/(2n)Tp) Assume4stages (2x4 5)/(2 ( )/( x4) ) 3/8 37.5%
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LimitstoSpeedUp
CarrygenerationG0 offirststagemustbe capableofdrivingallsucceedingstages Eachsucceeding gstage g requires q g gateswith increasingnumberofinputs(fanin) Gatecountincreaseswitheachstage
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ExpandableCarryLookAheadAdder
4Tp 7Tp
2Tp 5Tp
74LS83A&74LS283
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CarrySaveAdders (WallaceTreeSummingNetwork)
Addingmorethantwooperandswithfulladders(A,B,CI,CO) A0 B0 + C0 S10 CO11 + D0 S21 S20 CO21 + E0 S31 S30 CO32 CO31 + CO42_________ S42 S41 S40
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CarrySaveAdders
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MultiplierDesign
MxNbitmultiplier p requires q M+Nbitresult:2M x2N =2M+N Considera2bitx2bitbinarymultiplier 11 x11 11 +11 1001 multiplicand multiplier partial product 0 partial product 1 result A0 B0 A0xB0 A0B0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1
Truth T thtables t bl quickly i kl b becomeunmanageable bl usemodular d l approach h EverypartialproductcanbeobtainedfromanANDoperation Userippleorcarrylookaheadaddertoaddtwosetsofpartialproducts Usecarrysaveaddertoaddmorethantwosetsofpartialproducts
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Example:3bitx3bitMultiplier UsingRippleAdders
A2 A1 A0 x B2 B1 B0 P20 P10 P00 + P21 P11 P01 S40 S30 S20 S10 S00 + P22 P12 P02 R5 R4 R3 R2 R1 R0 multiplicand multiplier partial ti l product d t0 Pmn = Am x Bn partial product 1 partial sum 0 partial product 2 partial sum 1 (result)
9partialproducts(9ANDgates) 2rowsofadders
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MultiplierUsingRippleCarryAdders
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A2 A1 A0 Pmn = Am x Bn x B2 B1 B0 P20 P10 P00 + P21 P11 P01 S40 S30 S20 S10 S00 + P22 P12 P02 R5 R4 R3 R2 R1 R0
multiplicand multiplier partial product 0 partial product 1 partial sum p su 0 partial product 2 partial sum 1 (result)
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MultiplierUsingCarrySaveAdder
A2 A1 A0 x B2 B1 B0 P20 P10 P00 + P21 P11 P01 + P22 P12 P02 R5 R4 R3 R2 R1 R0 multiplicand multiplier partial product 0 partial product 1 partial sum 2 sum (result)
Pmn = Am x Bn
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MultiplierUsingCarrySaveAdder
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Pmn = Am x Bn
A2 A1 A0 x B2 B1 B0 P20 P10 P00 + P21 P11 P01 + P22 P12 P02 R5 R4 R3 R2 R1 R0
multiplicand multiplier partial product 0 partial product 1 partial sum p su 2 sum (result)
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ALUs ArithmeticLogicUnits
Computational heart of a computer M (mode) selects arithmetic or logic mode S (select) selects operations M S0 0 0 0 1 1 0 1 1 F and CO A+CI A+B+CI A OR B AB Comment Increment A if CI == 1 Add A+B with carry A OR B A XOR B
1 bit slice 1-bit li (because (b of f CO, CO capable bl of f being b i expanded) d d)
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ModularALUImplementation
M S0 0 0 0 1 1 0 1 1
F and CO A+CI A+B+CI C A OR B A B 33
ALUs ArithmeticLogicUnits
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HierarchicalImplementationof 16bitALU
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HierarchicalImplementationof 16bitALU
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HierarchicalImplementationof 16bitALU
16 16
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ALUs
32 bit ALU 32-bit
Typical ALU Operations
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