LC Tank Voltage Controlled Oscillator Tutorial

by Professor John Starr Hamel Introduction by Ryan Norris, Presented to the UW ASIC Analog Group and edited by Ryan Norris,

Waterloo, Ontario, Canada, 2005 c 2005

This tutorial was created from a set of hand written notes that were prepared by Professor John Starr Hamel at the University of Waterloo, Ontario, Canada for use in E&CE 439, an undergraduate course in Analog Integrated Circuits.

ii

Abstract
This tutorial provides an introduction to the fundamentals of LC tank voltage controlled oscillator analysis and design.

iii

Acknowledgments
I would like to thank Professor John Starr Jamel for allowing the UW ASIC Analog Group to utilize his tutorial within the UW ASIC Analog Group.

iv

Dedication
This tutorial is dedicated to the students of the UW ASIC Analog Group.

Contents
1 Introduction 2 LC Tank Voltage Controlled Oscillator Tutorial 2.1 Voltage Controlled Oscillator Analysis and Design . . . . . . . . . . 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2 Small Signal (a.c.) Analysis . . . . . . . . . . . . . . . . . . Design Constraints . . . . . . . . . . . . . . . . . . . . . . . Transistor Non-Idealities . . . . . . . . . . . . . . . . . . . . Determining Transistor Width W . . . . . . . . . . . . . . VCO Design Procedure . . . . . . . . . . . . . . . . . . . . . 1 4 4 6 12 13 16 19 20 23 25 29 33 42

Oscillator Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 2.2.2 Quality Factor Q of an Oscillator . . . . . . . . . . . . . . Dependence of Phase Noise on Q and Oset Frequency . . .

2.3 2.4

MOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET Models . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bibliography

vi

List of Figures
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 LC Tank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balanced NMOS VCO. . . . . . . . . . . . . . . . . . . . . . . . . . Balanced NMOS VCO with each tank represented by a series impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCO of Figure 2.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . Bandwidth of an LC tank oscillator. . . . . . . . . . . . . . . . . . . MOSFET parasitic elements. . . . . . . . . . . . . . . . . . . . . . . LC tank parasitic elements. . . . . . . . . . . . . . . . . . . . . . . MOSFET I-V characteristics. . . . . . . . . . . . . . . . . . . . . . Illustration of phase noise in the time domain. . . . . . . . . . . . . 4 5 7 8 9 14 15 18 21 22 23 24 25 25 27 28 30 30 31 32

2.10 Illustration of phase noise in the frequency domain. . . . . . . . . . 2.11 Calculation of Q from the frequency response. . . . . . . . . . . . . 2.12 LC tank VCO open-loop transfer function. . . . . . . . . . . . . . . 2.13 LC tank and phase function. . . . . . . . . . . . . . . . . . . . . . . 2.14 Phase noise in the signal path. . . . . . . . . . . . . . . . . . . . . . 2.15 Noise shaping in an oscillator. . . . . . . . . . . . . . . . . . . . . . 2.16 Nonlinear mixing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.17 Tuning characteristic for PMOS capacitor where Body, Drain and Source are connected together. . . . . . . . . . . . . . . . . . . . . . 2.18 MOS internal capacitors. . . . . . . . . . . . . . . . . . . . . . . . . 2.19 Fingered MOSFET gate. . . . . . . . . . . . . . . . . . . . . . . . . 2.20 IMOS C-V characteristic. . . . . . . . . . . . . . . . . . . . . . . . . vii

2.21 MOSFET transistor cross section and symbols.

. . . . . . . . . . .

33 34 35 35 37 38 39 40

2.22 MOSFET energy band diagram. . . . . . . . . . . . . . . . . . . . . 2.23 3D MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.24 Detailed 3D MOSFET, and MOSFET output Drain characteristics. 2.25 MOSFET small signal equivalent circuit. . . . . . . . . . . . . . . . 2.26 NMOS depletion capacitance. . . . . . . . . . . . . . . . . . . . . . 2.27 NMOS capacitances. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.28 Gate-Drain overlap region. . . . . . . . . . . . . . . . . . . . . . . .

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List of Tables
1.1 List of ideal VCO specications. . . . . . . . . . . . . . . . . . . . . 2

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Chapter 1 Introduction
The Analog Group, of the UW ASIC Group, has decided to concurrently design two dierent VCO (Voltage Controlled Oscillator) topologies. This introduction provides some of the reasoning for why the Analog Group has chosen to design VCOs that have the ring oscillator and the LC tank topology. There are two types of VCOs that one may choose to design: 1) waveform oscillators 2) resonant oscillators. Waveform oscillators: 1) ring oscillator topology 2) relaxation oscillator (which has poor phase noise performance). Resonant oscillators: 1) LC tank oscillator topology 2) crystal oscillator (which is neither integrated nor tunable). Ideally a given VCO topology would be able to meet all of the specications listed in Table 1.1. 1

Chapter 1: Introduction

Table 1.1: List of ideal VCO specications. 1) 2) 3) 4) 5) 6) low noise low power integrated wide tuning range small die area occupancy high frequency (GHz)

As discussed below, it is unlikely that either the ringVCO (ring oscillator VCO) or LCVCO (LC tank VCO) topologies can meet all of these specications. Through a comparison of ringVCOs and LCVCOs, the following advantages and disadvantages may be formulated. RingVCO advantages: 1) highly integrated in VLSI 2) low power 3) small die area occupancy 4) wide tuning range. RingVCO disadvantages: 1) As frequency increases phase noise and jitter performance degrades. LCVCO advantages: 1) outstanding phase noise and jitter performance at high frequency. LCVCO disadvantages: 1) contains an inductor and a varactor (variable capacitor) which are large area components, and thus is not as suitable for VLSI

Chapter 1: Introduction

2) high power consumption 3) occupies a large die area 4) small tuning range. Clearly, the ringVCO is most suitable for low power, highly integrated applications that require a large tuning range and a low die space area. In contrast, the LCVCO out performs the ringVCO in low noise applications. For mobile wireless applications one desires low power, hence the ringVCO may be of choice. However, wireless applications require outstanding noise (phase noise and jitter) performance at high frequency, hence the LCVCO may be of choice. Having said that, there may be specic applications where either the ringVCO or the LCVCO topology may be optimized to perform suciently well. The aforementioned advantages and disadvantages should hold true for the fabrication technologies (0.13m CMOS, etc) that are predicted, by IRTS road map, to be in use in the future. Hence, a design decision - to utilize either a ringVCO or a LCVCO - that is based on the above advantages and disadvantages should be a valid decision in the future when silicon CMOS fabrication technologies scale further into the deep deep sub-micron regime. This analysis illustrates that to be able to target the most diverse range of applications, one should be knowledgeable in the design and optimization of both the ringVCO and LCVCO topologies. The forthcoming tutorial provides fundamental information on the analysis and design of a LCVCO. Ryan Norris, 2005 UW ASIC Analog Group leader

Chapter 2 LC Tank Voltage Controlled Oscillator Tutorial

2.1

Voltage Controlled Oscillator Analysis and Design

An LC tank VCO can be thought of as two 1-port networks connected together.

Figure 2.1: LC Tank.

One 1-port represents the frequency selective tank where the oscillations occur and the other 1-port represents the active circuit that cancels the losses in the tank. Oscillations can occur when:

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

i) the negative conductance of the active network cancels out the positive conductance (loss) of the tank ii) the closed loop gain has zero phase shift. Conditions i) & ii) above amount to a closed loop gain greater than or equal to unity magnitude with no imaginary component. The rst step in designing an oscillator is to choose a circuit topology or type. For this example a balanced NMOS VCO will be chosen.

Figure 2.2: Balanced NMOS VCO.

The only losses being assumed in Figure 2.2 are those associated with the inductor. In reality there would also be losses associated with the variable capacitors (varactors) and the MOSFETs (the active devices). In practical integrated VCOs the inductors are on-chip spiral inductors with low quality factor that dominates the losses of the VCO tank. The quality factor QL of the inductor is given by

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

QL =

o L R

(2.1)

where o is the oscillation frequency [rad/s] L is the value of the inductance [H] R is inductors equivalent series resistance []. QL in practical silicon RF IC processes ranges from 5 to 10. Values of on-chip inductances range from 0.1 nH to 10 mH in practical RF IC processes. It can be shown that the oscillation frequency of the circuit shown in Figure 2.1, assuming ideal varactors and MOSFETs is given by 1 LC
2

o = 2

R2 C L

(2.2)

It can also be shown, under the same set of assumptions that the gm of each MOSFET must be gm RC L (2.3)

for oscillation to occur.

2.1.1

Small Signal (a.c.) Analysis

The oscillator is essentially a dierential pair that have been cross-coupled in a positive feed back conguration.

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

Figure 2.3: Balanced NMOS VCO with each tank represented by a series impedance. The input of each transistor in the dierential pair has been connected to the output of the opposite transistor. The output voltage vo = v1 v2 is a dierential output signal. v1 which is the input signal to M1 is also the single ended output of M2 . Each individual transistor in the pair is essentially a common-source amplier with a complex, tuned load comprised of a lossy inductor in parallel with a capacitor. The Zs load is called a tank circuit since it holds the oscillating energy like a tank at the oscillation frequency. The two separate tanks form a dierential load to the dierential pair where node A remains, to rst order, at the same potential during oscillations. Node A is a virtual a.c. ground point in the same manner as the virtual ground that exists in a normal dierential amplier.

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

Node A is not a complete a.c. short, however, since, ideally, there should be an innite a.c. impedance between this node and the power supply rail VDD . A proper active current source must be designed to provide the d.c. biasing to node A and hence M1 and M2 as well as maintaining a high a.c. impedance between node A and the supply rail. If the a.c. impedance between node A and VDD is not high, then RF energy will leak out of the tanks into the supply rail destroying the oscillations.

Figure 2.4: VCO of Figure 2.3.

For small signal (a.c.) analysis the current source of Figure 2.3 behaves as an open circuit. The VCO of Figure 2.3 can then be represented by Figure 2.4 as two 1-port networks. Assuming ideal MOSFETs (i.e. no parasitic resistances or capacitances), the entire dierential amplier can be modeled as a negative resistance R (or m ). negative conductance Gm = g2 The two tank circuits appear in series where ZT = 2Zs = RT + jXT = 2(Rs + jXs ) (2.4)

The oscillation condition requires that the closed loop gain (around the two 1-ports) be of at least unity magnitude and zero phase angle. The zero closed loop phase condition implies that at the frequency of oscillation, o , XT (o ) = 0.

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

The magnitude of the amplier negative resistance must be at least as large as RT (o ), the total resistive or real loss of the two tanks.
1 m setting XT (o ) = 0 determines o and setting | R | = | g2 |= the minimum gm of each MOSFET for oscillation to occur. 1 RT (o )

determines

In general, the negative resistance of the dierential pair must overcome all real resistive losses in the oscillator circuit. An ideal oscillator has no losses with innite voltage swing at precisely one frequency. The presence of losses results in a nite voltage swing over a narrow spread of frequencies. How ideal an oscillator is can be directly related to the quality factor of the tank.

Figure 2.5: Bandwidth of an LC tank oscillator.

At resonance, a pure LC tank with no losses presents innite impedance to an applied signal across the tank. This implies that the output voltage across the tank will be innite if the tank is driven by a source with innite impedance. If the tank has real losses, however, even if it is driven by an innite impedance source (i.e. Rin = 0), the losses can be modeled as if the lossless tank had a nite impedance load, Rp = .

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

10

The nite impedance load Rp will de-Q the tank resulting in a nite output voltage. One denition of quality factor or Q is Q= o 1 2 (2.5)

as per Figure 2.5. It can be shown that Equation 2.5 is also equal to Qloaded = Rp o L (2.6)

where o is the resonant frequency of the lossless tank wo = 2 1 LC (2.7)

Equation 2.6 is known as a loaded Q. The loaded Q can be related to something called a component Q where the parallel resistance, Rp , modeling the total losses of the tank can be related to the individual losses of the inductor and capacitor components themselves. The component Q of the inductor is given by QL = o L R (2.8)

where R is the series resistance of the inductor.

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11

The component Q of the capacitor is given by QC = 1 Ro C (2.9)

where R is the series resistance of the capacitor.

The total loaded Q can then be estimated as 1 Qloaded = 1 1 + . QL QC (2.10)

Often capacitors have much higher component Qs than inductors in silicon integrated processes (though this may not be the case if varactors are used as the capacitor) such that QL << QC Then QL Qloaded . One can then write Qloaded = lossy tank.
Rp o L

(2.11)

= QL =

o L R

= Q as the quality factor of the

= Rp =

o L 2 (o L)2 =( ) R = Q2 R R R

(2.12)

where R is the series resistance of the inductor, Rp is the equivalent parallel resistance of the lossy tank, and Q is the quality factor of the lossy tank the component Q of the inductor the loaded Q of the lossy tank (under the assumption made thus far).

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12

From Equation 2.12, the total nite a.c. impedance shunting an otherwise perfect LC tank can be related to the series resistance of the inductor and the component Q of the inductor. It is desirable to have as large of an Rp as possible for a good oscillator. In practice, an RF IC designer sets the value of L required for an oscillator, and then attempts to layout the inductor for maximum component Q so that Rp is as high as possible. Generally over a reasonable range of on-chip inductors the maximum Q possible is more or less independent of the value of inductance provided the particular inductor layout is optimized for maximum Q given the technology being used. Also, the maximum Q is more or less independent of frequency over a fairly large frequency range since inductor layout can also be optimized for dierent frequencies of operation. For the above reasons, one usually attempts to determine the maximum reasonable Q one can expect over a range of inductance values and frequency ranges for a given technology. Then this value is used as a constant in the initial design process. Typical values of Q that can be obtained in todays deep sub-micron processes (silicon CMOS) for on-chip inductors range from 5 to 10 for inductor values ranging from 0.1 to 10 nH and frequencies ranging from 1 to several GHz.

2.1.2

Design Constraints

VCOs are generally designed for minimum phase noise under constraints of d.c. power dissipation, tuning range, output voltage swing and die area. Usually on-chip spiral inductors are utilized for this type of VCO. These inductors usually dominate the chip area required ranging in diameter from 100 to 500 m. The d.c. power dissipation is given by

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13

Vsupply Ibias Pdissipation max

(2.13)

The magnitude of the output voltage at the drains of the NMOS transistors is governed, to rst order, by the a.c. impedance of the lossy tank: Vtank Ibias Rp where Rp = QL o L and Vtank is the single-ended peak-to-peak voltage swing at either the + or - output node of the VCO before any output buering. The tuning range of a VCO is required to be in excess of a certain minimum percentage of the center frequency, o . The LC tank is made tunable by implementing the C of the LC tank using a varactor (variable capacitor). The varactor is designed to be adjustable over some range Ctank min to Ctank max . Assuming that o
1 2 LC

(i.e. that of an ideal tank) then, 1 (max )2 ; Ltank Ctank max = 1 (min )2 (2.14)

Ltank Ctank min =

where (max min )/o = fractional tuning range and (max + min )/2 = o The minimum criterion for oscillation is that the closed loop gain, , is at least unity. In practise designers set the gm of the NMOS transistors so that exceeds the absolute minimum value of 1 such that the minimum designed becomes min > 1. An min of 2 or 3 is often used. Finally, assuming that the on-chip spiral inductors are limiting chip-area one usually determines the inductor diameter d such that it is some maximum possible value (d dmax ).

2.1.3

Transistor Non-Idealities

MOSFETs have many parasitic capacitances and resistances that determine transistor performance.

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14

Figure 2.6: MOSFET parasitic elements. Parasitic resistances increase the losses in the VCO requiring a higher gm compared to the ideal transistor case. Parasitic capacitances can combine with the tank capacitance, C , reducing the oscillation frequency. Therefore the tanks C must be decreased to allow for these parasitic transistor capacitances. Parasitic resistances will also contribute thermal noise increasing oscillator phase noise. rds is not a real resistance contributing noise, but results from channel path length modulation decreasing the a.c. output resistance of the MOSFET and partially de-Qs the LC tank. As shown in Figure 2.7 a) and b), ignoring the eects of gate resistance rg , it can be shown that rds appears in parallel with Rp if node A can be assumed to experience no a.c. voltage uctuations during oscillation (i.e. node A is a virtual ground). All parasitics can be associated with the tank as shown in Figure 2.7 leaving ideal NMOS transistors in the active 1-port circuit. The oscillation frequency o will them be altered such that

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

15

Figure 2.7: LC tank parasitic elements.

o =

1 L(C + Cgs + 4Cgdo )

R2 (C + Cgs + 4Cgdo ) L

(2.15)

In the above equation it can be seen that the transistor capacitances more or less simply add to the tank capacitance, C , requiring a decrease in C compared to the ideal case for a given o . The start-up gm condition also changes such that the absolute minimum gm required for oscillation becomes:

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

16

gm

1 R(C + Cgs + 4Cgdo ) + rds L

(2.16)

Equation 2.16 states the important result that the bigger the MOSFETs the higher the gm must be to achieve oscillation.

2.1.4

Determining Transistor Width W

The NMOS transistors must be biased and laid out such that the required gm is obtained to overcome all losses including those of the tank and the transistors themselves. The above amounts to determining the Vgs (the bias) and W for a given minimum transistor channel length Lchannel , which is xed for a given process technology. For modern CMOS processes Vgs is selected such that Vgs Vt 0.4 to 0.5, where Vt is the MOSFET threshold voltage. If Vgs Vt is too high, gm is degraded due to eects such as mobility degradation and saturate velocity eects for channel carriers. If Vgs Vt is too small then W must be very large such that the transistor will not t into the require area, or such that gm is always too large according to Equation 2.16 too obtain. To estimate the required gm one must iterate on device equations for Id , gm , rds , Cgs , Cgdo and the equation for start-up criterion of Equation 2.16. Assume the MOSFETs are in saturation. A basic Level 1 MOS model gives: Idsat = gm kp W (Vgs Vt )2 = (Vgs Vt ) 2 Lchannel 2 W dIdsat = kp (Vgs Vt ) dVgs Lchannel (2.17)

gm =

(2.18)

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17

rds =

1 Idsat

(2.19)

2 Cgs = Cox W Lchannel ; Cgdo = CGDo W 3

(2.20)

Certain model parameters must be determined from the design kit for the CMOS process including: Lchannel = min channel length Vt = threshold voltage kp - models channel length modulation Cox = tox /
ox ,

tox = gate oxide thickness

GGDo = gate-to-drain capacitance per unit gate width W . Some of the model parameters must be determined for a combination of other parameters. Begin the iteration process assuming ideal MOSFETs and including only the tank losses due to R. gm = RC L (2.21)

(once C and L are known - see design procedure steps) from Equation 2.18 we have W = gm Lchannel kp (Vgs Vt ) (2.22)

then calculate Idsat , rds , Cgs , Cgdo from Equations 2.17 to 2.20.

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Figure 2.8: MOSFET I-V characteristics. Idsat is the drain current under saturation conditions. A higher gm will be required for non-ideal case using gm = 1 R(C + Cgs + 4Cgdo ) + rds L (2.23)

W is then increased according to Equation 2.22, etc. until convergence is obtained. Tank C can then be adjusted to obtain the require o from Equation 2.15 once nal values of Cgs , Cgdo , etc., are known. The above method is only approximate and W and gm will have to be adjusted once realistic higher level NMOS models are used (i.e. BSIM3) and transistor layout is completed since actual layout will aect Cgs and Ggdo . The above assumes that one will use a very wide single stripe MOSFET. In reality multiple nger MOSFETs are used to obtain a total W to reduce series gate resistance and to provide a more compact layout with lower parasitic capacitances.

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Actual gm should be above the minimum estimated using Equation 2.23 by some safety factor min (e.g. 2 or 3). Therefore, incorporate this safety factor into the iteration from the beginning.

2.1.5

VCO Design Procedure

Certain design specications must be given: a) max d.c. power dissipation = Vsupply Ibias b) min output voltage swing (single-ended) = Vtank c) tuning range in percentage = d) min > 1 e) chip area f) Frequency of operation (o ) The goal of the design is then to develop a VCO that meets the above constraints with minimum phase noise. An alternative strategy may be to design a VCO with a pre-specied phase noise but where the d.c. power dissipation is minimized. Design Procedure Steps 1) Set Ibias =
Pd.c. max Vsupply max min o

100%

2) Determine max QL of inductors for a given process at required frequency o . This can be determined in may ways including i) already known from previous design experience in that particular process ii) read from model elements in design kit iii) determined through exhaustive design and optimization of inductor using electromagnetic simulation packages iv) measured data taken from test inductors already fabricated in the same process.

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3) Using Vtank = Ibias Rp = Ibias o LQL , set L so that Vtank is at the minimum required voltage swing for the design. Ibias , o and QL area already known. Caution: values of L must be chosen such that it is in a practical value range to be fabricated as well as being at a value that results in a practical value of capacitance, C , for the varactor.
2 1 oL 1 RLC where R = = eective series resistance of in4) Using o = 2 QL LC ductor, calculate the required value of C for the LC tank with o being the center frequency of the VCO. 2

5) Given the minimum closed loop gain min > 1 calculate the minimum transconductance of each NMOS transistor gm such that gm = min RC L 6) Take transistor non-idealities into account to arrive at a new gm and also a transistor width, W , *as per Prof. Hamels E&CE 439 lecture notes*.

2.2

Oscillator Phase Noise

Noise is injected into an oscillator by the devices that constitute the oscillator itself including the active transistors and passive elements. This noise will disturb both the amplitude and frequency of oscillation. Amplitude noise is usually unimportant because non-linearities that limit the amplitude of oscillation also stabilize the amplitude noise. Phase noise, on the other hand, is essentially a random deviation in frequency which can also be viewed as a random variation in the zero crossing points of the time-dependent oscillator waveform. Let (t) = Acos o t + n (t) where A is the noiseless oscillator amplitude, o is the oscillator frequency, n (t) is the phase noise, (t) is the oscillator output signal.

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21

Figure 2.9: Illustration of phase noise in the time domain. For Small n (t) (t) = Acos o t + n (t) = A cos(o t)cos(n (t)) sin(o t)sin(n (t)) Acos(o t) An (t)sin(o t) since cos(n (t)) cos(0) = 1 and sin(n (t)) n (t) for small n (t) the spectrum of the noise noise n (t) is eectively translated to the oscillation frequency o i.e. the phase noise signal is amplitude modulating a sinusoid signal of frequency o that is in turn superimposed on the ideal oscillator itself. An oscillator, however, is a frequency selective (or narrow band, high quality factor) circuit and will tend to reject out of band (i.e. frequencies oset from o ) signals to some degree. This rejection increases at larger osets from o . As a result, the eect of the noise sources is to produce skirts on either side of the ideal impulse function of the oscillator in the frequency domain.

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Figure 2.10: Illustration of phase noise in the frequency domain. To measure or quantify phase noise, one considers a unit bandwidth at an oset with respect to o , calculates the noise power in this bandwidth, and divide the result by the average carrier power. e.g. carrier power = -2dBm, noise power measured in a 1kHz bandwidth at an oset of 1MHz = -70 dBm 0 dBm = 1 mW of power, # dBm
in watts ) = 10log10 ( P ower 103 watts

= 10log10 (P ower in mW ) -70dBm = 10log10 (P ower in mW )) 1010 W noise power in 1Hz bandwidth = 100dBm = = 70dBm P = 107 mW =

107 103

= 1010 mW/Hz 10log10 (1010 ) =

Dividing by carrier power amounts to adding 2dBm phase noise = -100 - (-2) = -98 dBc/Hz dBc means in dB with respect to carrier power.

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2.2.1

Quality Factor Q of an Oscillator

Phase noise of an LC oscillator depends on the Q of the LC tank circuit. For an LC tank, Q is an indication of how much of the energy is lost as it is transferred from the capacitor to the inductor and vice versa. Three Denitions of Q 1) One denition of Q denes it as:
energy stored per cycle 2 energy dissipated

2) Q can also be dened as the sharpness of the magnitude of the frequency response

Figure 2.11: Calculation of Q from the frequency response.

3) Q can also be dened with respect to the phase of the open-loop transfer function ( ) at the resonance of the LC tank in an oscillator Q=
o d( ) | d | 2

at = o

where o = resonant frequency

Chapter 2: LC Tank Voltage Controlled Oscillator Tutorial

24

Figure 2.12: LC tank VCO open-loop transfer function. H (j ) = Z (j ) = open-loop transfer function
(Z (j )) ) (j ) = tan1 ( Imag Real(Z (j ))

1 Z

= jC +
1

1 jL

1 Rp

= j (C

1 ) L

1 Rp

Z=

1 1 j (C L )+ R p

1 1 j ( L C )+ R

p p

1 1 2 ((C L ))2 +( R )

(j ) = tan1 ( L 1
d(tan1 u) dx

Rp

) = tan1 ( Rp (1 L

2 LC )

) = tan1 [Rp (L)1 (1 2 LC )]

use

1 du 1+u2 dx

d d

1 [ Rp2 (1 Rp 1+( L (1 2 LC ))2 (L) 2 LC = 0 1 o

2 LC ) 2 LC Rp ] L

o =

1 2 LC

d | d =o

= 2CRp = o CRp =
Rp XC

o d | | 2 d =o

where XC =

1 o C

at resonance XL = XC where XL = o L Q=
o d | | 2 d =o

= o CRp =

Rp o L

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25

Figure 2.13: LC tank and phase function. For steady state oscillation, the total phase shift around the feedback loop must be zero. If the oscillator frequency deviates slightly, say due to noise injection, then the larger the change in the loop phase the greater the tendency for the oscillator to return to its center frequency. The open-loop Q is a measure of how much the closed-loop system opposes variations in the frequency of oscillation.

2.2.2

Dependence of Phase Noise on Q and Oset Frequency

Phase Noise in the Signal Path

Figure 2.14: Phase noise in the signal path.

Y (s) = H (s)(X (s) + Y (s))

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26

Y (s)(1 H (s)) = H (s)X (s)

H (s ) 1 H (s )

In the vicinity of the frequency of oscillation = o + , H (j ) can be approximated by the rst two terms if its Taylor series expansion H (j ) H (jo ) + dH d [using f (x) = f (a) + f (a)(x a) where x = , a = o , x a = o = ]
Y (j ) X (j )

H (jo )+ dH d 1(H (jo )+ dH ) d

H (jo ) = +1 = closed-loop gain of the oscillator = one criterion for oscillation

+ )

1+ dH d dH d

1 for small and H not changing very much from unity assuming that dH d over a d change in frequency
Y (o X

+ )

1 dH d 1 |2 ( )2 | dH d

Y |X (o + )|2

= the factor by which noise introduced into the signal path is multiplied when it appears at the output of the oscillator. H (j ) = |H |ej expressed in polar form
dH d

d|H | j e d

d j + j |H | d e

|H | 2 d 2 and | dH |2 = | dd | + | d | |H |2 d

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27

for an LC oscillator

since the Q is relatively high, |H | is close to unity and d|H |/d cannot be large for oscillation to be sustained since |H | must remain close to unity.
Y |X (j )|2 = noise transfer function 1 d 2 ( )2 | d |

d 2 2 2 2 | = ( )Q = | d o

4 2 2Q o

Y |X (j )|2 =

1 ( o )2 4Q2

Known as Leesons Equation

Noise Shaping in Oscillators

Figure 2.15: Noise shaping in an oscillator. Therefore, the phase noise of an oscillator is proportional to 1/Q2 and 1/( )2 . Other Phase Noise Factors A physical principle known as the equipartition theorem states that the energy of an oscillator tends to distribute itself equally between the dierent modes of the oscillator.

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28

the phase noise is typically 1/2 of that given above since the Leesons equation accounts for both amplitude and phase noise. Phase Noise Also Depends On a) magnitude of noise source X (j ) b) amplitude of power in oscillator itself that is the useful noiseless power of the oscillator c) nonlinearities resulting in noise folding where noise at higher frequencies are down-converted through self-mixing mechanisms to the oscillation frequency

phase noise o 2 1 ) Q2 ( spectral density

nonlinear noise f olding

oscillator component noise power signal power

Noise from nonlinear mixing arises when odd-order nonlinearity in the amplitude leads to intermodulation between and injected noise component at a frequency n and the oscillator carrier creating another component at 2o n .

Figure 2.16: Nonlinear mixing.

Assuming noise from the active MOSFETs dominates, noise power of the MOSFETs is proportional to gm of the MOSFETs which is proportional to Idrain which is proportional to Ibias

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29

The larger the inductor of the LC tank, the larger the voltage swing, Vtank , since Vtank Ibias Rp = Ibias o LQ where Q =
Rp o L

Rp = o LQ.

oL Assuming that Q is limited by the losses of the inductor where Q = , Rs = Rs series resistance of the inductor, ar larger inductor will simply increase Rs making Q approximately constant.

Vtank increases as L increases for constant Q and o Larger Vtank = larger nonlinearities associated with nonlinear voltage dependent components such as varactors and active transistors = more noise folding or more mixing. For Minimum Phase Noise 1) make Q as high as possible 2) make Ibias as large as is allowed or design for power dissipation specications 3) use minimum gm of MOSFETs to satisfy startup condition, gm (min ) RC , L where min is a safety factor (usually 2 or 3). 4) use minimum L such that startup condition is still satised and such that minimum Vtank value is attained according to specications.

2.3

MOS Varactors
o

in accumulation: CM OS = Cox =

tox

W L = Cmax

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30

in depletion: CM OS =

Cox Cdep Cox +Cdep

Cmin where Cdep =

sW L Wm

, Wm =

2 s (2F +VSB ) qNsub

Figure 2.17: Tuning characteristic for PMOS capacitor where Body, Drain and Source are connected together.

Figure 2.18: MOS internal capacitors. Practical Cmax /Cmin ratios are in the range of 2 taking parasitic device capacitances into account that do not vary strongly with bias. Designing a PMOS Varactor 1) determine Cmax /Cmin ratio required for design: fractional tuning range =
fmax fmin fo

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31

where fo = center oscillator frequency = fmax

1 2 Ltank Cmax

Cmax Cmin

2 fmax 2 fmin

2) MOS varactor layout considerations a) use channel length Lmin = minimum available L for maximum varactor quality factor Q b) determine MOS gate total width, W , using Cmax =
o

tox

W L = W =

tos L ox

c) layout varactor using multi-nger gate to reduce gate series resistance such that Q of varactor is reasonably high.

Figure 2.19: Fingered MOSFET gate.

Qmin =

1 o Cmax Rg

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32

1 where Rg = total gate a.c. series resistance = (Rpoly / ) W , assuming that the L n2 gate contact is composed of polysilicon with sheet resistance Rpoly / , and n = # of ngers and assuming gate is connected from one end.

If the gate is contacted from both ends then divide above formula by 2. For balanced dierential structures, layout two varactors for best matching. For LC tank oscillators, a high Q for the varactor would be where Qvar e.g. Qvar = 40 to 50 when Qinductor = 10. An Inversion Mode MOS (IMOS) Capacitor Qinductor ,

Figure 2.20: IMOS C-V characteristic. If the Body contact (B) of a PMOS varactor is tied to the most positive voltage (e.g. VDD ), then the PMOS varactor will be prevented from entering the accumulation mode. An inversion mode MOS capacitor is more monotonic with respect to dependence of CM OS on applied tuning voltage. For large signals, which exist during operation of a VCO, the eective capacitance of the MOS varactor that determines the VCO frequency is actually an average of the instantaneous CM OS over the signal swing.

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33

= An IMOS varactor will have a larger eective tuning range compared to the conventional PMOS varactor where the Body , Source and Drain are tied together.

2.4

MOSFET Models

Figure 2.21: MOSFET transistor cross section and symbols.

Large Signal Model for MOSFET Vt = threshold voltage = ms + 2f +

Qss Cox

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34

where ms is the work function dierence between gate and body, f represents the strong inversion condition, Qb is the bulk depletion charge and Qss is the interface charge due to defects in gate oxide and at oxide-channel interface.

Figure 2.22: MOSFET energy band diagram.

Vt = Vto + ( 2 2f + VSB

2f )

where Vto is the threshold voltage for VSB = 0, is the gamma factor, and VSB is the source to body bias body eect. Qb = =
2
2

2q s NA (2f + VSB )
A = VT ln( N ) ni

2q s NA ; f Cox

NA = body doping; s 1012 F/cm for Si; ni =intrinsic carrier concentration ox 1.5 1010 cm3 ; Cox = Gate oxide capacitance per unit Gate width, W , = tox ; ox = permittivity of oxide (SiO2 ) = (3.9)(8.85 1014 ) F/cm= r o ; tox = Gate oxide thickness (typically 100s of A).

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35

Figure 2.23: 3D MOSFET.

Figure 2.24: Detailed 3D MOSFET, and MOSFET output Drain characteristics.

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36

Lef f = Ldrawn 2Xl Xd Xl = lateral diusion of Source and Drain under Gate Xd = space-charge-layer width of Body-Drain reverse-biased diode under Gate. IDS =
kW [2(VGS 2Lef f 2 Vt )VDS VDS ]

linear region (VDS < VGS Vt )

where k = n Cox =

n ox , tox

n = channel mobility.

When channel potential at drain end of inversion channel under Gate reaches VGS Vt due to VDS , the channel becomes pinched-o at this point onwards towards the Drain. Hence, for VDS VGS Vt , pinch-o occurs and ideally the Drain current IDS becomes independent of VDS such that: IDS =
kW (VGS 2Lef f

Vt )2 for VDS VGS Vt .

As VDS increases beyond VGS Vt , the pinch-o point of the channel moves towards the Source shortening the channel length Lef f causing an increase in IDS To model this: where =
1 ; VA VA

IDS =

kW (VGS 2L

Vt )2 (1 + VDS )

for VDS VGS Vt

= Early voltage.

Small Signal for MOSFET in Saturation Recall: Vt = Vto + ( 2 2f + VSB =

2f )

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37

IDS =

Vt )2 (1 + VDS ) in saturation

k = n Cox VA =
1

ID ID /VDS

IDS is a function of both VGS and VBS (since IDS is a function of Vt and Vt is a function of VBS ). Note: VBS = VSB . The small signal model will possess two transconductance generators.

Figure 2.25: MOSFET small signal equivalent circuit.

gm = gmb =

IDS VGS

kW (VGS L

Vt )(1 + VDS )

kW (VGS L

Vt ) =

2k

W I L DS

if VDS

IDS VBS

W Vt = kL (VGS Vt )(1 + VDS ) V BS

Vt = Vto + ( 2 2f VBS

2f )

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38

2f VBS = 2
2

2f +VSB

Wm = =
2

2 s (2f +VSB ) qNA

2q s NA Cox
s

Cdep =

Wm

Figure 2.26: NMOS depletion capacitance.

= 2
2

2f +VSB

2q s NA Cox

1 2

2 s 1 qNA Wm

1 s Wm Cox

Cdep Cox

or

Vt VBS

= Cdep = ox

where Cdep = depletion layer capacitance below Gate oxide in channel region. gmb =
2 W Vt W = = kL (VGS Vt )(1+VDS ) V = kL (VGS Vt )(1+VDS ) BS 2 2 2f +VSB 2 k (W/L)IDS k (W/L)(VGS Vt )(1+VDS ) = assuming VDS 1. 2 2 IDS VBS 2f +VSB 2(2f +VSB )

Using gm =

kW (VGS L

Vt )(1 + VDS ),

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39

gmb gm

(VGS Vt )(1+VDS )

Vt = V BS

gmb gm

= 2
2

2f +VSB

==

Cdep Cox

( usually ranges from 0.1 to 0.3) Note: gmb arises from the Body being held at a constant voltage and a small signal being applied to the Source.
ID 1 W ro = ( V ) = ( k (VGS Vt )2 )1 = (IDS )1 = 2 L DS a.c. output resistance 1 IDS

VA ID

where VA =

Cgs = the only intrinsic capacitance while all others are considered parasitic. Csb = the parasitic depletion-region capacitance between the substrate and Source. Cdb = the parasitic depletion-region capacitance between the substrate and Drain.

Figure 2.27: NMOS capacitances.

qC
2

1+

dbo VDB o

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40

Cgb = capacitance between Gate and substrate that models parasitic oxide capacitance between Gate contact materials and substrate outside the active device area. - is a constant capacitance - models coupling between polysilicon, metal interconnects and substrate Cgs and Cgd Capacitances
::::::::::::::::::

In ohmic region of device operation: Cgs = Cgd = 1 C WL 2 ox

::::::::::::::::::::::

In saturation region of device operation: i) Cgd consists of a constant parasitic oxide-capacitance due to Gate overlap of the Drain region.

Figure 2.28: Gate-Drain overlap region.

- intrinsic portion of Cgd 0 in saturation since VD (Drain voltage) has little inuence on channel charge beneath Gate. C WL ii) Cgs = 2 3 ox Transition Frequency, fT Assuming that the input capacitance is dominated by Cgs one can write fT =
1 gm 2 Cgs

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41

by comparison to the formula for a bipolar transistor. Substituting for gm and Cgs (using gm = k Cgs = 2 C W L): 3 ox
W (VGS L

Vt ) = n Cox W (VGS Vt ) and L

fT (M OSF ET ) =

1 gm 2 Cgs 1 n Cox W (VGS Vt ) = 2 L Cgs n Cox W 3 1 = (VGS Vt )[ ] 2 L 2 Cox W L 3 n = (VGS Vt ) 2 2L2 1 2F 1

fT max (BIP OLAR) = =

2 2DB n 1 n =2 V 2 T 2 WB

where Dn = VT n . Comparing:

fT (M OSF ET ) =

3 n (VGS Vt ) 2 2L2 n fT (BJT ) = 2 V 2 T 2WB

Bibliography
[1] P. Andrenani and S. Mattison, On the use of MOS varactors in RF VCOs, IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 908910, June 2000. [2] D. Ham and A. Hajimiri, Concepts and methods in optimization of integrated LC VCOs, IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 896909, June 2001. [3] J. R. Smith, Modern Communication Circuits, Chapter 7, 2nd ed. Hill, 1986. McGraw-

[4] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, Chapter 6. McGraw-Hill, 1995.

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