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Vlsi Signal Processing

The document outlines the units of the LTPC 3003 course which covers various digital signal processing and analog VLSI design topics. Unit I introduces DSP systems and algorithms as well as pipelining and parallel processing of FIR filters. Unit II discusses retiming, algorithmic strength reduction, and parallel architectures for filters and transforms. Unit III focuses on fast convolution techniques and pipelining and parallel processing of IIR filters. Unit IV examines scaling, round-off noise, and bit-level arithmetic architectures. Finally, Unit V covers numerical strength reduction, synchronous and asynchronous pipelining.

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Natheswaran
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182 views

Vlsi Signal Processing

The document outlines the units of the LTPC 3003 course which covers various digital signal processing and analog VLSI design topics. Unit I introduces DSP systems and algorithms as well as pipelining and parallel processing of FIR filters. Unit II discusses retiming, algorithmic strength reduction, and parallel architectures for filters and transforms. Unit III focuses on fast convolution techniques and pipelining and parallel processing of IIR filters. Unit IV examines scaling, round-off noise, and bit-level arithmetic architectures. Finally, Unit V covers numerical strength reduction, synchronous and asynchronous pipelining.

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Natheswaran
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
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LTPC 3003 UNIT I INTRODUCTION TO DSP SYSTEMS, PIPELINING AND PARALLEL PROCESSING OF FIR FILTERS 9 Introduction to DSP systems

Typical DSP algorithms, Data flow and Dependence graphs - critical path, Loop bound, iteration bound, Longest path matrix algorithm, Pipelining and Parallel processing of FIR filters, Pipelining and Parallel processing for low power. UNIT II RETIMING, ALGORITHMIC STRENGTH REDUCTION 9 Retiming definitions and properties, Unfolding an algorithm for unfolding, properties of unfolding, sample period reduction and parallel processing application, Algorithmic strength reduction in filters and transforms 2-parallel FIR filter, 2-parallel fast FIR filter, DCT architecture, rank-order filters, Odd-Even merge-sort architecture, parallel rankorder filters. UNIT III FAST CONVOLUTION, PIPELINING AND PARALLEL PROCESSING OF IIR FILTERS 9 Fast convolution Cook-Toom algorithm, modified Cook-Toom algorithm, Pipelined and parallel recursive filters Look-Ahead pipelining in first-order IIR filters, Look-Ahead pipelining with power-of-2 decomposition, Clustered look-ahead pipelining, Parallel processing of IIR filters, combined pipelining and parallel processing of IIR filters. UNIT IV SCALING, ROUND-OFF NOISE, BIT-LEVEL ARITHMETIC ARCHITECTURES 9 Scaling and round-off noise scaling operation, round-off noise, state variable description of digital filters, scaling and round-off noise computation, round-off noise in pipelined IIR filters, Bit-level arithmetic architectures parallel multipliers with sign extension, parallel carry-ripple and carry-save multipliers, Design of Lyons bit-serial multipliers using Horners rule, bit-serial FIR filter, CSD representation, CSD multiplication using Horners rule for precision improvement, Distributed Arithmetic fundamentals and FIR filters UNIT V NUMERICAL STRENGTH REDUCTION, SYNCHRONOUS, WAVE AND ASYNCHRONOUS PIPELINING 9 Numerical strength reduction subexpression elimination, multiple constant multiplication, iterative matching, synchronous pipelining and clocking styles, clock skew in edge-triggered single phase clocking, two-phase clocking, wave pipelining. Asynchronous pipelining bundled data versus dual rail protocol. L: 45 REFERENCES: 1. Keshab K. Parhi, VLSI Digital Signal Processing Systems, Design and implementation , Wiley, Interscience, 2007. 2. U. Meyer Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer, Second Edition, 2004 VL9254 ANALOG VLSI DESIGN LTPC 3003 UNIT I BASIC CMOS CIRCUIT TECHNIQUES, CONTINUOUS TIME AND LOW- VOLTAGESIGNAL PROCESSING

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