Low Voltage, High Frequency Four-Quadrant CMOS Current Multiplier Circuit

Kittipat Poorahong Risanuri Hidayat Kobchai Dejhan Phichet Moungnoul

Department of Telecommunication, Faculty of Engineering King Mongkuts Institute of Technology Ladkrabang (KMITL) Bangkok, Thailand

Abstract This paper proposes a high frequency four-quadrant CMOS current multiplier circuit using low voltage supply. This circuit has frequency response about 15 GHz, using 1V supply voltage and has input range about 15A . All CMOSs operate in saturation region and the simulation results are based on 0.18 m CMOS technology achieved using HSPICE (Level 49).

1. Introduction Current multiplier circuit is a basic circuit to apply to make other circuit. Some application use current multiplier, for example modulator. This paper proposes frequency four-quadrant CMOS current multiplier circuit based on 0.18 m CMOS technology. 2. Circuit Description Lets A = (a + b + c )2 , B = ( a b + c )2 C = (a b + d )2 , D = ( a + b + d )2 So

Io
Ii

Figure 1. Current Copier

( A + B ) (C + D ) = 8ab

The proposed current multiplier circuit consist of current copier and apply to current adder and current sub tractor, I to V converter, Inverter, V to I converter with current copier to get output signal inform of multiply. All CMOSs operate in saturation region.

Figure 1 is a current copier circuit that the direction of input and output is opposite. If the circuit sinks I in at the input, then it will source I in at the output. If the circuit sources I in at the input, then circuit will sink I in at the output.

Figure 2. Current adder I X + I Y and current sub tractor VGS1 = VGS 2 I D1 = I D 2 I B Ii = I B Io (1) (2) (3) When K n = n C ox
I D1 =

W = K1 L

(5) (6) (7) (8) (9) (10) (11)

So

Since the direction of the currents are opposite, then I o = I i (4)

K1 (VDD Vo VT )2 2 K 2 I D 2 = 1 (V0 V SS VT ) 2 V DD VT = (V SS + VT )

Mixing the current copiers such like Figure 2, we get a current adder I X + I Y and current sub tractor I X I Y .

I in = I D 2 I D1 I in = 2 K 1Vo (V DD VT ) Ii Vo = 2 K 1 (V DD VT )

Vo

Vo = Vi
Vi

Ii

Figure 3. I to V Converter Figure 3 is an I to V converter that consists of 2 same aspect ratio of MOSs and operates in the saturation region.

Figure 4. Inverter Figure 4 is an inverter that consists of 2 same aspect ratio of MOSs and operates in saturation region.

K1 (VDD Vo VT )2 (12) 2 K 2 I D 2 = 1 (Vi VSS VT ) (13) 2 VGS1 = VGS 2 (14) I D1 =

VD =

I X + IY 2 K 1 (V DD VT )

(20)

V DD Vo = Vi V SS Vo = Vi

(15) (16)

V A , VB , VC and VD feed to M 17 , M 18 , M 19 and M 20 , as shown in Figure 7, all of 4 MOSs have same aspect ratio MOSs and operate in saturation region
Let

W = K2 L a = 2 K 1 (V DD VT ) b = (V SS + VT ) K n = n C ox
Figure 5. I to V converter and Inverter with feed input of I X + I Y

(21) (22) (23)

The Drain currents of each MOS are

(24)
2

I D18 = I D19 I D 20

K2 2

I X IY + b (25) a a
2

K I I = 2 X Y + b 2 a a

(26)
2

Figure 6. I to V converter and Inverter with feed input of I X I Y Merging the I to V converter and the inverter, as shown in Figure 5 and Figure 6, yields the nodes V A , V B , VC and VD voltages bellow
I X + IY 2 K 1 (V DD VT ) I X IY VB = 2 K 1 (V DD VT ) I X IY VC = 2 K 1 (V DD VT ) VA =

K I I = 2 X + Y + b (27) 2 a a

(17) (18) (19) Figure 7. V to I converter with current copier

Figure 8. Current multiplier

M 21 and M 22 in Figure7 are current copier and act to subtract the current of (I D17 + I D18 ) (I D19 + I D 2o )
ID17 + ID18 =
2 2 K2 2I X 2IY 4I I (28) + + 2b2 + X2 Y 2 2 2a a a

I D19 + I D20
(29)

K = 2 2

2 2I X 2I 2 4I I 2 + 2Y + 2b 2 X2 Y a a a

3. Results The complete circuit of the current multiplier is viewed in Figure 8, and the simulation use 0.18m CMOS and simulate with H-Spice level 49 MOS aspect ratio shown in Table 1. Current source is showing in Table 2. The simulation result of the DC characteristic can be seen in Figure 9. Input of Ix and Iy current are -15A to +15A by Ix increase from -15A to +15A and Iy sweep from -15A to +15A in 7 (seven) steps, as we can see in Figure 9.

I o = (I D17 + I D18 ) (I D19 + I D 2o ) 4K 2 I X I Y Io = a2 K I I Io = 2 2 X Y 2 K 1 (V DD VT )

(30) (31) (32)

Table 1. Aspect ratio of MOS transistor MOS transistor W/L M1-M16, M21-M22 0.3/0.3 M17-M20 0.3/0.6 Table 2. Current Source Current Source I1, I3, I4 I2, I5 I6, I7

Figure 11 shows about the total harmonic distortion (THD). We feed Iy current 2 values that are -10A and +10 A. Ix is sine wave by amplitude 10A, and the frequency from 10 kHz to 10 GHz. The period of consider frequency is

Current
30 A 15A

40A

TSTOP = And the step is

2 f

(33)

TSTEP =

2 100 f

(34)

Figure 9. DC Characteristics Figure 10 shows about frequency response. The frequency increases from 100 kHz to 100 GHz. The simulation result measures that -3dB of the frequency is about 15 GHz.
-124

As seen in the THD graph, when Iy is 10A,that THD is approximately 1.4% until the frequency increase to 10 MHz, where THD starts to increase. The graph shows that the maximum THD is 7.5% at 1 GHz. When Iy is +10A, THD is approximately 1.2% until the frequency increase to 10 MHz, where THD starts to increase. The maximum THD is 5.4% at 9 GHz.
8 7 6 Iy = -10uA Iy = 10uA

THD (%)

Current dB (IO)

-125 -126 -127 -128

5 4 3 2 1 0 1e+4 1e+5 1e+6 1e+7 1e+8 1e+9 1e+10

Frequency (Hz)
100K 1M 10M 100M 1G Frequency (log) (Hz) 10G 100G

Figure 11 Total harmonic distortions The next is about the multiplier circuit that is applied in modulator. Ix is

Figure 10 Frequency Response

10 AP P and has frequency 500 MHz, while Iy is a carrier signal, with frequency 5 GHz, and amplitude 5AP P as we can see in Figure 12 and Figure 13. The modulated frequency is shown in Figure 14.

4. Conclusion A current multiplier circuit using 1V voltage supply is proposed in this article. Frequency response of the circuit is 15 GHz. Other Value of Simulation is shown in Table 3.

Figure 12 Signal, frequency 500 MHz and amplitude 10 AP P

Table 3 Other Value of simulation result Parameter Technology Supply Voltage CMOS amount Current Source amount Input Range Bandwidth (-3 dB) Power dissipation

Simulation and Value 0.18 m CMOS

22 7 15A 15 GHz 0. 681m watts

Figure 13 Carrier signal, frequency 5 GHz, and amplitude 5AP P

Figure 14 Modulated output Signal

5. References [1] B. Razavi, Design of Integrated Circuits for Optical Communications, (1st Ed), McGraw Hill, 2003 [2] J. S. Pena-Finol and J. A. Connelly, A Mos FourQuadrant Analog Multiplier Using the Quarter-Square Technique, IEEE Journal of Solid-State Circuits, vol. sc-22, December 1987 [3] K. Bult and H. Wallinga, A CMOS Four-Quadrant Analog Multiplier, IEEE Journal of Solid-State Circuits, vol. sc-21, June 1986 [4] Y. H. Kim and S. B. Park, FourQuadrant CMOS Analogue Multiplier, Electronics Letters, vol.28, pp. 649-650, March 1992 [5] Z. Wang, 2-Mosfet Transistor with Extremely Low Distortion for Output Reaching Supply Voltages, Electronics Letters, vol.26, pp. 951-952, June 1990