Week 3
Week 3
Introduction
8051 instruction set is: Optimized for 8-bit control applications Provides fast, compact addressing modes for accessing internal RAM with small data structures Extensive support for 1-bit variables, allowing direct bit manipulation Instructions have 8-bit opcodes, providing 28 = 256 instructions. 255 are implemented, one is undefined Some instructions have one or two additional bytes for data and addresses: 139 1-byte instructions 92 2-byte instructions 24 3-byte instructions
Addressing Modes
Most instructions operate on some data, but that data can reside in many places. ie. Within a register (R0-R7), internal RAM, or external memory Addressing modes allow us to specify the locations of the data and in different ways. There are 8 modes available:
1) Register 2) Direct 3) Indirect 4) Immediate 5) Relative 6) Absolute 7) Long 8) Indexed
Register Addressing
Since there are 8 active registers at any one time, they can be encoded using 3 bits, leaving 5 bits for the opcode, to form a short (1-byte) instruction:
Opcode n
n = register number
e.g. ADD A,R7 OPCODE = 00101111B MOV A,R7 OPCODE = 11101111B Some instructions are specific to a certain register, so the address bits are not needed and the register name is built into the opcode: e.g. INC DPTR ;increment data pointer by 1 other register names are: A (accumulator), PC (program counter), C (carry flag), AB (accumulator-B)
Direct Addressing
Allows access to any on-chip variable or hardware register An additional byte is appended to the opcode specifying the location to be used:
Opcode Direct Address
e.g. 1: ADD
A,55H
OPCODE = 00101111B
The contents at mem location 55H are placed in the accumulator e.g. 2: MOV P1,A OPCODE = 10001001B (1st byte) Address of P1 = 10010000B (2nd byte) The contents of the accumulator are transferred to Port 1, whose address is determined by the assembler and inserted as byte 2 of the instruction
Indirect Addressing
Allows access to a variable in internal RAM whose address is determined, computed or modified while the program is running R0 or R1 may operate as a pointer to an actual memory location The least-significant bit of the opcode determines which register is used as the pointer
Opcode
The contents at mem location pointed to by R0 are added to the accumulator and placed back in the accumulator e.g. 2: MOV A,@R1 OPCODE = 11100111B
Immediate Addressing
Used when the operand is a constant (ie. known at assemble-time) An additional byte contains the value, which may be a numeric constant, a symbolic variable or an arithmetic expression using constants, symbols and operators Preceded by a number sign (#)
Opcode Immediate data
The constant number 44H is added to the accumulator and placed back in the accumulator The constant is always assumed to be 8 bits except when initializing the data pointer, which assumes a 16-bit constant: MOV DPTR,#8000H OPCODE = 10010000B
Relative Addressing
Used only with certain jump instructions 8-bit signed value (offset) is added to the PC to form the address of the next instruction Range for jumping is -128 to +127 bytes or locations Relative offset is appended to the instruction as an extra byte:
Opcode Relative offset
e.g. 1:
SJMP AHEAD
OPCODE = 10000000B
If the label AHEAD represents memory location 1040H and the above instruction is in memory locations 1000 and 1001H, the assembler will assign a relative offset of 3EH as byte 2 of the instruction (1002H + 3EH = 1040H) Provides position-independent code with limited jump ranges
Absolute Addressing
Used only with the ACALL and AJMP instructions Allows branching within the current 2K page of code memory by providing the least-significant bits of the destination address in the opcode (A10-A8) and byte 2 of the instruction (A7-A0):
A10-A8 Opcode A7-A0
The upper 5 bits of the destination address are the current upper 5 bits of the PC. e.g. 1: AJMP ADDR OPCODE = aaa00001B
If the label ADDR represents memory location 0F46H and the above instruction is in memory locations 0900H and 0901H, the assembler will encode the instruction as 1110000101000110B Provides short (2-byte) instructions but is position-dependent and has limited range
Long Addressing
Used only with the LCALL and LJMP instructions Allows branching using a full 16-bit destination address that is specified in bytes 2 and 3 of the instruction:
Opcode A15-A8 A7-A0
e.g. 1:
LJMP ADDR
OPCODE = 00000010B
Provides full use of the 64K code space but is position-dependent and the instructions are three bytes long
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Indexed Addressing
Uses a base register (either the PC or the data pointer DPTR) and an offset (the ACC) in forming the effective address for a JMP or MOVC instruction:
Base register PC or DPTR Offset Effective address
ACC
e.g. 1:
MOVC A,@A+PC
OPCODE = 10000011B
Jump tables or look-up tables are easily created using indexed addressing.
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Instruction Types
The 8051 instructions are divided among five functional groups:
1)Arithmetic 2)Logical 3)Data transfer 4)Boolean variable 5)Program branching
Refer to Appendix A for a reference chart showing all 8051 instructions by functional grouping
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Arithmetic Instructions
The ADD A instruction can be written in different ways depending on which addressing mode is chosen: ADD ADD ADD ADD INC A,7FH A,@R0 A,R7 (direct addressing) (indirect addressing) (register addressing)
All arithmetic instructions execute in one machine cycle except: (2 machine cycles) (4 machine cycles) 13
MUL/DIV
Example: The ACC contains 63H, R3 contains 23H, and the PSW contains 00H. a)What is the hex content of the ACC and the PSW after execution of the following instruction? ADD A,R3 b)What is the content of the ACC in decimal after the above instruction?
SOLUTION: part a)
ACC R3 ACC 63H +23H 86H (13410)
But how does the 8051 CPU interpret the values? For signed binary: valid range is [-128, +127] ... out of range! For unsigned binary: valid range is [0, +255] ...ok
The CPU has no special knowledge of the format...only you, the programmer knows for sure. The status bits of the PSW allow us to manage the different formats. In binary, the above addition becomes: ACC R3 ACC 11...11. 01100011H +00100011H 10000110H
- Since there was no carry out of bit 7 the C bit is not set. - The OV flag is set because the result is out of range for 8-bit signed numbers. - The AC bit is cleared since a carry did not occur out of bit 3 - The P bit is set because 3 bits in ACC are equal to 1
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Decrementing DPTR
One of the INC instructions operates on the 16-bit data pointer, but there is no equivalent decrement instruction. Instead, we have to write a sequence of instructions:
DEC DPL MOV R7,DPL CJNE R7,#0FFH,SKIP DEC DPH SKIP: (continue) ;DECREMENT LOW-BYTE OF DPTR ;MOVE TO R7 ;IF UNDERFLOW TO FF ;DECREMENT HIGH-BYTE TOO
The high- and low-bytes of the DPTR must be decremented separately. High-byte (DPH) is only decremented if the low-byte (DPL) underflows from 00H to FFH 15
Multiplication
e.g. If the ACC contains 55H, the B register contains 22H and the PSW contains 00H, what are the contents of these registers after execution of the following: MUL AB
Solution: Converting to decimal gives 55H = 8510 and 22H = 3410 ,so the product is 289010 In order to determine the values in ACC and B we convert back to hex: 289010= 0B4AH 0BH (high-byte) is placed in B 4AH (low-byte) is placed in ACC The P bit in the PSW is set to establish even parity with ACC. The OV flag is set since the result is greater than 25510 Therefore, the PSW contains 05H 16
Logical Instructions
Perform Boolean operations (AND, OR, XOR, NOT) on bytes of data on a bit-by-bit basis e.g. If the ACC contains 00110101B then the instruction: ANL A,#01010011B
leaves the ACC holding 000010001B Addressing modes are same as that of arithmetic instructions All logical instructions using the ACC as one of the operands execute in one machine cycle. The others take two machine cycles. Can be performed on any byte in internal data memory space without going through the ACC: XRL P1,#0FFH ;inverts port1 bits using XOR 17
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Direct addressing is used to identify the byte being saved or restored The stack itself is accessed by indirect addressing using the SP register 20
Boolean Instructions
8051 processor contains a complete Boolean processor for single bit operations All bit accesses use direct addressing with: 128 bit addresses 00H-7FH in the lower 128 locations starting with bit 0 of address 20H (bit 00H) to bit 7 of address 2FH (bit 7FH) 128 bit addresses 80H-FFH in the SFR space Bits may be set or cleared: SETB P1.7 CLR P1.7 ;set Port 1 bit 7 ;clear Port 1 bit 7
The assembler does the conversion of the symbol P1.7 into the correct bit address, 97H 23
Instructions exist for a logical AND (ANL) and a logical OR (ORL) but not the logical exclusive OR (XRL) All other logical operations (such as XRL) must be implemented in code 24
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SKIP:
CJNE JNC
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