Politecnico di Milano

Scuola di Ingegneria dellInformazione

Corso di Laurea Magistrale in Ingegneria Elettronica
Low-Power and Compact
Successive Approximation ADC
for Bio-Electronic Chips
Relatore: Prof. Marco SAMPIETRO
Correlatore: Prof. Andreas HIERLEMANN
Tesi di Laurea di: Andrea BONETTI
matricola 750696
Anno Accademico: 2010-2011
Acknowledgments
First of all, I would like to thank my supervisor Prof. Marco Sampietro of
Politecnico di Milano for his continuous support and for making my stay
at ETH Z urich. I am particularly grateful to Prof. Andreas Hierlemann
who gave me the unique opportunity to carry out my Masters Thesis at his
laboratory. Dr. Yihui Chen deserves special thanks for his intelligent guid-
ance through the world of the analog-to-digital converters. I also would like
to express my gratitude to Pascal Meinerzhagen for his helpful suggestions
and to Vijay Viswam for his insightful comments during the completion of
the project. I was truly fortunate to have the possibility to work at the Bio
Engineering Laboratory (BEL) and I owe sincere thanks to all the people I
worked with.
3
Contents
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 MEA Chips Developed at BEL . . . . . . . . . . . . . . . . . 1
1.2.1 Interfacing Electrogenetic Cells in Vitro with CMOS
Microelectrode Arrays . . . . . . . . . . . . . . . . . . 1
1.2.2 The High-Density MEA Chip . . . . . . . . . . . . . . 3
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . 5
2 Specications and ADC Topologies 6
2.1 Required ADC for the New Version of the Chip . . . . . . . . 6
2.2 Elaboration of Specications . . . . . . . . . . . . . . . . . . 6
2.3 Low Power ADC Topologies Overview . . . . . . . . . . . . . 7
2.4 Fully Dierential Switched-Capacitor SAR ADC . . . . . . . 10
3 Design implementation 13
3.1 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Switched-Capacitor Array . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Capacitive Array Design . . . . . . . . . . . . . . . . . 17
3.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 Switch Structures . . . . . . . . . . . . . . . . . . . . . 27
3.3.2 DAC Settling Time . . . . . . . . . . . . . . . . . . . . 30
3.3.3 Other Switches . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.3 Preamplier . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . 50
3.5.2 SAR Control Logic Implementation . . . . . . . . . . 53
3.5.3 Delay Elements . . . . . . . . . . . . . . . . . . . . . . 54
3.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4
4 Simulations and Conclusions 58
4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5 Appendix 64
5.1 Eects of the parasitic capacitances in the DAC . . . . . . . . 64
5.2 Standard deviation estimation of the DAC output voltage . . 65
Bibliography 68
5
List of Figures
1.1 Packaged MEA chip on a custom-designed printed circuit board. 2
1.2 (a) Schematic of a cell attached to a sensor surface. (b) Mi-
crograph of an acute cerebellar brain slice (parasagittal cut)
placed on a CMOS high-density electrode chip for measure-
ments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Micrograph of the MEA chip (7.5 6.1 mm
2
). . . . . . . . . 3
1.4 Block diagram of the MEA chip. . . . . . . . . . . . . . . . . 4
2.1 Single-slope ADC [4]. . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Successive-approximation ADC structure [4] and a 4-bit analog-
to-digital conversion. . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 First-order sigma-delta ADC [4] . . . . . . . . . . . . . . . . . 9
2.4 3-bit single-ended switched-capacitor SAR ADC. . . . . . . . 10
2.5 4-bit fully dierential switched-capacitor SAR ADC. . . . . . 11
2.6 Voltages at V
ipA
and V
inA
during the sampling and conversion
phases for the 4-bit fully dierential switched-capacitor SAR
ADC [8]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Binary weighted switched-capacitor array. . . . . . . . . . . . 15
3.2 Binary weighted switched-capacitor array equivalent circuit. . 16
3.3 2bw1Cs capacitive array. . . . . . . . . . . . . . . . . . . . . . 16
3.4 5bw4Cs capacitive array. . . . . . . . . . . . . . . . . . . . . . 16
3.5 C2C capacitive array. . . . . . . . . . . . . . . . . . . . . . . 16
3.6 2bw1Cs switched-capacitor array with the bottom-plate par-
asitic capacitance added. . . . . . . . . . . . . . . . . . . . . . 18
3.7 2bw1Cs switched-capacitor array equivalent circuit. . . . . . . 19
3.8 INL graph estimation of each split capacitive array. . . . . . . 20
3.9 Modied split capacitive array. . . . . . . . . . . . . . . . . . 23
3.10 Modied split capacitive array equivalent circuit. . . . . . . . 23
3.11 Floorplan of the capacitive array. . . . . . . . . . . . . . . . . 25
3.12 INL graphs of the 9-bit DAC comparing two dierent values
for the unit capacitance. . . . . . . . . . . . . . . . . . . . . . 25
3.13 Capacitive array with ideal bottom-plate and top-plate switches. 28
3.14 Mux-like structure for the switches of the capacitive array. . . 29
6
3.15 Shared-block structure for the switches of the capacitive array. 29
3.16 Dependance of the on-resistance value of the transmission-
gate on the input voltage value. While maintaing the rela-
tion (3.26), the value of W
N
has been swept from 0.7 m to
7 m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.17 Equivalent RC model of the 9-bit DAC for D
IN
= 256. . . . . 32
3.18 Simplied equivalent RC model of the 9-bit DAC for D
IN
= 256. 32
3.19 First-order equivalent RC model of the 9-bit DAC for D
IN
=
256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.20 Structure of the comparator stage. . . . . . . . . . . . . . . . 35
3.21 Dynamic latch. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22 Output response of the latch for a dierential sinusoid input
signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.23 Load of the dynamic latch. . . . . . . . . . . . . . . . . . . . 37
3.24 Output response of the latch during the regeneration phase.. 38
3.25 Test bench for the input-referred oset voltage estimation of
the latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.26 Two-stage preamplier. . . . . . . . . . . . . . . . . . . . . . 41
3.27 Kickback noise in the rst stage of the preamplier. . . . . . 41
3.28 First preamplier stage with dummy transistors using the
capacitive neutralization technique. . . . . . . . . . . . . . . . 42
3.29 Closed-loop operation of the preamplier performing the in-
put oset storage. . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30 Simplied equivalent circuit of the analog part of the ADC. . 45
3.31 Sampling timing diagram example. . . . . . . . . . . . . . . . 45
3.32 Magnitude and phase diagrams of the open-loop preamplier
transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.33 Step responses of the preamplier stages for a LSB
de
dier-
ential input. The blue trace represents the dierential output
voltage of the rst stage, while the red trace shows the dier-
ential output voltage of the second stage. . . . . . . . . . . . 48
3.34 Magnitude and phase diagrams of the loop gain transfer func-
tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.35 Timing diagrams of the SAR control logic. . . . . . . . . . . . 52
3.36 Timing diagrams for the rst three cycles of a conversion. . . 53
3.37 Timing diagrams of the cycles used to determine the last 9
bits of the digital output. . . . . . . . . . . . . . . . . . . . . 54
3.38 Successive approximation register for binary search. . . . . . 55
3.39 Chain of inverters to generate the delayed clock signal. . . . . 55
3.40 Floorplan of the SAR ADC. . . . . . . . . . . . . . . . . . . . 56
3.41 Analog and digital blocks composing the SAR ADC. . . . . . 57
3.42 Layout of the shared digital logic among all the ADCs on chip. 57
3.43 Floorplan of the ADCs integrated on the MEA chip. . . . . . 57
7
4.1 Example of an analog-to-digital conversion performed by the
SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 DNL histogram plot of the SAR ADC. . . . . . . . . . . . . . 59
4.3 INL histogram plot of the SAR ADC. . . . . . . . . . . . . . 60
4.4 2048-points FFT output of the SAR ADC. . . . . . . . . . . 60
5.1 Switched-capacitor DAC equivalent circuit. . . . . . . . . . . 64
5.2 3-bit switched-capacitor DAC and its equivalent circuit. . . . 66
8
List of Tables
1.1 Performance summary of the MEA chip presented in [1]. The
reported values are based on experimental measurements. . . 5
2.1 Specications for a single ADC. . . . . . . . . . . . . . . . . . 7
3.1 Summary of the most relevant parameters for the available
types of capacitors. . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Examples of the resulting parametric estimation of (V
M,D
IN
=256
)
for the bw and 2bw1Cs capacitive arrays. . . . . . . . . . . . 21
3.3 Summary of the results for the design of the capacitive array. 22
3.4 Calculated and simulated settling time for D
IN
transiting
from 0 to 256. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5 Preamplier specications. . . . . . . . . . . . . . . . . . . . . 47
4.1 Summary of the ADC power consumption. . . . . . . . . . . . 60
4.2 Requirements and estimated performance of a single SAR ADC. 61
4.3 Specications of the single-slope data-conversion system cur-
rently implemented on chip, compared to the performance of
the SAR ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9
Abstract
For both the electrical stimulation and recording of cultured neurons, the
CMOS-based microelectrode arrays (MEAs) are one of the most promising
electronic devices used nowadays. To ensure a robust transmission of the
information between the chip and external devices, the MEA chip requires
integrated analog-to-digital converters (ADCs). Moreover, the presence of a
large number of read-out channels on chip poses stringent requirements on
both area and power consumption for the design of the ADCs. Thus, this
Masters thesis work proposes a low-power and compact successive approx-
imation register (SAR) ADC for such bio-electronic chips.
In this thesis, some low-power ADC topologies are rst investigated and
the SAR ADC is nally chosen, that is the optimum solution for the ap-
plication. The choice of multiplexing the read-out channels of the MEA
chip for the analog-to-digital conversion is then presented while the require-
ments for the ADC are derived. In this work, the design of each part of the
converter is described, starting from the switched-capacitor array which is
usually used as a sample and hold (S/H) as well as a digital-to-analog con-
verter (DAC). The size of the switches that are providing the signals to the
DAC is optimized considering the timing requirements. Furthermore, low
power solutions are proposed for the comparator while good performances
are achieved for both noise and speed. A successive approximation register
logic is nally used to provide the digital control signals.
The performance of the SAR ADC is evaluated with post-layout simula-
tions. All the preliminary requirements are met and the proposed converter
represents a promising solution for low-power applications. In conclusion,
the specications of the entire data-conversion system are compared with
the ADCs currently implemented on the MEA device and a possible im-
provement of the chip is presented.
Key words: Microelectrode Array (MEA), Switched-Capacitor (SC) Suc-
cessive Approximation Register (SAR) Analog-to-Digital Converter (ADC),
Low-Power, Split Capacitor Array, Oset Cancellation.
10
Sommario
Fra i dispositivi che permettono la stimolazione e la misura dellattivit`a
elettrica di colture neuronali, i CMOS microelectrode array (MEA) sono
una delle migliori soluzioni utilizzate oggigiorno. Per una sicura trasmissione
di informazioni dal chip ai dispositivi esterni, il dispositivo MEA richiede
convertitori analogico-digitali (ADC) da integrare nel chip. In particolare,
la progettazione di tali circuiti deve essere eseguita limitando il consumo di
area e potenza in quanto il numero di canali di lettura integrati `e elevato.
Per questo motivo, la presente tesi propone un ADC ad approssimazioni
successive (SAR) compatto e a basso consumo di potenza per chip bio-
elettronici.
In questa tesi, diverse tipologie di ADC a risparmio di potenza sono in-
izialmente investigate e il modello SAR `e inne scelto, in quanto dimostra di
essere la soluzione ottimale per lapplicazione studiata. La scelta di utilizzare
il multiplexing dei canali di lettura per la conversione analogico-digitale `e
quindi presentata assieme alle speciche dellADC. La progettazione di ogni
componente elettronico del convertitore `e poi descritta, iniziando dallarray
a capacit`a commutate che `e usato sia come sample and hold (S/H), sia come
convertitore digitale-analogico (DAC). Le dimensioni degli interruttori che
forniscono i segnali al DAC sono ottimizzate considerando le speciche del
tempo di assestamento. Una soluzione a basso consumo di potenza `e pro-
posta per il comparatore e un registro ad approssimazioni successive `e usato
per generare i segnali digitali di controllo.
Le prestazioni dellADC SAR sono valutate con simulazioni post-layout.
Tutte le speciche stabilite sono soddisfatte e il convertitore proposto rap-
presenta una promettente soluzione per applicazioni a basso consumo di
potenza. La performance dellintero sistema di ADC integrabile nel dispos-
itivo MEA `e dunque confrontata con quella degli ADC a singola rampa al
momento implementati sul chip e un possibile miglioramento del dispositivo
`e presentato.
Parole chiave: Microelectrode Array (MEA), Convertitore Analogico-Digitale
(ADC) ad Approssimazioni Successive (SAR) a Capacit`a Commutate (SC),
Basso Consumo di Potenza, Array a Capacit`a Commutate, Cancellazione
dellOset.
11
Chapter 1
Introduction
1.1 Motivation
The CMOS-based microelectrode arrays (MEAs) [1] are sophisticated de-
vices, which can be used to bidirectionally communicate with cultured neu-
rons. They can perform measurements at a high spatial and temporal resolu-
tion, which is hardly achievable with passive MEAs. A switch-matrix-based
high-density MEA chip [2] has been developed at Bio Engineering Labora-
tory of ETH Z urich. With the switch-matrix scheme, an arbitrary subset
of around 11000 electrodes can be selected for recording and stimulation.
By placing the front-end ampliers outside the array, a high signal-to-noise
ratio (SNR) has been achieved together with a subcellular spatial resolution.
To ensure robust and stable transmissions of the information between
the chip and other devices on the printed circuit board (Figure 1.1), the
amplied and ltered neural signals are usually digitized by on-chip analog-
to-digital converters (ADCs). The number of neural signals which can be
recorded simultaneously is limited by the number of read-out channels in-
tegrated on the chip, hence, in order to observe the electrical activity of a
large scale neural network, the 126 read-out channels of the previous design
are not sucient. Therefore, the new version of the chip integrates much
more channels, posing stringent area and power consumption constraints on
the individual read-out channel and ADC.
1.2 MEA Chips Developed at BEL
1.2.1 Interfacing Electrogenetic Cells in Vitro with CMOS
Microelectrode Arrays
Complementary semiconductor-metal-oxide (CMOS) technology is a very
powerful technology used to realize substrate-integrated microelectrode ar-
rays. These devices are arrangements of electrodes that can be more or
1
Figure 1.1: Packaged MEA chip on a custom-designed printed circuit board.
less directly interfaced to electrogenetic cells, like heart or brain cells. It is
therefore possible to study fundamentals of learning processes and assess the
behavior of electrogenetic cells in vitro by culturing or placing them directly
atop the electronic chips, as shown in Figure 1.2.
Figure 1.2: (a) Schematic of a cell attached to a sensor surface. (b) Micrograph of
an acute cerebellar brain slice (parasagittal cut) placed on a CMOS high-density
electrode chip for measurements.
The CMOS technology plays an important role for such devices since it
allows the possibility to address a large number of microelectrodes on the
same chip, leading to a spatial sub-cellular resolution. Another advantage
of using CMOS integrated circuits (ICs) is the high signal quality provided
and the relative low-noise electrophysiological recordings that can be per-
formed from a variety of biological preparations. Many functions can be
programmed via software and digital interfaces. The recording technique is
extracellular and noninvasive, enabling long-term measurements.
Applications areas for such devices include neuroscience as well as med-
ical diagnostics and pharmacology. The most common biological prepara-
tions studied using microelectrode arrays are acute tissue preparations (e.g,
slices) which are recorded from immediately after they have been cut from
2
the animal and cell cultures.
1.2.2 The High-Density MEA Chip
The Bio Engineering Laboratory (BEL) of ETH Z urich designed a CMOS-
based microelectrode array [1] featuring 11011 metal electrodes and 126
read-out channels for extracellular bidirectional communication with elec-
trogenetic cells. The micrograph of the chip is shown in Figure 1.3. The
most important features include:
High spatial resolution at (sub)cellular level with 3150 electrodes per
mm
2
. The electrode diameter is 7 m and the electrode pitch is 18 m.
A recongurable routing of the recording sites to the 126 read-out
channels.
A low front-end input referred noise of 2.4 V
rms
.
Figure 1.3: Micrograph of the MEA chip (7.5 6.1 mm
2
).
The high-density arrays are usually CMOS-based devices that over-
come the connectivity limitation by making use of on-chip signal multi-
plexing. The simultaneous recording from all electrodes requires the front-
end ampliers being placed in each pixel (recording site), which, due to
3
area constraints, entails rather high noise levels. Instead of scanning the
entire electrode array, the approach of this device provides a recongurable
electrode/readout-channel routing to select an arbitrary subset of electrodes
for recording and stimulation. This enables both, low-noise signal record-
ing, and cellular or subcellular resolution, since the front-end circuitry can
be placed outside the array.
Figure 1.4: Block diagram of the MEA chip.
In the MEA chip designed by BEL [2] the read-out 126 channels and the
associated signal amplication and stimulation circuitry are located outside
the recongurable electrode array, where sucient area for a low-noise circuit
implementation is available (Figure 1.3). The readout channels includes two
amplication and lter stages. Both stages feature digitally congurable
gain and lter settings. The rst stage provides bandpass ltering (BPF)
and a gain of 30 dB. The second stage provides an additional gain of either
0 dB, 20 dB or 30 dB with a second LPF. Eight channels are then multiplexed
and buered by a third stage with an additional gain of 0 dB, 6 dB, 14 dB
or 20 dB, and nally digitized at 20 kHz using successive-approximation
analog-to-digital converters (ADCs) with a resolution of 8-bit. The digital
recording controller then transfers the data o chip by means of a 9-bit bus
together with chip-status information and a CRC (cyclic redundancy check)
for error detection.
The chip was fabricated in an industrial 0.6 m 3-metal 2-polysilicon
CMOS-process. The total area of the device is 7.5 6.1 mm
2
, while the
electrode array covers an area of 2.0 1.75 mm
2
. The front-end input-
referred noise within the band of 1 Hz to 100 KHz is 2.4 V
rms
. The maxi-
mum gain of the entire read-out circuit is 80 dB. The power consumption of
the front-end (rst and second stage) is 160 W/channel while the overall
power consumption of the chip is 135 mW. The most relevant specications
characterizing the chip are summarized in Table 1.1.
4
Parameter Value
Technology 0.6m 3M2P CMOS
Area 7.5 6.1 mm
2
Supply voltage analog 5.0 V
Supply voltage digital 3.0 V
Clock frequency recording controller 3.2 MHz
Clock frequency comand controller 8 MHz
Number of electrodes 11011
Sensor area 2.0 1.75 mm
2
Electrode density 3150 1/mm
2
Power consumption overall 135 mW
Power consumption front-end (stage 1&2) 160 W/channel
Front-end input-referred noise (1 Hz to 100 kHz) 2.4 V
rms
Amplication 0-80 dB (18 steps)
Table 1.1: Performance summary of the MEA chip presented in [1]. The reported
values are based on experimental measurements.
1.3 Thesis Organization
Requirements and specications of the ADC for the new version of the MEA
chip are dened in Chapter 2 where dierent topologies of converters are an-
alyzed. Chapter 3 presents the design of the SAR ADC, showing the analysis
and simulations of the switched-capacitor array, switches, comparator and
SAR control logic. The characterization of the converter is shown in Chap-
ter 4 where the conclusions are reported. Finally, Chapter 5 is reserved for
the appendix.
5
Chapter 2
Specications and ADC
Topologies
This chapter provides the key design aspects for the new version of the chip.
The choice of multiplexing the read-out channels for the analog-to-digital
conversion is then presented and the requirements for the ADC are derived.
Finally, some low-power ADC topologies are investigated and the optimum
solution for our application is chosen.
2.1 Required ADC for the New Version of the
Chip
The presence of on-chip ADCs is an essential requirement for allowing a
robust signal transmission between the chip and the printed-circuit board
(PCB). For the MEA chip presented in [2], 16 successive approximation
ADCs with a 8-bit resolution have been employed.
In order to observe the electrical activity of a large-scale neural network,
the new version of the chip needs to provide an increased number of channels
N
Channels
equal to 1024, which poses stringent area and power consumption
constraints on the individual read-out channel and ADC. In order to improve
the signal quality, in the new design, the number of bits is increased to 10.
For this reason, a thorough noise and oset analyses of the converter are
key aspects that have to be considered during the design.
2.2 Elaboration of Specications
The frequency band for typical neural signals is roughly 10 Hz 5 KHz [3].
In order to avoid aliasing and ease spike sorting, the sampling frequency for
a single read-out channel is set to 20 KHz. The number of ADCs is reduced
by multiplexing the signals before their eective conversion. For the new
6
design, a number of 16 ADCs has been aimed to be integrated on the chip,
leading to the following sampling frequency f
S
for each converter:
f
S
=
N
Channels
N
ADCs
f
N
=
1024
16
20kHz = 1.28 MS/s (2.1)
Due to limited chip area, the area for each ADC is restricted to 1 mm
2
.
To reduce quantization error, 10-bit resolution is chosen while the signal-
to-noise and distortion ratio (SNDR) is set to be larger than 56 dB, which
corresponds to an eective number of bits (ENOB) equal to 9. The new
version of the chip will be designed using a 0.35 m CMOS technology and
a 3.3 V power supply, aiming to a maximum power consumption of 1 mW
for each ADC. The preliminary specications are summarized in Table 2.1.
Parameter Value
Resolution 10 bits
Sampling rate 1.28 MS/s
SNDR 56 dB
Power consumption 1 mW
Supply voltage 3.3 V
Technology 0.35 m CMOS
Area 1 mm
2
Table 2.1: Specications for a single ADC.
2.3 Low Power ADC Topologies Overview
In order to evaluate to evaluate which ADC architecture [4] best satises the
presented requirements, some of the most important topologies are briey
reviewed in this section.
Integrating ADC
The Integrating ADC can be an appropriate solution for low-speed appli-
cations where low power consumptions are required. A possible implemen-
tation of this topology is the single-slope architecture, shown in Figure 2.1,
where the input signal is compared with a voltage ramp. Counting the time
required by the ramp to reach the signal value, it is possible to perform
the analog-to-digital conversion. Even if this solution presents a very sim-
ple structure (a comparator, the voltage ramp generator and the counter
in principle), it suers from several drawbacks. A stable and precise ramp
generator is required since voltage and temperature coecients can aect
7
the linearity of the conversion. Moreover, a high clock frequency is desired
in order to reach a sucient resolution.
Figure 2.1: Single-slope ADC [4].
Successive-Approximation ADC
The successive-approximation ADC is based on the binary search algorithm
and it requires a simple structure based on a sample and hold (S/H), com-
parator, digital-to-analog converter (DAC) and the successive approxima-
tion register (SAR). This is a topology mostly used to design medium-high
resolution ADCs for medium-low speed applications. The DAC is controlled
by the SAR logic and its output voltage varies depending on the decision of
the comparator, as shown in Figure 2.2. Besides the simple structure, the
converter presents a low power consumption as well.
Sigma-Delta ADC
The Sigma-Delta ADC is one of the best solutions if high resolution is re-
quired in low frequency applications. The converter is based on the oversam-
pling and noise shaping techniques and it can achieve high signal-to-noise
ratio (SNR). The analog part of the circuit is simple since only a compara-
tor, voltage reference, integrators and analog summing circuits are required.
On the other hand, the digital circuitry is quite complex and it consists of
a digital signal processor (DSP) which acts as a digital lter and decimator
(Figure 2.3). The delta modulation is used to achieve higher transmission
eciency by transmitting the changes (delta) in value between consecutive
samples. Combining the oversampling with the sigma-delta modulator it
8
Figure 2.2: Successive-approximation ADC structure [4] and a 4-bit analog-to-
digital conversion.
is possible to obtain a high SNR at low frequencies by shaping the quanti-
zation noise such that most of it occurs outside the bandwidth of interest.
The noise outside the frequency bandwidth of interest will be removed by
the digital lter while the decimator will reduce the output data rate back
to the Nyquist rate. Some of the disadvantages of this structure are the high
clock frequency required and the large silicon area consumed by the digital
part.
Figure 2.3: First-order sigma-delta ADC [4]
9
2.4 Fully Dierential Switched-Capacitor SAR ADC
Considering the ADC specications mentioned in Section 2.2, the successive
approximation ADC has been preferred among the three dierent low-power
ADC topologies presented. The most relevant advantages of this topology
are the following:
Low power consumption: Since the SAR ADC does not contain any
power-hungry operational ampliers (OpAmps), it is a well-known
topology for its power eciency. In fact, the comparator usually con-
sumes less than an OpAmp since it does not need linear settling.
Simple structure: The low complexity of the circuit ease its imple-
mentation on chips where compact realizations are required. This is
also due to the very simple principle on which the ADC is based, the
binary search algorithm. Moreover, promising solutions can also be
evaluated in order to reduce even more the total area required by the
ADC.
In particular, the converter presented in this work is a fully dieren-
tial switched-capacitor or charge-redistribution SAR ADC [5]. This circuit
incorporates an array of capacitors that is usually used as a S/H as well
as a DAC. In order to better understand the operation, we rst consider a
simple single-ended 3-bit switched-capacitor ADC with a binary weighted
capacitive array [6], which is shown in Figure 2.4. The main parts of the
circuit are: the capacitive array, the switches, the comparator and the SAR
control logic.
Figure 2.4: 3-bit single-ended switched-capacitor SAR ADC.
During the sampling phase, the top plates of the capacitors are reset to
the common voltage V
CM
while all the bottom plates of the capacitors are
connected to the input signal source V
sig
that is equal to the sum of V
CM
and the input signal component V
sig
. The switches resetting the input
node of the comparator are then turned o and all the bottom plate nodes
are connected to V
CM
, performing the so-called bottom plate sampling [7].
Now that the voltage V
CM
V
sig
is stored on the top plate node of the
10
capacitors, the switch controlled by D
2
is connected to V
REF
and a voltage
equal to V
REF
/2 is added to V
CM
V
sig
. The comparator can therefore
determine the most signicant bit (MSB) by comparing this value with V
CM
.
The SAR control logic either leaves the switch controlled by D
2
connected
to V
REF
or connects it back to V
CM
depending on the comparator output.
A similar process is followed for the remaining two bits leading to the deter-
mination of the digital output value. All the switches are then reset again
to the initial positions and the converter can start another cycle of conver-
sion [4]. Note that the extra LSB capacitor (C in the case of the 3-bit DAC)
is required to make the total value of the capacitive array equal to 8C, so
that binary division is accomplished when the individual bit capacitors are
manipulated.
Using the same switched-capacitor array of the previous example and
considering a fully dierential topology of the circuit, the 4-bit ADC shown
in Figure 2.5 is obtained. This new structure diers from the single-ended
one in Figure 2.4 in various aspects, i. e., the dierential input signal for
the comparator, two identical capacitive arrays and two dierent references
voltages V
REFP
and V
REFN
. Note that this structure gains an additional bit
D
3
that is the sign bit and it is determined once the dierential input signals
are sampled on the input nodes of the comparator. Hence, the MSB bit
corresponds to the sign of the output digital value. Each reference voltage is
assigned to a capacitive array depending on the result of the sign bit decision.
At this point, the switch controlled by D
2
in each array is connected to
the respective reference voltage and the values of the remaining 3 bits are
determined using the binary search algorithm, as explained in the single-
ended example. The voltages at the input nodes of the comparator, V
ipA
and
V
inA
, during the sampling and conversion phases are shown in Figure 2.6.
Figure 2.5: 4-bit fully dierential switched-capacitor SAR ADC.
11
Figure 2.6: Voltages at V
ipA
and V
inA
during the sampling and conversion phases
for the 4-bit fully dierential switched-capacitor SAR ADC [8].
Since the overall accuracy and linearity of the SAR ADC is primarily
determined by the internal DAC, the switched-capacitor realizations of it
have become very popular in newer SAR ADCs due to their high accuracy
and linearity. A high degree of temperature stability is another advantage
of these capacitive DACs. Moreover, the fully dierential analog signal
path has been preferred respect to a single-ended one for the following main
reasons:
Immunity to common-mode noise.
The input dynamic range is doubled, which relaxes the design require-
ments of the comparator.
12
Chapter 3
Design implementation
3.1 Design Guidelines
The design of the SAR ADC has been conducted focusing on the power
and area constraints while maintaining good linearity performances for the
analog-to-digital conversion. Switched-capacitor arrays are used to imple-
ment both the S/H and DAC while minimizing the area of the unit capac-
itor. Parasitic capacitances and matching properties have been taken into
account during the analysis. Switches are providing the signals to the DAC
and their size has been optimized focusing on the timing requirements. A
low power solution is proposed for the comparator while achieving good noise
performances and speed requirements. The input-oset storage technique
has been chosen for this stage and a dynamic latch has been preferred. The
digital control signals are provided by a successive approximation register.
3.2 Switched-Capacitor Array
The design of the switched-capacitor array is a key aspect for the overall
performance of the entire SAR ADC. Generally, the array is used as:
S/H: the dierential input voltage can be stored at the input nodes of
the comparator using the bottom plate sampling technique [7].
DAC: in combination with the SAR control logic, the switched-capacitor
array can provide the required voltage variations to perform the binary
search.
Usually the capacitive array is the part of the circuit that requires the largest
silicon area due to a large number of capacitors. Dierent design solutions
can be taken into account to reduce the size of the array while maintaining a
good linearity performance for both S/H and DAC. In particular, the struc-
ture of the array can be modied and the unit capacitor can be minimized.
13
However, these design choices can lead to larger parasitic capacitances and
worse matching. For this reason, an accurate and precise analysis is required
in order to choose the best solution.
The analysis should cover also the choice of the type of capacitor. The
available technology oered two main types: poly-poly (cpp) capacitors and
metal-metal (cmm) capacitors. The most relevant parameters describing
these topologies in terms of capacitance, bottom plate parasitic capacitance
and matching parameters are summarized in Table 3.1.
cpp capacitor cmm capacitor
Area capacitance 0.85 fF/m
2
1.25 fF/m
2
Perimeter capacitance 0.021 fF/m 0.111 fF/m
Parasitic area capacitance 105 aF/m
2
12 aF/m
2
Parasitic perimeter capacitance 57 aF/m 36 aF/m
Minimum area 17.24 m
2
25 m
2
Minimum unit capacitance 15 fF 33.47 fF
Matching parameter A
C
1.25% m 0.65% m
Table 3.1: Summary of the most relevant parameters for the available types of
capacitors.
The capacitor matching is described by the following equation:

_
C
C
_
=
A
C

WL
(3.1)
where
_
C
C
_
is the standard deviation of the dierence C of identically
designed capacitors, normalized to their absolute value C. The parameters
W and L dene the geometric size of the capacitor.
Since the MSB is the sign bit, two identical 9-bit capacitive arrays are
required for the SAR ADC. Most of the analyses have been conducted con-
sidering only one capacitive array, extending then the results to the dier-
ential case. For this reason, it is better to dierentiate the least signicant
bit (LSB) denition in the two following cases:
Dierential signal path: the required resolution n of the ADC is 10
bits for a dierential dynamic input range of FS
de
= 4V . The input
signal for the ADC is in fact dierential and each single-ended signal
has a range of 2V. This results in a dierential LSB
de
equal to:
LSB
de
=
FS
de
2
n
=
4V
2
10
3.906 mV (3.2)
Single-ended signal path: since the switched-capacitor DAC is con-
trolled by a 9-bit digital input signal D
IN
, it is possible to dene
14
the single-ended LSB
se
. This value is useful to evaluate the perfor-
mance of each DAC and then estimate the dierential performance
while adding linearly this error, which represents the worst case.
LSB
se
=
V
REFP
V
CM
2
9
=
1V
2
9
1.953 mV (3.3)
Note that, depending on the sign bit, the analog input range of the single-
ended signals becomes either [1.65 , 2.65] V or [0.65 , 1.65] V. However, the
value of the single-ended full scale range FS
se
is equal to 2 V, as expected.
Split Capacitive Array
The most popular switched capacitor DAC is an array of parallel binary-
weighted capacitors [6]. The structure is shown in Figure 3.1 for a 9-bit
DAC where the capacitor C is equal to the unit capacitor chosen. After
being discharged, the bottom plates of the capacitors are connected either
to a reference voltage or to V
CM
, determining an output voltage V
m
which
is a function of the voltage division between the capacitors. The equivalent
circuit of the DAC is shown in Figure 3.2. Considering m as the number
of capacitors connected to the reference voltage V
REFP
, the equation giving
the value of V
m
is the following:
V
m
= V
CM
+ (V
REFP
V
CM
)
m
2
9
(3.4)
Figure 3.1: Binary weighted switched-capacitor array.
As a drawback, the presented capacitive array requires a large area due to
the large number of capacitors. The total capacitance of the array is in fact
2
9
C, which can result also in a large dynamic power consumption. A possible
solution that can be considered is splitting the array in parts using one or
more series capacitors [6]. Maintaining the binary weighted capacitor size
for the sub-arrays and choosing the correct values for the series capacitors, it
is possible to maintain the same ratios for the voltage division, obtaining the
identical equation given in (3.4). For the 9-bit switched capacitor DAC, the
array can be split in two parts (2bw1Cs array), ve parts (5bw4Cs array) or
it can be even realized with a C-2C ladder (C2C array) [9]. These topologies
are shown in Figures 3.3, 3.4 and 3.5 where the total capacitance is in fact
15
Figure 3.2: Binary weighted switched-capacitor array equivalent circuit.
Figure 3.3: 2bw1Cs capacitive array.
Figure 3.4: 5bw4Cs capacitive array.
Figure 3.5: C2C capacitive array.
reduced (e.g., the 2bw1Cs presents a total capacitance of approximately
48.07C).
However, the series capacitors introduce bottom-plate parasitic capacitances
that are aecting the top-plate nodes of the sub-arrays, hence decreasing the
linearity of the ADC. In addition, the matching is also degraded due to the
16
capacitors whose value is a fraction of the unit capacitor, such as
16
15
C and
4
3
C. An accurate analysis of these eects is therefore required in order
to choose a split capacitive array that provides the required linearity and
matching for the DAC, while occupies the smallest chip area.
3.2.1 Capacitive Array Design
Thermal Noise (kTC Noise)
The rst limiting factor for the minimum acceptable size of the capacitors
is the Johnson-Nyquist noise (thermal noise) that is usually referred as kTC
noise for the sampling circuits [6]. Considering that the entire ADC has two
capacitive arrays, the mean-square value expressing the thermal noise for
each array is summed up while considering the SNR of the entire structure.
Since the two arrays are identical, the worst SNR due to the kTC noise can
be written as follows:
SNR
Thermal
=
P
Signal
P
Thermal
= 10log
10
_

_
1
2
_
FS
de
2
_
2
2
k
B
T
C
u
_

_
(3.5)
where k
B
is the Boltzmann constant, T is the temperature expressed in
Kelvin and C
u
is unit capacitor considered. Since for all the dierent split
capacitive array topologies there is always a unit capacitor connected to the
output node of the DAC, this capacitive value has been considered for the
calculation as worst case. Comparing this SNR with the theoretical signal-
to-quantization-noise-ratio (SNQR) of the ADC, it is possible to nd a value
of the capacitor C
u
that returns a negligible kTC noise. The denition of
the SQNR is the following:
SQNR = 10log
10
_

_
1
2
_
FS
de
2
_
2
LSB
de
12
_

_
= 6.02n + 1.76 (3.6)
For a 10-bit ADC, the theoretical SQNR is equal to 62 dB. The value of the
unit capacitor is therefore found considering the following condition:
SNR
Thermal
SQNR (3.7)
That results in the a minimum capacitor values at a temperature T of 300 K
equal to:
C
u
10
6.02n+1.76
10
4k
B
T
_
2
FS
de
_
2
6.55 fF (3.8)
Being 15 fF and 33.47 fF respectively the minimum unit capacitance C
cpp,min
and C
cmm,min
for the technology considered (Table 3.1), the eect of the kTC
noise is not relevant and it can be neglected in the future considerations.
17
Parasitic Capacitances
Every integrated capacitor presents parasitic capacitances between its plates
and the surrounding layers. This parasitics can be therefore summarized in
two groups: top-plate (TP) parasitic capacitances and bottom-plate (BP)
parasitic capacitances, depending on which plate is considered. Since usually
the BP parasitic capacitances presents the highest value, the eect of the
TP parasitic capacitances has been neglected during the presented analysis.
Considering rst the bw capacitive array (Figure 3.1), the BP nodes of all
the capacitors are always connected to a xed voltage value (either to a
reference voltage or V
CM
), hence the parasitic capacitances are not aecting
the DAC characteristic of the output voltage. This is not true for the split
arrays where the series capacitors are adding parasitics on the TP nodes of
the sub-arrays, giving a gain error and decreasing the linearity of the DAC.
As an example, the 2bw1Cs capacitive array is shown in Figure 3.6 where
the BP parasitic capacitance C
p1
of the series capacitor C
s1
has been added.
Note that C
p1
is considered to be connected between the top-plate of the
LSB sub-array and the n-well where the capacitive array is placed. This
well is tied to V
DD
.
Figure 3.6: 2bw1Cs switched-capacitor array with the bottom-plate parasitic ca-
pacitance added.
Both eects can be highlighted in the equation of the output voltage of the
DAC, which is obtained by solving the system of equations given by the
charge conservation principle. Considering the 2bw1Cs capacitive array as
an example, the equivalent circuit of the DAC is shown in Figure 3.7 where
m and p are the sums of the unit capacitors connected in parallel to the
reference voltage in the LSB sub-array (C
69
) and MSB sub-array (C
15
)
respectively. The values of m and p depend on the digital input D
IN
of the
DAC, for example: if D
IN
= 256 = 100...0, then m = 0 and p = 16.
Assuming that all the capacitors are discharged before applying the digital
input signal, the equations given by the charge conservation principle are
the following:
C
p1
(V
CM
V
DD
) = mC(V
L
V
REFP
) + (16 m)C(V
L
V
CM
) +
+
16
15
C(V
L
V
M
) +C
p1
(V
L
V
DD
)
18
Figure 3.7: 2bw1Cs switched-capacitor array equivalent circuit.
0 = pC(V
M
V
REFP
) + (31 p)C(V
M
V
CM
) +
16
15
C(V
M
V
L
) (3.9)
Solving the previous system of equations, the output voltage V
M
of the DAC
is:
V
M
= V
CM
+(V
REFP
V
CM
)
_
16(m+ 16p)C
8192C + 481C
p1
+
15pC
p1
8192C + 481C
p1
_
(3.10)
While not considering the parasitic capacitance (C
p1
= 0) the equation is
reduced to the output voltage equation of an ideal 9-bit DAC:
V
M
= V
CM
+ (V
REFP
V
CM
)
m+ 16p
512
(3.11)
Comparing (3.10) with (3.11) it is therefore possible to note how the parasitic
capacitance C
p1
is aecting both gain error and linearity.
Focusing on the linearity of the DAC, the integral nonlinearity (INL)
graph can be estimated for each presented topology. This can be done
by solving the equations given by the charge conservation principle while
considering the BP parasitic capacitances, nding the equation of the output
voltage and proceeding then with the INL estimation. The INL values have
been found comparing the eective output voltage with its best tting line
in order to eliminate the gain error [4]. As an example, the estimated INL
graph for each split capacitive array topology is shown in Figure 3.8 where
minimum-size cmm capacitors have been used. The binary weighted solution
has not been considered since no BP parasitic capacitances are connected
to the TP node of the array. Note that each graph has been found while
considering only one capacitive array, hence the LSB considered is referred
to the single-ended case, that has been estimated in (3.3). The results can
be extended to the dierential case since both capacitive arrays in the ADC
19
are identical. From the INL results shown in Figure 3.8, it is possible to
notice that the more the array is divided into parts, the more it is aected
by the parasitic components. Hence, the area of the unit capacitor should
be increased in order to reduce the parasitic capacitances and limit this
eect. The tradeo between the linearity and required area will be therefore
considered while comparing all the results, aiming the following requirement:
INL 0.5LSB
se
(3.12)
Figure 3.8: INL graph estimation of each split capacitive array.
Matching of the Capacitors
The matching of the capacitors is another key aspect that has to be taken
into account in order to achieve a desired performance from the capaci-
tive DAC. The matching properties of capacitors depend on the technology
used, the capacitor size and the layout employed. While for the layout
design a common-centroid technique has been considered (Section 3.6), in
this section, a pre-layout estimation of the capacitors matching has been
studied [10]. The output voltage of each 9-bit DAC for the half-range dig-
ital input code (D
IN
= 256 = 100...0) presents the worst case in terms of
mismatch among the capacitors [11], hence the standard deviation of this
voltage should be constrained with the following condition:
3(V
M,D
IN
=256
) 0.5LSB
se
(3.13)
20
where V
M,D
IN
=256
is the output voltage value for the half-range digital input
code and is ideally equal to:
V
M,D
IN
=256
= V
CM
+
V
REFP
V
CM
2
= 2.15 V (3.14)
If (3.13) is satised, the linearity performance of the DAC is met. Note that
if the requirement is met considering only one capacitive array, the result
can be extended also for the dierential case. Considering the parametric
expression of the output voltage of the DAC and assuming that the mis-
match of each capacitor is independent, it is possible to estimate both the
mean value and the standard deviation of (V
M,D
IN
=256
). The calculations
have been conducted using the properties of the variance from the statis-
tics theory. A simplied example of this type of calculation is reported in
Appendix 5.2 for a 3-bit capacitive DAC. This type of estimation has been
conducted for each capacitive array topology presented before. The values of
(V
M,D
IN
=256
) for both the bw and 2bw1Cs capacitive array are presented
in Table 3.2, where
C
is the mean value of the unit capacitor considering
both area and perimeter capacitance (Table 3.1) and
C
is the standard
deviation of the unit capacitor, that is dened as follows:

C
=
_
C
C
_

C
=

_
C
C
_

2

C
(3.15)
Capacitive array topology (V
M,D
IN
=256
)
bw (V
REFP
V
CM
)

3
C
32

2
C
2bw1Cs (V
REFP
V
CM
)

C
_
24591
2
C
+ 15
2
C
1024
2
C
Table 3.2: Examples of the resulting parametric estimation of (V
M,D
IN
=256
) for
the bw and 2bw1Cs capacitive arrays.
Since both
C
and
C
depend on the area of the unit capacitor, by substi-
tuting the parametric expressions in (3.13), one can determine the minimum
unit capacitor area that satises the condition. The results found with the
analytical method have been compared with MATLAB simulations where
the (V
M,D
IN
=256
) value has been calculated considering the capacitor vari-
ables as 100-points gaussian distributions. The comparison shows that the
proposed method overestimates the minimum unit capacitor area and this is
probably due to the independent-variables assumption. However, this type
of analysis can still be used to roughly determine the unit capacitance with
some margin.
21
Results and Considerations
Summarizing all the results found in the previous analyses, one can decide
the capacitive array topology, the type of capacitor and its unit area that
best t for our application. Since the kTC noise can be considered negligi-
ble, the minimum unit capacitor area WL that satises both the parasitic
capacitance (PC) condition (3.12) and the capacitive matching (CM) con-
dition (3.13) are summarized in Table 3.3.
PC CM Overall
WL [m
2
] WL [m
2
] WL [m
2
] # C
u
C
Tot
[fF]
bw
cpp min min min 512 7682
cmm min min min 512 17137
2bw1Cs
cpp 17.28 min 17.28 48.07 722
cmm min min min 48.07 1609
5bw4Cs
cpp 140.63 >1000 >1000 - -
cmm 38.03 105 105 20.50 2784
C2C
cpp 248.27 >1000 >1000 - -
cmm 74.95 >1000 >1000 - -
Table 3.3: Summary of the results for the design of the capacitive array.
The total number of unit capacitors required in the array is # C
u
and C
Tot
is
the total capacitance of the array. The min value states that the minimum-
size unit capacitor satises the considered design condition. On the other
hand, when a unit capacitance area less than 1000 m
2
cannot satisfy the
matching condition for a certain condition, the topology is discarded. As
expected, it is possible to notice how the split topologies are aected by
both parasitics and mismatch. In particular, the 5bw1Cs and C2C can be
discarded since they require a very large unit capacitor mostly due to the
presence of BP parasitic capacitances. Hence, the 2bw1Cs capacitive array
has been chosen since it meets the requirements with the minimum unit
capacitance value. Furthermore, cmm capacitors have been preferred due
to their better matching characteristic and less parasitic capacitances.
Split Capacitive Array Realization
The 2bw1Cs capacitive array chosen includes a series capacitor C
s1
with a
value of
16
15
C whose layout design could be cumbersome. In addition, its
matching properties could be worse than those of the other capacitors since
22
its capacitance is not an integer multiple of the unit capacitor C. Therefore,
the modied split capacitive array presented in [13] has been adopted in this
work. The modied array, shown in Figure 3.9, diers from the common
2bw1Cs structure for the following two aspects:
The series capacitor is substituted with a unit capacitor, i. e., C
s1
is
equal to C.
The additional parallel capacitor C
e
of the LSB sub-array is removed.
Figure 3.9: Modied split capacitive array.
In order to check the accuracy of the proposed solution, it is possible
to study the equivalent circuit of the DAC, which is shown in Figure 3.10.
Assuming that all the capacitors are discharged before applying the digital
input signal and neglecting the eect of the parasitic capacitance (C
p1
= 0),
the equations given by the charge conservation principle are the following:
0 = mC(V
L
V
REFP
) + (15 m)C(V
L
V
CM
) +C(V
L
V
M
)
0 = pC(V
M
V
REFP
) + (31 p)C(V
M
V
CM
) +C(V
M
V
L
)
(3.16)
Figure 3.10: Modied split capacitive array equivalent circuit.
Solving the previous system of equations, the output voltage V
M
of the DAC
is found as follows:
23
V
M
= V
CM
+ (V
REFP
V
CM
)
m+ 16p
511
(3.17)
Comparing (3.11) with (3.17), it can be noticed that a gain error of 1 LSB
introduced by the proposed array. However, this is not severe since the
gain error caused by the input capacitance of the comparator is even larger
(Appendix 5.1).
DAC Post-Layout Simulations on Cadence
The reliability of the previous analyses can be veried by simulating the
DAC with Cadence. First of all, the linearity of the DAC is evaluated by
running an INL analysis which, however, takes into account only the eects
of the parasitic capacitances. The results given by the pre-layout simulations
match the previous estimated values. Nevertheless, the performance of the
DAC decreases while checking the post-layout simulations. This is due to
the two following aspects:
The parameters describing the dierent capacitor technologies (Ta-
ble 3.1) are dened as mean values. The minimum unit capacitance
can be considered as a boundary case, hence the estimations could be
not accurate enough.
The post-layout simulations take into account the coupling eects be-
tween the capacitors and wires, that are dicult to estimate. This
aspect can be critical since the unit capacitance could be comparable
to the parasitic and wiring capacitances.
For this reason, the layout design of the capacitive array has been conducted
in order to reduce the parasitic eects and maximize the DAC performance.
The common-centroid technique [15] has been chosen to reduce the com-
plexity of the structure and, hence, minimize the wiring. In addition, while
the metal layers MET2 and MET3 have been reserved for the capacitors
and the internal connections, MET1 has been used to wire the input signals
and to reduce capacitive unbalances of the structure due to the asymmetric
structure. The capacitive array oorplan is shown in Figure 3.11 where C
sd
is the dummy capacitor of C
s1
.
The modied split capacitive array implemented with minimum unit capac-
itors (C
u
=33.47 fF) manifests an INL that is always less than 0.5 LSB
se
.
However, the unit capacitor C
u
has been nally increased to 64.36 fF in
order to have some margin on the performance. The INL graphs of both
cases are shown in Figure 3.12.
The DAC non-linearity caused by the capacitance mismatch has been
veried with a 1000-runs Monte Carlo simulation. The worst-case value of
V
M,D
IN
=256
has been considered and measured. The following results have
been obtained:
24
Figure 3.11: Floorplan of the capacitive array.
Figure 3.12: INL graphs of the 9-bit DAC comparing two dierent values for the
unit capacitance.
25
(V
M,D
IN
=256
) = 2.150 V
(V
M,D
IN
=256
) = 82.30 V
It is possible to compare the standard deviation of V
M,D
IN
=256
with the
0.5 LSB
se
reference value as follows:
3(V
M,D
IN
=256
) = 246.90 V 0.5 LSB
se
1.953 mV (3.18)
Hence, the estimations about the DAC non-linearity are reliable.
Dynamic Power Consumption
The dynamic power consumed in the array can be estimated considering
both the power required by the DAC and the power delivered during the
sampling phase [14]. Considering only one capacitive array, it is possible to
estimate these values as follows:
P
DAC
= f
S
9

i=1
E
i
f
S
C
Charged
V
2
REF
(3.19)
P
Samp
= f
S
E
Samp
= f
S
C
Charged
_
FS
se
2
_
2
(3.20)
where f
S
is the sampling frequency which is equal to 1.28 MS/s, E
i
the
energy required by the DAC for the i-th digital input applied, C
Charged
is
the total capacitance charged during the DAC phases (note that the voltage
across the series capacitor is assumed to remain the same) and is equal to
46C, V
REF
is the voltage at which each capacitor is charged and is equal to
1 V and E
Samp
is the energy required by the sampling phase. Considering
both capacitive arrays, their total dynamic consumption is therefore the
following:
P
Tot
= 2(P
DAC
+P
Samp
) 2f
S
C
Charged
_
V
2
REF
+
_
FS
se
2
_
2
_
(3.21)
Which results in a total power consumption P
Tot
equal to 15.16 W. Since
the total power required to charge the array is proportional to C
Charged
, it
is favorable to split the array. For a conventional binary weighted array, the
equivalent charged capacitance is 512C which leads to a P
Tot
of 168.72 W
for the same unit capacitance.
The previous estimated values can be veried by a simple simulation
on Cadence. Considering rst the DAC phase, the switching behavior can
be simplied in two steps: while the top-plate nodes of both MSB and
LSB sub-arrays are rst maintained at V
CM
, the bottom-plate nodes of
all capacitors excluding C
s1
are switched between V
REFP
and V
CM
. The
26
switching frequency of this circuit has to be equal to 1.28MS/s that is the
sampling frequency f
S
. Hence, the power consumed by the DAC can be
estimated as follows:
P
DAC,Sim
(V
REFP
V
CM
)I
Avg
(3.22)
where I
Avg
is the average current delivered by the reference voltage source
calculated on 1000 cycles. For the sampling phase, the switching behavior
is the same and, instead of V
REFP
, the maximum input voltage value is
applied. Since this value is theoretically equal to 2.65V, that is actually
V
REFP
, both the circuit and the conditions are exactly equal to the previous
case. Hence, P
Samp,Sim
is equal to P
DAC,Sim
, as obtained also in the previous
calculations. The total dynamic consumption estimated before is veried by
this simulation, as it can be noticed from the results:
P
Tot,Sim
= P
DAC,Sim
+P
Samp,Sim
2(V
REFP
V
CM
)I
Avg
= 15.59 W
(3.23)
3.3 Switches
Each capacitive array requires a relatively high number of switches that are
used both for passing signals and reset the voltage values at specic nodes.
A design analysis based on the settling time and sampling linearity has been
conducted in order to optimize the size of each switch.
3.3.1 Switch Structures
The switched-capacitor array is used both for sampling the input signal and
providing comparing reference voltages required by the SAR algorithm. In-
put and reference signals are applied to the bottom-plate of the capacitors
using switches. On the other hand, the top-plates of the capacitors belong-
ing to the LSB sub-array are reset by applying the common-mode voltage
V
CM
through only one switch (Figure 3.13) while the node V
M
is reset by
the preamplier stage during the oset-cancellation phase, as shown in Sec-
tion 3.4. For this reason, the switches used can be divided into two groups:
Bottom-plate switches: they pass the input voltage signal, the common
voltage or one of the two reference voltages to the bottom-plate of the
capacitors.
Top-plate switch: it resets the voltage value at the V
L
node passing
the common voltage.
The structure of the entire capacitive array with the switches is shown in
Figure 3.13 where V
BP
can be one of the four voltages mentioned before and
here summarized with their voltage values or range:
27
0.65 V V
Sig
2.65 V
V
CM
= 1.65 V
V
REFP
= V
CM
+V
REF
= 1.65 V + 1 V = 2.65 V
V
REFN
= V
CM
V
REF
= 1.65 V 1 V = 0.65 V
Figure 3.13: Capacitive array with ideal bottom-plate and top-plate switches.
Starting rst the design of the BP switches, they can be organized choos-
ing one of the following main structures:
Mux-like (ML) structure: four dierent switches are connected to the
bottom plate of each capacitor in the array, respectively passing the
voltages V
Sig
, V
REFP
, V
REFN
and V
CM
. Figure 3.14 shows the struc-
ture connected to the bottom plate of one capacitor.
Shared-block (SB) structure: the bottom plate of each capacitor is di-
rectly connected to two switches only. While one switch is passing
V
CM
, the other is connected to a structure shared among all the ca-
pacitors belonging to the array. This structure is made up of three
switches that are providing the remaining voltages (V
Sig
, V
REFP
and
V
REFN
). This topology is shown in Figure 3.15 where the shared block
has been highlighted.
The SB structure has been implemented because it requires a less compli-
cated control logic and routing due to the shared structure. Although the
switches are connected in series, this solution does not need very low switch
on-resistance. Still good performances can be achieved while maintaining
small gate-width and minimum gate-length for all the transistors used.
Only NMOS pass-transistors (NMOS PTs) have been used to implement
the switches passing the negative reference voltage V
REFN
and common
voltage V
CM
while PMOS pass-transistors (PMOS PTs) are used to provide
the highest reference voltage V
REFP
. On the other hand, transmission-
gates (TGs) are preferred while passing the input voltage, whose range is
from 0.65 V to 2.65 V. Considering the SB structure, the switch TG
BP
that
controls the passage of V
Sig
, V
REFP
and V
REFN
for each capacitor is also a
28
Figure 3.14: Mux-like structure for the switches of the capacitive array.
Figure 3.15: Shared-block structure for the switches of the capacitive array.
transmission-gate. The on-resistance values of both NMOS PT and PMOS
PT depend on the input signal V
Sig
and their denitions are shown in (3.24)
and (3.25) respectively [12].
R
on,N
=
1

n
C
ox
_
W
L
_
N
(V
DD
V
Sig
V
TN
)
(3.24)
R
on,P
=
1

n
C
ox
_
W
L
_
P
(V
Sig
|V
TP
|)
(3.25)
29
where C
ox
is the MOS gate capacitance per unit area,
W
L
the aspect ratio
and V
T
the threshold voltage. Since the electron mobility
n
of the NMOS
transistors is approximately three times larger than the hole mobility
p
of
the PMOS transistors for our technology, a scaled value of the minimum
gate-width can be used while sizing the PMOS switches. Hence, assigning
W
P
for the gate-width of the PMOS transistor and W
N
the gate-width of
the NMOS transistor, the relation between them is expressed as follows:
W
P
= 3W
N
(3.26)
Therefore, following the relation given by (3.26) and minimum gate-length
for the design of all the PTs, it is possible to reach a low on-resistance
value for the PMOS PTs that is comparable to the one of the minimum-
size NMOS switches for the respective input voltage ranges. Using the
same design choice for the design of the transmission-gates, the variation
of its on-resistance as a function of the input voltage will be much less
compared to that of a pass-transistor. This result is shown in Figure 3.16
where this function has been plotted considering dierent values for W
N
and maintaining the ratio given by (3.26). Finally, as a reference value, the
minimum size and aspect ratio for the gate of the NMOS transistors of the
switches provided by the technology used in this thesis are the following:
_
W
L
_
N,min
=
W
min
L
min
=
0.7 m
0.35 m
=
2
1
(3.27)
3.3.2 DAC Settling Time
Most of the switches has been sized considering the settling time require-
ment of the DAC. During the settling phase, all the BP switches are in-
volved except for the shared transmission-gate that is directly passing the
input signal. It is therefore useful to study the RC equivalent model of
the switched-capacitor array where the switches are represented with their
on-resistance.
The settling time of the output voltage provided by the 9-bit DAC
reaches its largest value when the digital input is switched from D
IN
= 0
to D
IN
= 256, since the voltage dierence between the initial and the -
nal value presents its maximum value which is V
V
REF
2
= 0.5 V . For
the digital input value D
IN
= 256, the bottom plate of the capacitor C
1
is
therefore connected to the series of the switches composed by TG
BP
and
one pass-transistor (NMOS or PMOS depending on the reference voltage)
while the bottom-plate of each other capacitor is connected to V
CM
through
the NMOS switch. Note, at this moment the TP reset switch is turned o.
The equivalent RC model is shown in Figure 3.17.
In order to obtain a rough estimation of the settling time, it is gener-
ally common to use the Open Circuit Time Constant (OCTC) analysis that
30
Figure 3.16: Dependance of the on-resistance value of the transmission-gate on the
input voltage value. While maintaing the relation (3.26), the value of W
N
has been
swept from 0.7 m to 7 m.
can be used to estimate the dominant time constant of the network. Un-
fortunately, in the case studied, this method is not accurate because there
are several poles having comparable frequencies. For this reason, another
approach has been used considering the following assumptions:
For the LSB sub-array in Figure 3.17, each branch has a time constant
whose value is comparable with the others. Hence, as an assumption,
the voltage at the bottom-plate of each capacitor connected to the
pass-transistor providing V
CM
is considered to be equal during the
transition. Therefore, these nodes can be shorted in the equivalent
circuit and the equivalent impedance of the LSB sub-array will be:
Z
BP,C
s1

1
15sC
+
R
PT,V
cm
4
(3.28)
The impedance seen from the top-plate of the splitting capacitor C
s1
to V
CM
is approximately the following:
Z
TP,C
s1
=
1
sC
+Z
BP,C
s1

1
sC
+
R
PT,V
cm
4
(3.29)
31
Figure 3.17: Equivalent RC model of the 9-bit DAC for D
IN
= 256.
The resulting equivalent circuit is shown in Figure 3.18.
At this point, the same assumption can be made once again since the
time constants of each branch are still comparable. The bottom-plate
nodes of each capacitor connected to the pass-transistor providing V
CM
are shorted together and the nal equivalent model is shown in Fig-
ure 3.19.
Figure 3.18: Simplied equivalent RC model of the 9-bit DAC for D
IN
= 256.
32
Figure 3.19: First-order equivalent RC model of the 9-bit DAC for D
IN
= 256.
Now the equivalent model corresponds to a simple rst order RC network
and the settling time can be easily estimated. Considering V
REFP
as refer-
ence voltage, the step response of the voltage node V
M
is described by the
following expression:
V
M
(t) = V
M
0
+
_
V
CM
+
V
REFP
V
CM
2
V
M
0
_
(1 e
t/
) (3.30)
where V
M
0
is the instant voltage value of V
M
when the digital input is
switched from Din=0 to Din=256 and it is equal to:
V
M
0
= V
CM
+ (V
REFP
V
CM
)
R
PT,V
CM
8
R
PT,V
CM
8
+R
PT,V
REFP
+R
TG,BP
(3.31)
Once the voltage signal V
M
(t) is settled, it reaches the nal value due to the
voltage divider given by the capacitors. Therefore, the dierence between
the nal and initial voltage is equal to:
V = V
CM
+
V
REFP
V
CM
2
V
M
0
(3.32)
While the time constant of the RC network is calculated as follows:
= (
R
PT,V
CM
8
+R
PT,V
REFP
+R
TG,BP
) 8C (3.33)
The settling time is then obtained by considering the time needed by the
output voltage to reach the nal value within an error of 0.5LSB
se
, i.e.:
V
M
(t
sett
) = = 0.5LSB
se
(3.34)
33
From Equation (3.30), the settling time is found as follows:
t
sett
= ln
_

V
_
(3.35)
Considering minimum-size switches, the settling time t
sett,calc
estimated
from (3.35) for the worst case of D
IN
is 12 ns. The ADC presented in
this work reserves approximately 60 ns for the DAC settling time and the
preamplication. In order to relax the requirements on both speed of the
preamplier and output resistance of the circuit providing the reference volt-
ages, a DAC settling time less than 5 ns is aimed. This can be easily achieved
by increasing the size of the switches in order to reduce their on-resistance,
calculating again the settling time and checking if it is short enough. In this
work the following dimensions have been used:
_
W
L
_
PT,V
REFN
=
6
1
_
W
L
_
PT,V
REFP
=
18
1
_
W
L
_
TG,BP,N
=
6
1
_
W
L
_
TG,BP,P
=
18
1
_
W
L
_
PT,V
CM
=
4
1
where PT
V
REFN
and PT
V
REFP
are the pass-transistors providing V
REFN
and
V
REFP
respectively, PT
V
CM
is the pass-transistor passing V
CM
and TG
BP,N
and TG
BP,P
the NMOS and the PMOS transistors composing the transmis-
sion gate TG
BP
. Considering V
REFP
as reference voltage, the settling time
t
sett,calc
calculated using Equation (3.35) is 4.10 ns, while the Cadence simu-
lation of the circuit returns t
sett,sim
= 5.17 ns. Some values calculated using
this method are reported in Table 3.4 and compared with the results given
by the simulation using dierent switches sizes and both reference voltages.
As shown, it is possible to obtain a rst rough estimation of the worst-case
settling time with this method.
t
sett,calc
[ns] t
sett,sim
[ns]
Minimum-size switches
V
REFP
= 2.65 V 12.00 13.91
V
REFN
= 0.65 V 11.87 13.15
Chosen switches
V
REFP
= 2.65 V 4.10 5.17
V
REFN
= 0.65 V 4.05 5.18
Table 3.4: Calculated and simulated settling time for D
IN
transiting from 0 to 256.
3.3.3 Other Switches
So far, all the bottom-plate switches have been sized except the transmission-
gate TG
Sig
which is directly connected to the input signal. This has been
34
sized to achieve a short settling time and good linearity, which will be further
discussed and analyzed in Section 3.4. Finally, for the top-plate NMOS
pass-transistor which resets the V
L
node, since low parasitic capacitance are
required on that node (Appendix 5.1), a minimum-size transistor has been
used. The LSB-subarray presents a relatively small equivalent capacitance,
hence even the minimum-size switch is sucient to perform the reset. The
aspect ratios of the transistors composing these switches are summarized as
follows:
_
W
L
_
TG,Sig,N
=
10
1
_
W
L
_
TG,Sig,P
=
30
1
_
W
L
_
PT,Res
=
2
1
3.4 Comparator
The comparator is an essential part in the SAR ADC to perform the binary
search algorithm. It has to discriminate voltage values as small as the dier-
ential LSB
de
. In addition, since it is usually the most power-hungry part
of the ADC, a power-ecient solution has to be found during the design.
3.4.1 Overview
During the binary search phase, the comparator has to discriminate which
of the MSB sub-array top-plate nodes has higher voltage. This information
is passed then to the SAR logic control which can provide the correct digital
input value for the DAC. Ideally, only one latch is required to perform the
comparison. However, this is not feasible in reality because the latch usually
has a very high oset voltage and can introduce large kickback noise. In this
work, the comparator is composed of two preampliers and a latch, as shown
in Figure 3.20. The latch is then loaded with a digital logic that reduces the
metastability eect.
Figure 3.20: Structure of the comparator stage.
The proposed structure has been chosen for the following main reasons:
Preamplication is required to overcome the oset voltage of the latch,
especially for small input voltage values.
Oset-cancellation techniques can easily be applied to the preamplier
stage, allowing a correct decision for the comparison.
35
The large kickback noise coming from the latch and aecting the ca-
pacitive array is reduced due to the presence of the preamplier.
There is a minor kickback noise given by the preampliers. This can
be reduced using two preamplier stages while limiting the voltage
gain of the rst one.
3.4.2 Latch
In order to derive the design choices for the preamplier, the latch stage is
rst presented. The dynamic latch [16, 17] shown in Figure 3.21 has been
chosen to reduce the power consumption. When the control signal LatxS is
low, the reset phase is performed and the output nodes are pulled to V
DD
.
During the regeneration phase, LatxS is set to 1 and the circuit determines
which input signal is higher with the aid of the two cross-coupled inverters
M19, M23 and M20, M22. The decision is therefore taken on the rising edge
of the signal LatxS, as shown in Figure 3.22.
Figure 3.21: Dynamic latch.
Since this latch is dynamic, the power consumption is reduced. This is true
because the latch consumes power only when it is triggered. Otherwise,
during the reset phase, no static current is owing through it. In addition,
it presents a high speed operation because the NMOS transistors M17-20
immediately enter the active region when the latch is triggered. This is
happening since, immediately after the reset phase, the source node voltages
of M19 and M20 are equal to V
DD
V
T
while the drain node voltage of M16
is V
T
below the latch input common mode voltage [18].
36
Figure 3.22: Output response of the latch for a dierential sinusoid input signal.
Metastability is an important issue while designing comparators, hence
the logic shown in Figure 3.23 has been chosen as load of the latch in order to
limit its inuence. During the reset phase (LatxS signal low) the output logic
states Q and Q are kept at the same value, while during the regeneration
phase (LatxS signal high) they provide the output of the result given by the
latch. In case of a metastability error, both output nodes of the latch remain
close to V
DD
and the output logic maintains the previous values. Hence, the
error due to metastability is bounded in a range equal to 1 LSB
de
.
Figure 3.23: Load of the dynamic latch.
Since the input capacitance of the OR gates is approximately 4 fF, the
performance of the latch has been tested considering a generic output load
C
L
of 20 fF in order to have some margin. Considering the maximum transi-
tion of 3.3 V as reference value for the dierential output, both regeneration
and reset time have been measured to be always less than 3 ns (Figure 3.24),
37
even for the voltage input as small as 1 LSB
de
. However, given that the
following OR gates can toggle with a smaller than 3.3 V dierential output
voltage and the input signal of the latch is already amplied by the previous
stages, enough margin is reserved. Therefore, for the timing diagrams, the
interval between the rising edge of LatxS and a valid output logic state of
Q is chosen to be equal to 3 ns.
Figure 3.24: Output response of the latch during the regeneration phase..
The power consumption of the latch can be estimated considering the
following formula where I
Avg
is the average current provided by the power
supply:
P
Latch,Sim
V
DD
I
Avg
(3.36)
Considering that both the regeneration and reset phase are performed ten
times over a 781 ns conversion time and 1000 cycles are simulated, the esti-
mated power consumption of the latch P
Latch,Sim
is approximately 7.68 W.
The input-referred oset voltage of the latch, V
OS,Latch
, has been esti-
mated using the test bench [19] shown in Figure 3.25. The common-mode
voltage V
CM
is applied to an input node of the latch while a ramp signal is
controlling the other one. The ramp signal starts with a value lower than
V
CM
and increases with 1 mV steps. The regeneration phase is therefore
performed for each voltage level given by the ramp signal. Ideally, the latch
starts toggling when the ramp signal is larger than V
CM
. In a real circuit,
the corresponding dierential input voltage is equal to V
OS,Latch
instead of
zero, as shown in Figure 3.25. The value of the input-referred oset voltage
38
of the latch is therefore estimated by carrying out a 1000-runs Monte Carlo
simulation and measuring the dierential input voltage. The results are the
following:
(V
OS,Latch
) = 122 V
(V
OS,Latch
) = 13.294 mV
Figure 3.25: Test bench for the input-referred oset voltage estimation of the latch.
Since the standard deviation of V
OS,Latch
is much larger than its mean value,
an estimation of the input-referred oset voltage value is obtained as follows:
V
OS,Latch
3(V
OS,Latch
) = 39.883 mV (3.37)
The oset value V
OS,Latch
of 40 mV will be considered in the forthcoming
calculations. Note, from the above estimation, the preamplier stage is
essential since the smallest dierential input to be discriminated by the
comparator should be less than 1 LSB
de
.
3.4.3 Preamplier
Requirements
The preamplier stage is mainly added to suppress the eect of the large
kickback noise and oset voltage from the latch. It is a critical part in this
design, and the following specications have to be met:
The preamplier has to overcome the input-referred oset voltage
V
OS,Latch
of the latch, which is approximately 40 mV. Since the mini-
mum dierential input value to be discriminated by the ADC is LSB
de
,
a required voltage gain A
V,OS
of the preamplier can be estimated as
follows:
A
V,OS
=
V
OS,Latch
LSB
se
=
40 mV
3.906 mV
= 10.23 21 dB (3.38)
39
A 9 dB of margin can be added and thus the minimum voltage gain
A
V,min
is equal to:
A
V,min
= 21 dB + 9 dB = 30 dB = 32 (3.39)
Considering 12 cycles for the SAR analog-to-digital conversion (Sec-
tion 3.5) and 1.28 MS/s as sampling frequency, each cycle lasts 65 ns.
In addition, reserving approximately 10 ns for both the regeneration
phase of the latch and the settling time of the DAC, the preamplica-
tion of the input signal has to be performed in a time interval t
PreAmp
less than 55 ns. In other words, the minimum dierential input value
LSB
de
has to be correctly amplied during t
PreAmp
.
The power consumption of the entire ADC should be less than 1 mW,
hence reserving half of this value to the preamplier stage, the maxi-
mum power consumption for this part will be:
P
PreAmp,max
=
P
ADC,max
2
= 500 W (3.40)
High values for the input capacitance of the preamplier result in a
large gain error for the DAC (Appendix 5.1). Therefore, the gate-area
of the input transistors has to be minimized.
Two-stage preamplier and kickback noise
The preamplier chosen has two stages and its structure is shown in Fig-
ure 3.26. Since the required minimum gain is not particularly high for
this type of structure, diode-connected PMOS transistors have been used as
loads for the rst stage while the second stage employs a resistive common-
mode feedback (R-CMFB) circuit [12, 20] where both resistors R are 110 k.
Therefore, no active common-mode feedback network is required, leading to
a low power consumption. Furthermore, the area occupied by the resistors
is small because the process used provides a high-ohmic resistor option.
Since a small unit capacitor is used for the capacitor array, the preampli-
er stage can inuence the charge redistribution in the capacitor array due
to its kickback noise. When the input signal is sampled on the top-plate
node (V
M
) of the MSB sub-array, this value is immediately amplied by
the preamplier. However, due to the presence of the gate-to-drain overlap
capacitance C
GD1
of the input transistor, the larger variation of the output
voltage of the rst preamplier can aect the node V
M
through this capaci-
tive path (Figure 3.27). This eect is called kickback noise [21]. If there is a
positive voltage step of V
M
, the kickback noise eect will decrease this step
size like that in a negative feedback loop. Clearly, the kickback noise also
aects the reference voltages given by the DAC during the binary search.
40
Figure 3.26: Two-stage preamplier.
Figure 3.27: Kickback noise in the rst stage of the preamplier.
The analysis with the linear small-signal model of the transistors shows
that the given error is proportional to the voltage gain of the preamplier,
as expected. Hence, the input voltage values of the comparator should
be always scaled by the same factor, avoiding any distortion on the signal.
However, since the range of the input voltage is relatively large (equal to 2 V
considering only one of the two branches), the rst stage of the preamplier
may saturate. In this case, the output response of the preamplier is not
linear anymore and the kickback noise is causing a distortion on the input
signal and, hence, limiting the linearity of the ADC.
For this reason, a two-stage structure has been chosen for the pream-
plier where the rst stage has a low voltage gain, which helps to reduce
the error caused by the kickback noise. Note that this design choice allows
41
also the use of small input transistors, leading to a small input capacitance
from the preamplier as well. The linearity of the sampled signal has been
evaluated with a FFT analysis. For this simulation, a dierential sinusoidal
voltage signal has been applied to the input of the ADC with peak-to-peak
amplitude close to FS
de
and a frequency equal to BW
Sig
. This results in
an SNDR equal to 69.92 dB (ENOB=11.32). Since the value obtained is
larger than 62 dB (ENOB = 10), a sucient linearity is achieved during the
sampling phase. However, it is preferable to have some margin on this value.
This is obtainable by reducing the eect of the kickback noise even more
with the the capacitive neutralization technique [21, 22]. Since the output
voltages are aecting the input nodes through the gate-drain overlap capac-
itances of the input transistors, it is possible to add two dummy transistors
that approximately present an input capacitance close to C
GD1
as shown in
Figure 3.28. To achieve this requirement, the dummy transistors are sized
using the same channel length and half of the width of the input pair M1,
M2:
_
W
L
_
Dummy
=
1
2
_
W
L
_
1
(3.41)
Therefore, the kickback noise through these overlap capacitances is reduced
and the improvement on the sampling linearity can be checked again with
a FFT analysis that returns an increased SNDR of 81 dB (ENOB=13.21).
Figure 3.28: First preamplier stage with dummy transistors using the capacitive
neutralization technique.
42
Oset Cancellation and Sampling
The oset of the comparator, which is constant and signal-independent,
causes also an oset of the ADC. This problem can be avoided limiting
or cancelling the oset at the comparator stage. The most famous oset
cancellation techniques [12, 23] are summarized as follows:
Input oset storage (IOS): two relatively large series capacitors are
added to the input nodes of the comparator and the preamplier is
placed in a unity-gain negative-feedback loop operation. The oset
of the circuit is therefore measured and stored across the capacitors.
The residual input-referred oset voltage after the cancellation is the
following:
V
OS,Residual
=
V
OS,PreAmp
1 +A
V
+
Q
C
+
V
OS,Latch
A
V
(3.42)
where C is the value of each series capacitor and Q the charge-
injection due to the mismatch of the loop switches. As a drawback, this
technique requires a high gain value A
V
and also a large capacitance
to limit the the charge-injection error.
Output oset storage (OOS): the series capacitors are now added to
the output nodes of the preamplier and the input nodes of the pream-
plier shorted together during the oset cancellation. The nodes of the
capacitors not connected to the preamplier are also shorted together
and thus the amplied oset voltage is stored on the capacitors. The
residual oset is given by the following equation:
V
OS,Residual
=
Q
A
V
C
+
V
OS,Latch
A
V
(3.43)
Hence, the oset of the preamplier is completely cancelled and the
value of the series capacitor can be chosen smaller than before. How-
ever, since the preamplier is performing an open-loop amplication,
it should not saturate. For this reason, the voltage gain is usually
limited to be less than 10.
Active oset cancellation: The main drawback of the previous oset
cancellation techniques is that they introduce capacitors in the signal
path. A possible solution is to perform the oset cancellation using an
auxiliary amplier. The introduced amplier can sense and subtract
the oset of the stage in a negative feedback loop. Obviously, this
technique is adding a new active element to the circuit, increasing the
overall power consumption.
43
Figure 3.29: Closed-loop operation of the preamplier performing the input oset
storage.
In order to achieve a low-power operation for the presented SAR ADC,
the active oset cancellation can be discarded. Also the OOS technique
is not a promising solution because it requires additional output series ca-
pacitors and limits the gain of the preamplier. Hence, the IOS has been
chosen since the capacitor arrays can be used as input series capacitances
and there is no limitation on the voltage gain. In addition, the entire array
of capacitors present a large equivalent capacitance that reduce the residue
oset caused by the charge injection mismatch, as shown in Equation (3.42),
while providing a sucient phase margin during the closed-loop operation
of the preamplier.
In order to better understand the oset cancellation technique chosen,
the equivalent circuit of the preamplier placed in the closed-loop operation
is shown in Figure 3.29 where the oset voltage V
OS,PreAmp
is added and each
capacitive array is replaced with a series capacitor, respectively. Dening
V
in,d
and V
out,d
as the dierential input and output voltage of the entire
preamplier, the system of equations to be solved is the following:
V
out,d
= V
in,d
V
out,d
= (V
in,d
+V
OS,PreAmp
)(A
V
) (3.44)
where the DC gain of the preamplier is equal to A
V
(unity-gain negative-
feedback). Solving the above equations, the result is the following:
V
out,d
= V
OS,PreAmp
A
V
1 +A
V
(3.45)
Referring the value obtained back to the input:
V
in,diff
=
V
out,diff
A
V
=
V
OS,PreAmp
1 +A
V
(3.46)
That is the residual oset voltage of the preamplier mentioned in Equa-
tion (3.42).
At this point, it is possible to have an overview of the whole analog
part of the SAR ADC and better understand how both sampling and oset
44
cancellation are performed. The simplied equivalent circuit of the previ-
ous designed circuits is shown in Figure 3.30 and the corresponding timing
diagram is represented in Figure 3.31.
Figure 3.30: Simplied equivalent circuit of the analog part of the ADC.
In Figure 3.30 the preamplier stages are represented as PreA 1-2. Ini-
tially, the input signal is applied to the bottom-plate nodes of the capacitive
array, the loop for the oset cancellation is closed and the output nodes
of each preamplier are shorted together using switches. In this way, each
stage of the preamplier is reset in a short period of time. After turning
o the ShortOutxS control signal, the loop can eectively perform the o-
set cancellation. Once the loop is open, also the path passing the input
signal can be disconnected and the common-mode voltage is connected to
the bottom-plate of each capacitor in the arrays. In order to correctly per-
form the bottom-plate sampling, the loop switches have to be open before
the switches connected to the input signal, whose charge injection is signal-
dependent. Therefore, any distortion eect is avoided on the sampled signal
at the input nodes of the comparator.
Figure 3.31: Sampling timing diagram example.
45
Using the resistive common-mode feedback for the second stage, the top-
plate nodes of the MSB capacitor arrays are correctly reset during the oset
cancellation phase by the closed-loop operation, without the need of other
switches. The reset voltage value V
RES
for these nodes is approximately
1.70 V while the top-plate nodes of the LSB sub-array are reset to V
CM
using two minimum-sized switches. After the signal has been sampled on
the input nodes of the preamplier, the circuit can start the binary search
algorithm.
Design, Analysis and Simulation
The optimization of the preamplier stage requires a thorough study of the
most relevant parameters in order to meet all the requirements. An analyti-
cal analysis has been rst conducted and the performances are checked with
Cadence simulations.
Considering rst the power-speed trade-o, a tail current I
Tail
of 10 A
is reserved for each stage. The power consumption of the preamplier is
therefore estimated as follows:
P
PreAmp
2V
DD
I
Tail
= 66 W (3.47)
Considering also the bias current, an overall power consumption of 75 W
can be expected, which is less than the value reserved during the denition
of the requirements.
The dierential voltage gain A
V
of the preamplier is dened as the
product of the dierential voltage gains of the rst and second stage, A
V 1
and A
V 2
respectively:
A
V
= A
V 1
A
V 2
(3.48)
where the dierential gain of each preamplier stage is approximately the
following:
A
V 1
=
g
m1
g
m3
+g
ds1

g
m1
g
m3
(3.49)
A
V 2
=
g
m7
g
ds9
+
1
R
+g
ds7
g
m7
R (3.50)
where g
m
is the transconductance and g
ds
the output conductance of the
transistors. The input transistors of both stages are operated in moderate
inversion to improve the values of the respective transconductances while all
the other transistors are operated in strong inversion.
Since the input capacitance of the latch is approximately 4 fF, the circuit
has been simulated in Cadence considering a generic capacitive output load
C
L
of 20 fF to have some margin. The results obtained are summarized in
Table 3.5 while the magnitude and phase diagrams of the open-loop transfer
function is shown in Figure 3.32.
46
Parameter Value
A
V
30.57 dB
f
3 dB
33.54 MHz
GBWP 1.13 GHz
Power 72.60 W
Table 3.5: Preamplier specications.
Figure 3.32: Magnitude and phase diagrams of the open-loop preamplier transfer
function.
The speed of the preamplier is another important requirement to be
considered during the design. Considering that a bit decision has to be taken
approximately every 65 ns, the input signal should be correctly preamplied
in a time interval t
PreAmp
less than 55 ns. Applying a step input voltage
equal to LSB
de
, which is the minimum input value to be discriminated,
the dierential output voltage reaches 129.4 mV after only 20 ns. Hence, the
input signal is suciently amplied in a short time interval since the output
reaches a value larger than the input-referred oset voltage of the latch.
Obviously, higher input values will achieve the requirements even faster. The
step responses of the dierential outputs for both the preamplier stages are
shown in Figure 3.33.
When the noise is considered, the rst stage of the preamplier is an-
alyzed since it is the major contributor. Both thermal and icker (1/f )
47
Figure 3.33: Step responses of the preamplier stages for a LSB
de
dierential
input. The blue trace represents the dierential output voltage of the rst stage,
while the red trace shows the dierential output voltage of the second stage.
input-referred voltage noises can be estimated respectively as follows:
e
2
Thermal,in
=
8k
B
T
g
m1
_
1 +
g
m3
g
m1
_
(3.51)
e
2
Flicker,in
=
2K
(1/f)
n
C
ox
W
1
L
1
1
f
+
2K
(1/f)
p
C
ox
W
3
L
3
1
f
_
g
m3
g
m1
_
2
(3.52)
where k
B
is the Boltzmann constant, T the temperature expressed in Kelvin,
K
(1/f)
a constant that depends on the technology, f the frequency, and a
coecient which is around
2
3
for long channel devices and can be larger for
deep sub-micron CMOS technologies. In order to evaluate the performance
of the circuit, the noise of the entire preamplier can be integrated over
its frequency bandwidth and referred back to the input. In this way, it
is possible to compare it with the 0.5LSB
de
reference value. The noise
bandwidth is the following:
BW
Noise
=

2
f
3 dB
= 52.68 MHz (3.53)
where f
3 dB
is the bandwidth of the preamplier stage. In order to have
some margin, a noise bandwidth BW
Noise
equal to 1 GHz has been consid-
ered during the simulation. The integrated input-referred RMS value of the
noise of the stage is:
[
Noise,in
]
1 GHz
1 Hz
=
[
Noise,out
]
1 GHz
1 Hz
A
V
= 138.33 V
RMS
(3.54)
48
where [
Noise,out
]
1 GHz
1 Hz
is the RMS value of the noise at the output nodes
of the stage integrated on the 1 GHz bandwidth. Therefore, it is possible
to estimate the input-referred noise and compare it with the 0.5LSB
de
reference value as follows:
V
Noise,PreAmp
3 [
Noise,in
]
1 GHz
1 Hz
= 415.00 V 0.5LSB
de
(3.55)
Since V
Noise,PreAmp
is much less than the 0.5LSB
de
reference value, the
stage has a good noise performance.
Statistic oset voltage can aect the performance of the preamplier and
hence of the entire ADC. The input-referred oset voltage of the rst stage
can be estimated as follows:
V
OS,PreAmp
= V
OS,1
+V
OS,3
g
m3
g
m1
(3.56)
where V
OS,1
and V
OS,3
are the variables representing the equivalent statistic
oset voltage values of M1, M2 and M3, M4 respectively. The variance of
these variables can be found as follows:

2
(V
OS
) =
2
(V
T
) +
2
_

__
I
D
g
m
_
2
(3.57)
where V
T
and represent the threshold voltage and current factor mis-
match respectively. Using Pelgrom coecients [24, 25]:
(V
T
) =
A
V T

WL
(3.58)

_
=
A

WL
(3.59)
From a 1000-runs Monte Carlo simulation, the input-referred oset voltage
V
OS,PreAmp
is estimated as follows:
V
OS,PreAmp

3(V
OUT
)
A
V
= 20.66 mV (3.60)
where V
OUT
is the dierence between the DC values of V
opA
and V
onA
.
Since the oset voltage of the preamplier stage is larger than LSB
de
, an
oset cancellation technique is required. The chosen input oset storage
technique returns the following residual input-referred oset voltage after
the cancellation:
V
OS,Residual
=
V
OS,PreAmp
1 +A
V
= 594.40 V (3.61)
Again, this residual voltage value can be compared to the 0.5LSB
de
reference value and note that the smallest dierential input signal can be
therefore estimated after the cancellation.
49
The oset cancellation is performed in an unity-gain negative-feedback
loop conguration during the sampling phase, hence, the stability of the
stage has to be checked. The preamplier reaches a phase margin PM of
78.40

during the closed-loop mode, providing a safe margin for the stability.
Due to the large equivalent capacitance at the input nodes of the comparator
provided by the capacitive array, the rst dominant pole of the loop gain
transfer function is shifted towards low frequencies, improving the stability
of the system. The magnitude and phase diagram of the loop gain are shown
in Figure 3.34.
Figure 3.34: Magnitude and phase diagrams of the loop gain transfer function.
3.5 SAR Control Logic
A control logic is required to control both the S/H and the DAC, to -
nally perform the binary search algorithm. Once the latch has made its
decision, the result is stored in the register and the DAC digital input is up-
dated according to the decision. During this closed-loop operation, timing
requirements have to be met and, again, low-power solutions are preferred.
3.5.1 Timing Diagrams
Since 16 ADCs are going to be implemented in the chip, a sampling fre-
quency f
s
of 1.28 MHz has been chosen during the elaboration of specica-
tions in Section 2.2. Therefore, each ADC has a conversion time t
conv
equal
50
to:
t
conv
=
1
f
s
781 ns (3.62)
One analog-to-digital conversion is carried out in 12 clock cycles as designed
in this work. While the rst cycle is reserved to reset the output voltage of
the comparator stages, the second one is used to sample the input signal.
The remaining 10 cycles are required for the 10-bit conversion. Therefore,
for each cycle the following time interval t
cycle
is needed:
t
cycle
=
t
conv
12
65 ns (3.63)
Hence, a master clock frequency f
clk
equal to 15.36 MHz is required. The
timing diagrams of the conversion are represented in Figure 3.35. All the
digital control signals are generated from the master clock signal ClkxC
and a second clock signal ClkdxC which is delayed by 3 ns with respect
to ClkxC. Note that the digital signal ClkdxC is mostly used to generate
the short pulses that trigger the latch and allows the circuit to perform the
bottom-plate sampling. Moreover, the digital signal ShortOutxS is high to
short the output nodes of each preamplier, LoopxS is the control signal
that closes the loop, SelInxS becomes high when the input signal is applied
to the capacitive array, D
IN
is the digital input of the DAC and LatxS is
the control signal for the latch. The signal DigOutxS represents the rst
9 bits of the output digital value while SignxS is the MSB (sign bit). It is
important to observe that D
IN
is equal to DigOutxS when its rst 8 bits
are determined (from cycle #4 to cycle #12) but it is reset at the beginning
of the new conversion. The value of the last bit of DigOutxS is instead
assigned at this time, therefore the 10-bit output digital value is ready to be
saved in a register during cycle #2, when the end-of-conversion signal EocxS
is high. During the rst cycle the preamplier stages are reset, as indicated
from the digital control signal ShortOutxS that is set to 1. The input
signal is eectively sampled on the bottom-plate nodes of the capacitors in
the second cycle since LoopxS and SelInxS are both high. At this time the
preamplier is operating in closed-loop, hence also the oset cancellation is
performed. LoopxS is set to 0 before the ending of the cycle in order to
realize the bottom-plate sampling. At the third cycle, all the bottom-plate
nodes of the capacitors are connected to the common voltage (D
IN
equal
to 0) and the sampled charge is redistributed on the input nodes of the
comparator. The rst comparison can be therefore executed and the MSB
is determined at the beginning of the fourth cycle when the latch is triggered.
The timing diagrams of the rst three cycles are shown in Figure 3.36.
At the beginning of the cycle #4 the reference voltages (V
REFP
and V
REFN
)
are assigned to the corresponding capacitor arrays depending on the result of
the last comparison and the DAC input signal is set to its half-range value.
Hence, the cycles from #4 to #12 are used to determine the remaining 9
51
Figure 3.35: Timing diagrams of the SAR control logic.
52
Figure 3.36: Timing diagrams for the rst three cycles of a conversion.
bits with the binary search algorithm. In particular, at the beginning of
each cycle, each DAC provides a new voltage value based on the previous
bit-decision, while the preamplier amplies the dierence between its input
nodes and the latch makes a decision once it is triggered (when the LatxS
signal goes high). On the new cycle, the digital input D
IN
of the DAC will
be eventually updated depending on the previous comparison result and
a new voltage value will be provided. A part from the fourth cycle, the
remaining cycles are clearly all equal, as shown in Figure 3.37 where cycles
#4, #5 and #6 are illustrated.
3.5.2 SAR Control Logic Implementation
The digital part of this ADC has been implemented as a successive approx-
imation register (SAR) whose simplied structure is shown in Figure 3.38.
Two rows of ip-ops are used to generate the digital input signal D
IN
for
the DAC: the rst row is a shift register that shifts a logical 1 while each
ip-op of the second row is rst set to logical 1 and then is eventually reset
53
Figure 3.37: Timing diagrams of the cycles used to determine the last 9 bits of the
digital output.
to logical 0, depending on the result of the comparison given by the signal
CompxS. The solution presented is quite popular in SAR ADCs [26, 27]
and it based on the design proposed in [28]. Considering the entire chip that
will host the 16 SAR ADCs, the shift register can be shared among them in
order to reduce both overall area and power consumption.
3.5.3 Delay Elements
A second clock signal delayed by 3 ns is required by the SAR control logic
and it is generated using a chain of inverters accurately sized. In order
to increase the delay, as shown in Figure 3.39, the chain consists of two
inverters using transistors with larger length L equal to 4.2 m and two
minimum-sized inverters added both to the input and the output of the
chain. This design choice allows to have larger output resistance for the
sized inverters, increasing the time delay while minimizing the capacitive
load for the driving circuit. The rst two minimum-sized inverters are used
to drive the structure while the last two one allow the circuit to achieve
54
Figure 3.38: Successive approximation register for binary search.
shorter rise and fall time. A generic output load C
L
of 10 fF has been used
to evaluate the time delay t
D
, the 10%-to-90% rise time t
R
, the 90%-to-10%
fall time t
F
and the dynamic power consumption. Simulating the circuit,
the values obtained are the following: a delay time t
D
of 3.446 ns is achived,
rise time and fall time are respectively equal to 248 ps and 186 ps, while the
power consumption is equal to 21.043 W. Nevertheless, this block can be
shared among all the ADCs present on chip.
Figure 3.39: Chain of inverters to generate the delayed clock signal.
3.6 Layout
The layout of the entire SAR ADC is shown in Figure 3.40. The dimen-
sions of this block are 395 391 m
2
, leading to an overall area A
ADC
of
154

445 m
2
. The oorplan is illustrated in Figure 3.41 where the dierent
parts have been highlighted. These parts are the two capacitive arrays and
their relative switches, the comparator and the digital part required for each
ADC. As expected, the capacitive array occupies the largest amount of area
among all blocks. The layout has been conducted while in a way to make
55
Figure 3.40: Floorplan of the SAR ADC.
a compact structure. However, the analog part has been placed at a safety
distance of approximately 100 m from the digital circuits to reduce the
coupling noise coming through the substrate [29].
Some of the digital part of the ADC is shared among all the ADCs on chip
(Section 3.5) and its layout is shown in Figure 3.42. The dimensions of this
part are 142 87 m
2
, for an area A
DigShared
of 12

354 m
2
.
Considering again the implementation of all the SAR ADCs on chip, at
this point it is possible to estimate the overall required area. One possible
oorplan for the MEA chip is to place 1024 read-out channels on two sides
of the chip, i. e., 512 channels are reserved for each side. Thus, the 16 SAR
ADCs can also be split in two groups while adding the digital shared logic
to each of them. The oorplan of the ADCs implemented on chip is shown
in Figure 3.43. Hence, the overall area required on chip can be estimated as
follows:
A
ADC,Chip
= 16A
ADC
+ 2A
DigShared
2.50mm
2
(3.64)
56
Figure 3.41: Analog and digital blocks composing the SAR ADC.
Figure 3.42: Layout of the shared digital logic among all the ADCs on chip.
Figure 3.43: Floorplan of the ADCs integrated on the MEA chip.
57
Chapter 4
Simulations and Conclusions
4.1 Simulation Results
In order to evaluate the performance of the designed circuit, the charac-
terization of the SAR ADC has to be conducted running dierent post-
layout simulations. First of all, an example of analog-to-digital conversion
is presented in Figure 4.1 where the reported voltage signals are measured
at the input nodes of the preamplier (V
ipA
and V
inA
). Both the sign-bit
SignxS and the remaining 9 bits DigOutxS composing the digital output
are shown as well. The conversion has been done for a constant analog input
value whose amplitude is equal to the dierential full-scale FS
de
. Hence,
the SAR ADC provides the highest value for the digital output. Note that
SignxS is equal to 1 if the dierential input voltage is positive, while the
remaining 9 bits are given by DigOutxS.
Dierential and integral linearity errors (DNL and INL respectively) can
be evaluated using the histogram test with a linear ramp input [4]. In this
kind of simulation consists a large number of digitized samples is collected
from the ADC for an input signal with known probability density function,
such as a linear ramp. From the simulation results, both DNL and INL
histogram plots can be derived and they are shown in Figures 4.2 and 4.3
respectively. Both DNL and INL errors are less than 0.5 LSB
de
for each
digital output. The resolution of the presented linearity analysis is equal to
0.05 LSB
de
.
A 2048-points FFT analysis is run to evaluate both the SNDR and
SFDR of the converter. The sampling frequency f
s
is set to 1.28 MS/s
while the frequency of the input sinusoidal wave is close to 10 KHz which is
the bandwidth BW
sig
of the neural signals. The output of the FFT analysis
is a power spectral density graph and is shown in Figure 4.4. The SFDR
measured is 76.51 dB while the SNDR reaches 60.74 dB that leads to an
ENOB of 9.79.
The power consumptions of both analog and digital parts of the ADC
58
Figure 4.1: Example of an analog-to-digital conversion performed by the SAR ADC.
Figure 4.2: DNL histogram plot of the SAR ADC.
are nally measured. Note, the digital control logic is divided into two parts:
one part is added to each converter (Digital) while the other one is shared
all the ADCs (Shared digital) present on chip, as explained in Section 3.6.
For this reason, in Table 4.1 the two dierent digital power consumptions
are distinguished.
For the MEA chip application, the overall power consumption of the ADCs
is therefore estimated as follows:
P
Tot
= 16(P
Analog
+P
Digital
) + 2P
SharedDigital
= 2.25 mW (4.1)
Altough the proposed data converter is not supposed to be general-purpose,
59
Figure 4.3: INL histogram plot of the SAR ADC.
Figure 4.4: 2048-points FFT output of the SAR ADC.
Part Power [W]
Analog 95.24
Digital 31.88
Shared digital 105.80
Table 4.1: Summary of the ADC power consumption.
its power eciency can be estimated with the following gure of merit:
FoM =
P
ADC
2
ENOB
f
S
(4.2)
60
where P
ADC
is the total power consumption of one ADC and, for the case
presented, is estimated as:
P
ADC
=
P
Tot
16
= 140.63 W (4.3)
That leads to a FoM of 125 fJ/conv-step. Note that this gure of merit is
calculated without considering the power consumptions of the multiplexers
and buers required by the system.
Table 4.2 summarizes and compare both the requirements and the es-
timated specications for the designed SAR ADC. In addition, the perfor-
mance of the proposed data-conversion system that can be integrated on
the MEA chip is shown in Table 4.3. These results are compared with the
specications of the single-slope ADCs currently integrated on the latest
version of the MEA chip.
Parameter Requirements Estimated values
Resolution 10 bits
Sampling Rate 1.28 MS/s
Supply Voltage 3.3 V
Full Scale Range 2.0 V
pp
(dierential)
DNL < 0.5 LSB + 0.35 / - 0.35 LSB
INL < 1 LSB + 0.35 / - 0.35 LSB
ENOB 9 bits 9.79 bits
SNDR 56 dB 60.74 dB
SFDR - 76.51 dB
Area 1 mm
2
0.157 mm
2
Power Consumption 1 mW 140.7 W
Technology 0.35 m CMOS
Table 4.2: Requirements and estimated performance of a single SAR ADC.
ADC Single-Slope SAR
Resolution 10 bits
ENOB 9.7 bits 9.79 bits
Area 7.04 mm
2
2.50 mm
2
Analog Power Consumption 6.19 mW 1.53 mW
Table 4.3: Specications of the single-slope data-conversion system currently im-
plemented on chip, compared to the performance of the SAR ADCs.
61
4.2 Conclusions
The presence of integrated analog-to-digital converters on chip is an essential
requirement for allowing a good signal transmission between the chip and
the external devices. After comparing the most relevant topologies for data
converters, the SAR ADC has been chosen since it is a promising solution
that could meet the required specications by multiplexing the read-out
channels on the MEA chip. Both low power consumption and low complexity
of the circuit are relevant advantages of the chosen ADC and key aspects to
succeed in the design.
Switched-capacitor arrays are used to implement both the S/H and DAC
while minimizing the value of the unit capacitor. The arrays are split in two
parts to reduce the overall equivalent capacitance which is equal to 6.05 pF
for a unit capacitor of only 64.36 fF. The capacitance provided by this part
can be used to store the oset voltage of the preamplier and cancel its
eect on the ADC performance. In fact, the residual input-referred oset
voltage of the amplier is 594.40 V after the cancellation, that is largely
less than the LSB value. While considering the timing requirements, the
sizes of the switches are optimized to reduce their area. In this work, the
switches occupy only 1.72 % of the total area of the ADC. A low-power
two-stage preamplier is designed to improve the eciency of the compar-
ison and drive the input nodes of the latch. In fact, the preamplier can
overcome the large oset voltage of the latch, that is estimated to be 40 mV
in the worst case. Moreover, the eect of the kickback noise caused by
the preamplier is reduced by using the capacitive neutralization technique,
leading to ENOB of 13.21 for the linearity quality of the sampling. The dig-
ital part is implemented adopting a successive approximation register whose
shift register is shared among all the ADCs present on chip, therefore saving
the 67.23 % of the digital power consumption.
The ADC occupies an area of 0.157 mm
2
and presents an overall power
consumption of 140.63 W for a sampling frequency of 1.28 MS/s. From
the post-layout simulation results, both DNL and INL errors are bounded
in a 0.35 LSB range. Concerning the linearity of the ADC, an ENOB of
9.79 is obtained. The power eciency is estimated with the FoM dened
in (4.2), that is equal to 125 fJ/conv-step. Finally, comparing this simulation
results with the specications of the single-slope ADCs currently integrated
on the latest version of the MEA chip, the proposed data-conversion system
presents an improvement of 64.49 % in terms of area reduction and its analog
power consumption is 4 times less.
In conclusion, the presented SAR ADC has proved to be a promising
solution for low-power applications. All the preliminary requirements have
been met and a good performance achieved. The specications of the data-
conversion system have been compared with the ADCs currently imple-
mented on the MEA chip and a possible improvement of its performances
62
has been presented. The designed circuit is therefore ready to be integrated
on chip for a nal characterization based on real measurements.
63
Chapter 5
Appendix
5.1 Eects of the parasitic capacitances in the DAC
The equivalent circuit of the switched-capacitor DAC is shown in Figure 5.1
where m and p are the sums of the unit capacitors connected in parallel
to the reference voltage in the LSB sub-array and MSB sub-array respec-
tively (Section 3.2). In addition, the parasitic capacitances aecting both
V
L
and V
M
nodes, C
p1
and C
p2
respectively, are added to the equivalent
circuit. While C
p1
is the bottom-plate parasitic capacitance of the series
capacitor C, C
p2
represents the gate capacitance of the input transistors of
the comparator.
Figure 5.1: Switched-capacitor DAC equivalent circuit.
Considering rst the ideal case where no parasitic capacitances are present
in the circuit (C
p1
= 0 and C
p2
= 0) and assuming that all the capacitors
are discharged before applying the digital input signal, the equations given
64
by the charge conservation principle are the following:
0 = mC(V
L
V
REFP
) + (15 m)C(V
L
V
CM
) +C(V
L
V
M
)
0 = pC(V
M
V
REFP
) + (31 p)C(V
M
V
CM
) +C(V
M
V
L
)
Solving the previous system of equations, the output voltage V
M
of the DAC
is:
V
M
= V
CM
+ (V
REFP
V
CM
)
m+ 16p
511
(5.1)
If the parasitic capacitances are taken into account, the previous system of
equations is modied as follows:
C
p1
(V
CM
V
DD
) = mC(V
L
V
REFP
) + (15 m)C(V
L
V
CM
) +
+C(V
L
V
M
) +C
p1
(V
L
V
DD
)
C
p2
(V
CM
V
DD
) = pC(V
M
V
REFP
) + (31 p)C(V
M
V
CM
) +
+C(V
M
V
L
) +C
p2
(V
M
V
DD
)
that results in the following output voltage V
M
for the DAC:
V
M
= V
CM
+ (V
REFP
V
CM
)
m+ 16p +pC
p1
511 + 32C
p1
+ 16C
p2
+C
p1
C
p2
(5.2)
It is therefore possible to study the inuence of the parasitic capacitances
on the DAC by comparing (5.2) with (5.1). In fact, while both parasitic
capacitances are introducing a gain error, only C
p1
is causing a distortion
on the DAC, hence limiting its linearity. Finally, note that, since the gate
capacitance C
p2
is usually larger than C
p1
, the gain error is mostly given by
the gate capacitance of the comparators input transistors.
5.2 Standard deviation estimation of the DAC out-
put voltage
Considering a simple 3-bit binary-weighted switched-capacitor DAC, the
analytical estimation of the standard deviation for its output voltage is pre-
sented in this section. The capacitive array and the equivalent circuit are
shown in Figure 5.2. The output voltage of the 3-bit DAC for the half-range
digital input code (D
IN
= 4 = 100) presents the worst case in terms of
mismatch among the capacitors [11], hence the constriction on the standard
deviation of this voltage should satisfy the following condition:
3(V
M,D
IN
=4
) 0.5LSB (5.3)
65
Figure 5.2: 3-bit switched-capacitor DAC and its equivalent circuit.
Dening C
eq
=C+C+2C, the output voltage value for the half-range digital
input code is the following:
V
M,D
IN
=4
= V
CM
+ (V
REFP
V
CM
)
4C
4C +C
eq
= 2.15 V (5.4)
Considering the capacitances as independent random variables, the mean
value of V
M,D
IN
=4
is:
(V
M,D
IN
=4
) = 2.15 V (5.5)
On the other hand, the calculation of the standard deviation (V
M,D
IN
=4
)
requires more steps. Calculating rst both the mean value and the variance
of the equivalent capacitance C
eq
:
(C
eq
) = (C) +(C) +(2C) = 4(C)

2
(C
eq
) =
2
(C) +
2
(C) +
2
(2C) = 4
2
(C)
Adding the value of the MSB capacitance 4C:
(4C +C
eq
) = (4C) +(C
eq
) = 8(C)

2
(4C +C
eq
) =
2
(4C) +
2
(C
eq
) = 8
2
(C)
Hence, the variance of the capacitive-divider ratio is:

2
_
4C
4C +C
eq
_
=
_
(4C)
(4C +C
eq
)
_
2
_

2
(4C)

2
(4C)
+

2
(4C +C
eq
)

2
(4C +C
eq
)
_
2
=
3
2
(C)
32
2
(C)
The variance of V
M,D
IN
=4
is therefore found as follows:

2
(V
M,D
IN
=4
) =
2
_
V
CM
+ (V
REFP
V
CM
)
4C
4C +C
eq
_
=
= (V
REFP
V
CM
)
2
3
2
(C)
32
2
(C)
66
Writing (C) as
C
and (C) as
C
, the standard deviation of V
M,D
IN
=4
is
the following:
(V
M,D
IN
=4
) = (V
REFP
V
CM
)

6
C
8
C
(5.6)
Since both
C
and
C
depend on the area of the unit capacitor, by substi-
tuting the parametric expressions in (5.3), one can determine the minimum
unit capacitor area that satises the condition.
67
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