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Lecture04 Timing Basics 2up

This document summarizes a lecture on timing basics for integrated circuits. It discusses different clocking types including synchronous and asynchronous approaches. Source synchronous clocking is described where the clock and data paths are matched. Clock and data recovery (CDR) techniques are also covered, including using phase detectors and phase adjustment circuits to recover the clock from the data. CDR allows separate clocks to be used and relaxes timing constraints. The document provides examples of how CDR can enable communication between chips with slightly different clock frequencies in a plesiochronous system.

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tarungupta79
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94 views

Lecture04 Timing Basics 2up

This document summarizes a lecture on timing basics for integrated circuits. It discusses different clocking types including synchronous and asynchronous approaches. Source synchronous clocking is described where the clock and data paths are matched. Clock and data recovery (CDR) techniques are also covered, including using phase detectors and phase adjustment circuits to recover the clock from the data. CDR allows separate clocks to be used and relaxes timing constraints. The document provides examples of how CDR can enable communication between chips with slightly different clock frequencies in a plesiochronous system.

Uploaded by

tarungupta79
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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EE290C Spring 2011

Lecture 4: Timing Basics

Elad Alon Dept. of EECS

Why We Need to Talk About Timing

EE290C

Lecture 4

Clocking Types

Many different options All boil down to relationship between (or even existence of) clk1 and clk2

EE290C

Lecture 4

Clocking Types

*Poulton99
EE290C Lecture 4 4

Simple Synchronous System

Under what conditions will this work? EE141 answer:

EE290C

Lecture 4

What You Really Do

EE290C

Lecture 4

An Example

tp,data = 2ns, Tbit = ? What else do you need to know?

EE290C

Lecture 4

An Example

tp,data = 2ns, Tbit = ?

EE290C

Lecture 4

An Example

# of bits on the line

tp,data = 2ns, tsk+jitt = +/-50ps Get bands of 15 14 functionality: 13


12 11 10 9 8 7 6 100 150 200 250 T (ps)
bit

300

350

EE290C

Lecture 4

Source Synchronous Clocking

Key idea: match clock and data paths


Link ideally works from DC up to timing uncertaintylimited frequency

What is the right tdel?

EE290C

Lecture 4

10

Source Synchronous Clocking

Want one clock link for multiple data links


Reduce overhead

What if data lines dont match each other?


Or dont match clock line Or tdel isnt quite right (depends on Tbit, PVT, etc.)
EE290C Lecture 4 11

Realistic Source Synchronous System

tp,data,1 D1 D Q TX RX D Q DRX1

tdel1 tp,data,0 D0 D Q TX tp,data,c TX clk RX tdel0 RX D Q DRX0

EE290C

Lecture 4

12

In General: CDR
CDR = Clock and Data Recovery
Recover clock phase and/or frequency based on data itself If phase only, need a frequency reference

Several advantages vs. fixed timing


Dont have to match delays/paths (mesochronous) Allows separate crystals (plesiochronous)

But, CDR isnt free


And places some requirements on data

EE290C

Lecture 4

13

Conceptual CDR

EE290C

Lecture 4

14

Linear (Hogge) Phase Detector

EE290C

Lecture 4

15

Bang-Bang (Alexander) Phase Detector


Vin

dn
data Clk

en
edge Clk

Edge clock Tsym/2 away from data Derive early/late from data and edge samples:
Dn: (dn != en) & (dn-1 != dn) Up: (dn == en) & (dn-1 != dn)
EE290C Lecture 4 16

Phase Adjustment
Many possibilities
DLL vs. PLL VCO vs. VCDL Digital vs. analog Etc.

All boil down to adjusting delay, frequency, or both


More in a few weeks

EE290C

Lecture 4

17

CDR in Plesiochronous System


CHIP 1
Logic Serializer Tx Rx

CHIP 2
Deserializer FIFO Logic Elastic Buffer

f1

PLL

CDR

f2 10 bits @ f1 10 bits @ f2

10 bits @ f1

from other links

Transmit data @ f1 Recover clock and data @ f1 on RX Elastic buffer (FIFO) transfers data from f1 to f2
EE290C Lecture 4 18

Implications
CHIP 1
Logic Serializer Tx Rx

CHIP 2
Deserializer FIFO Logic Elastic Buffer

f1

PLL

CDR

f2 10 bits @ f1 10 bits @ f2

10 bits @ f1

from other links

FIFO must be deep enough


Set by max. freq. offset, data length

CDR must be able to track max. freq. offset


EE290C Lecture 4 19

Final Notes: Parallel vs. Serial Links

EE290C

Lecture 4

20

Final Notes: Clock Distribution

EE290C

Lecture 4

21

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