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CMOS Layout: Mask Layers

This document discusses the CMOS layout process and considerations for MOSFET layout. It includes: 1) An overview of the layout process including mask layers for devices, interconnects, and design rules. 2) Details on how to electrically connect active, polysilicon, and metal layers to form transistors and interconnects between devices. 3) An example layout showing transistors, interconnects, and connections between layers. 4) How circuit extraction is used to simulate a layout and calculate parasitic capacitances and resistances.

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chittajitsarkarster
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36 views

CMOS Layout: Mask Layers

This document discusses the CMOS layout process and considerations for MOSFET layout. It includes: 1) An overview of the layout process including mask layers for devices, interconnects, and design rules. 2) Details on how to electrically connect active, polysilicon, and metal layers to form transistors and interconnects between devices. 3) An example layout showing transistors, interconnects, and connections between layers. 4) How circuit extraction is used to simulate a layout and calculate parasitic capacitances and resistances.

Uploaded by

chittajitsarkarster
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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CMOS Layout
Mask Layers

IC design procedure: system specifications circuit design layout post-layout extraction and simulation IC fabrication testing select (p+) brown active green n-well purple Layer Representation Color Convention (EECS 105)

Layout considerations: mask layers devices electrical connectivity (interconnect) layout (design) rules contact black metal blue polysilicon red

EE 105 Fall 1998 Lecture 12

EE 105 Fall 1998 Lecture 12

MOSFET Layout
s s

Electrical Connectivity
active, polysilicon, and metal can be used for interconnects (wires)

polysilicon crossing active results in an NMOS device: L gate W


s s

metal has much lower resistivity than either active or polysilicon

metal is separated from active or polysilicon by an (insulating) oxide; a contact is needed for electrical connections between these layers

source / drain (symmetric)

PMOS devices are placed in n-wells:


s

active and polysilicon cannot be connected directly (without metal)

use p-doped active (select mask) as contact to the bulk use n-doped active (no select mask) as a contact to n-wells

select n-well contact to bulk contact to well

EE 105 Fall 1998 Lecture 12

EE 105 Fall 1998 Lecture 12

Layout Rules (EECS 105 Technology)


minimum dimensions and separations (in mm, not to scale):
n-well 4 5 active 2 2 select 2 2 1 2 contact 1 1 metal 2 polysilicon 1

Layout Example

VDD

VDD

polysilicon

active 1 2

contact-topoly 2

metal

polysilicon active 3 n-well 1 1

VSS 0 2 4 6 8 10 12 14 16

VSS 18 20 m

EE 105 Fall 1998 Lecture 12

EE 105 Fall 1998 Lecture 12

10 12

14 16

18 20 m

Circuit Extraction
1) Find all transistors and sizes 2) Extract wiring 3) Calculate (parasitic) capacitance and resistance VDD VDD

Circuit Extraction
1) Find all transistors and sizes 2) Extract wiring 3) Calculate (parasitic) capacitance and resistance VDD VDD

10 12 14 16 18 20 m

VSS 0 2 4 6 8

VSS 10 12 14 16 18 20 m

VSS 0 0 2 4 6 8

VSS 10 12 14 16 18 20 m

EE 105 Fall 1998 Lecture 12

0
EE 105 Fall 1998 Lecture 12

10 12 14 16 18 20 m

Extracted Schematic
s

Circuit Simulation
Objectives: fabricating an IC costs $1000 ... $100,000 per run

VDD
CA-DD (4.5/1) CB-DD (4.5/1)

---> nice to get it right the first time check results from hand-analysis (e.g. validity of assumptions) F Cw evaluate functionality, speed, accuracy, ... of large circuit blocks or entire chips

B
CB-SS

(3/1)
s

Simulators: SPICE: invented at UC Berkeley circa 1970-1975

A
CA-SS

(3/1)

commercial versions: HSPICE, PSPICE, I-SPICE, ... (same core as Berkeley SPICE, but add functionality, improved user interface, ...) EECS 105: student version of PSPICE on PC, limited to 10 transistors

VSS
s

other simulators for higher speed, special needs (e.g. SPLICE, RSIM)

Wire capacitance Cw is found from its capacitance per unit length - ox - W w L w C w = ---------t thox Interconnect capacitances CA-SS and CA-DD are the sum of polysilicon and metal capacitances to the substrate (connected to VSS ) or the well (connected to VDD) Could add resistances of polysilicon and metal interconnects

Limitations: simulation results provide no insight (e.g. how to increase speed of circuit) results sometimes wrong (errors in input, effect not modeled in SPICE) ===> always do hand-analysis first and COMPARE RESULTS

EE 105 Fall 1998 Lecture 12

EE 105 Fall 1998 Lecture 12

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