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An Example of A Hierarchical VHDL Project Under Altera Quartus II

The document describes a hierarchical VHDL project structure using multiple VHDL files. It contains a top-level module that uses lower-level modules that have already been designed and tested. It provides steps to compile the project and test each module using provided waveform files by changing the top-level module.

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anilshaw27
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54 views

An Example of A Hierarchical VHDL Project Under Altera Quartus II

The document describes a hierarchical VHDL project structure using multiple VHDL files. It contains a top-level module that uses lower-level modules that have already been designed and tested. It provides steps to compile the project and test each module using provided waveform files by changing the top-level module.

Uploaded by

anilshaw27
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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An Example of a Hierarchical VHDL Project Under Altera Quartus II

CAPT Charles B. Cameron January 8, 2009

Introduction

It is feasible under Quartus II to have multiple VHDL les, each one describing a dierent module, as well as multiple waveform les for testing each of them. Not only that, but a high-level module can make use of low-level modules that have already been designed, tested, and debugged. This document shows how to do this.

Getting the Example Files

On the EE361 web site, download the le AlteraFiles.zip from the web address http://www.usna.edu/EE/ee362/Labs/. Extract all of the constituent les into a new directory (or folder, if you prefer that term.) The les are listed in Table 1 on the following page.

Creating and Using a Project

The following steps from within Altera Quartus II will allow you to compile each of the les you have downloaded and test them. 1. Create a new project: File | New Project Wizard. For the working directory, designate the directory where you stored the downloaded les from AlteraFiles.zip. You can choose any project name you like, Register, for example. You will see that the top-level entity for the project will be assumed to be the same, but you do not have to accept that. In this case, designate module myd as the top-level module. Later, well change this more than once as we test the higher level modules. When you are asked to select the design les you want to include in the project, specify all seven of them: the four VHDL source les and the three waveform les. Specify the FLEX10K family of devices. The larger of the two devices on the Altera UP-2 board is the EPF10K70RC240-4. 1

File Name dreg n.vhd

Description This le contains the top-level module in this example. The module is called dreg n. It generates a 16-bit register. To do this it uses the dreg.vhd module, passing it the paramter 16 to specify the number of bits in the register. This module oers an N-bit register driven by a clock. The value of N is passed to it via a generic parameter. This module uses one instance of myd.vhd for each bit int the register. This module denes a clocked D ip-op. The design makes use of a VHDL PROCESS statement. An asynchronous reset signal is one of its inputs. A package is useful for holding the VHDL COMPONENT declarations for low-level modules used by a high-level module. This package contains component declarations for myd A le of waveform inputs for the dreg n module. The inputs include the reset and clock one-bit signals and a few of the 216 possible 16-bit signals d. A le of waveform inputs for the dreg module. The inputs include the reset and clock one-bit signals and an exhaustive set of the 16 possible 4-bit signals d. A le of waveform inputs for the myd module. The inputs include the reset, clock, and several dierent d one-bit signals. Table 1: Contents of the le AlteraFiles.zip.

dreg.vhd

myd.vhd

cameronpkg.vhd

dreg n.vwf

dreg.vwf

myd.vwf

     

   

    

!   

 " # 

 $ # 

Figure 1: Output of the simulation of module myd using the test waveform myd.vwf . We will not be using any external tools (so-called EDA tools.) When you select the Finish button, all seven les will appear in a list near the left side of your screen on the Files tab under the heading Project Navigator. Select the tab Hierarchy and you should see the top-level le. If you followed the directions earlier, this will be the module myd. 2. Compile the project: Processing | Start Compilation. This will cause the top-level module to be analyzed, synthesized, and tted to the target device (the EPF10K70Rc240-4). This step can take several minutes. You can look at the VHDL source code for myd while you are waiting by rightclicking on the entity name (myd ) in the Hierarchy tab and selecting Locate | Locate in Design File. You can do it even more simply by just double-clicking the entity name. 3. Test the project: Processing | Start Simulation. The results of the simulation show how the value of signal d is reected on q and how its complement is reected on qn shortly after each rising edge of clock, provided that the device is not still in its reset mode. 4. Test another module in the project, dreg. To do this, right-click the Files tab in the Project Navigator window and select Set as Top-Level Entity. You will need to recompile. To select the correct waveform input for testing this module, select Assignments | Settings. Then select the heading Simulator Settings. In the Simulation Input window enter the name of the le that contains the correct waveform specication, dreg.vwf . Once you have done this you can run another simultation
ff

5. Test the nal module in the project, dreg n.

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