Scalar Types Scalar types describe objects that can hold, at most, one value at a time.

The type itself can contain multiple values, but an object that is declared to be a scalar type can hold, at most, one of the scalar values at any point in time. Referencing the name of the object references the entire object. Scalar types encompass these four classes of types: Integer types Real types Enumerated types Physical types

Physical Types
Objects which are declared to be of Physical type, carry a value as well as a unit. These are used to represent physical quantities such as time, resistance and capacitance. The Physical type defines a basic unit for the quantity and may define other units which are multiples of this unit. Time is the only Physical type, which is pre-defined in the language. The user may define other Physical types. Pre-defined Physical Type: Time

Type time is range 0 to . . . units fs; --femtosecond ps = 1000 fs; --picosecond ns = 1000 ps; --nanosecond us = 1000 ns; --microsecond ms = 1000 us; --millisecond sec = 1000 ms; --second min = 60 sec; --minute hr = 60 min; --hour end units time; The user may define other physical types as required. User Defined Physical Types As an example of user defined Physical types, we can define the resistance type. Type resistance is range 0 to 1E9 units ohm; kohm = 1000 ohm; Mohm = 1000 kohm; end units resistance; INTEGER TYPES Minimum range for any implementation as defined by standard: 2,147,483,647 to +2,147,483,647 Example assignments to a variable of type integer: ARCHITECTURE test OF test IS BEGIN PROCESS(X) VARIABLE a : INTEGER; VARIABLE b : int_type; BEGIN a := 1; --Ok 1 a := -1; --Ok 2

a := 1.0; --error 3 END PROCESS; END test; Scalar objects can hold only one data value at a time. A simple example is the integer data type. Variables and signals of type integer can only be assigned integers within a simulator-specific range, although the VHDL standard imposes a minimum range. In the above example, the first two variable assignments are valid since they assign integers to variables of type integer. The last variable assignment is illegal because it attempts to assign a real number value to a variable of type integer. REAL TYPES The minimum range of real numbers is also specified by the Standard package in the Standard Library, and is from 1.0E38 to 1.0E38. These numbersare represented by the following notation +or -number.number[E or -number] Example assignments to a variable of type integer: ARCHITECTURE test OF test IS SIGNAL a : REAL; BEGIN a <= 1.0; --Ok 1 a <= 1; --error 2 a <= -1.0E10; --Ok 3 a <= 1.5E-20; --Ok 4 a <= 5.3 ns; --error 5 END test; A second simple example is the real data type. This type consists of the real numbers within a simulator-specific (but with a VHDL standard imposed minimum) range. The variable assignment lines marked OK are valid assignments. The first illegal statement above attempts to assign an integer to a real type variable, and the second illegal statement is not allowed since the unit ns denotes a physical data type.

ENUMERATED TYPES An enumerated type is a very powerful tool for abstract modeling. A designer can use an enumerated type to represent exactly the values required for a specific operation. All of the values of an enumerated type are user-defined. An enumeration type is defined by listing (enumerating) all possible values of that type. The syntax of an enumeration type definition is type type_name is (enumeration_literal {,enumeration_literal} ); type_name is an identifier, and each enumeration_literal is either an identifier(enum_6) or acharacter literal (A). An identifier is a sequence of letters, underscores, and numbers. An identifier must start with a letter and cannot be aVHDL reserved word, such as TYPE A character literal is any value of type CHARACTER, in single quotes. User specifies a list of possible values Example declaration and usage of enumerated data types:

The enumerated data type allows a user to specify the list of legal values that a variable or signal of the defined type may be assigned. As an example, this data type is useful for defining the various states of a FSM with descriptive names. The designer first declares the members of the enumerated type. In the example above, the designer declares a new type binary with two legal values, ON and OFF. Note that VHDL is not case sensitive. Typing reserved words in capitals and variables in lower case may enhance readability, however. Array Types An array is an object that is a collection of elements of thesame type. VHDL supports N-dimensional arrays, but VHDLCompiler supports only onedimensional arrays. Array elements can be of any type. An array has an index whose value selects each element. The index range determines how many elements are in the array and their ordering (low to high, or high downto low). An index can be of any integer type. You can declare multidimensional arrays by building one-dimensional arrays where the element type is another one-dimensional array, as shown in Example 46. Example 46 Declaration of Array of Arrays type BYTE is array (7 downto 0) of BIT; type VECTOR is array (3 downto 0) of BYTE; VHDL provides both constrained arrays and unconstrained arrays. The difference between these two comes from the index range in the array type definition. Constrained Array A constrained arrays index range is explicitly defined; for example, the integer range (1 to 4) . When you declare a variable or signal of this type, it has the same index range. The syntax of a constrained array type definition is

type array_type_name is array ( integer_range )of type_name; array_type_name is the name of the new constrained array type, integer_range is a subrange of another integer type, and type_name is the type of each array element Example 47 Constrained Array Type Definition type BYTE is array (7 downto 0) of BIT; A constrained array whose index range is (7, 6, 5, 4, 3, 2, 1, 0) Unconstrained Array You define an unconstrained arrays index range as a type;for example, INTEGER. This definition implies that the index range can be any contiguous subset of that types values. When you declare an array variable or signal of this type, you also define its actual index range. Different declarations can have different index ranges. The syntax of an unconstrained array type definition is type array_type_name is array ( range_type_name range <>) of element_type_name ; array_type_name is the name of the new unconstrained array type, range_type_name is the name of an integer type or subtype, and element_type_name is the type of each array element. Example 48 shows an unconstrained array type definition and a declaration that uses it. Example 48 Unconstrained Array Type Definition type BIT_VECTOR is array(INTEGER range <>) of BIT; An unconstrained array definition ... variable MY_VECTOR : BIT_VECTOR(5 downto 5);

The advantage of using unconstrained arrays is that a VHDL tool remembers the index range of each declaration. You can use array attributes to determine the range (bounds) of a signal or variable of an unconstrained array type. With this information, you can write routines that use variables or signals of an unconstrained array type, independently of any one array variables or signals bounds. RECORD TYPES Record types group objects of many types together as a single object. Each element of the record can be accessed by its field name. Record elements can include elements of any type, including arrays and records. The elements of a record can be of the same type or different types. Like arrays, records are used to model abstract data elements. Records are used to group elements of possibly different types into a single VHDL object. Elements are indexed via field names Example of record declaration and usage:

The second VHDL composite type is the record. An object of type record may contain elements of different types. Again, a record element may be of any data type, including another record. A TYPE declaration is used to define a record. Note that the types of a record's elements must be defined before the record is defined. Also notice that there is no semi-colon after the word RECORD. The RECORD and END RECORD keywords bracket the field names. After the RECORD keyword, the record's field names are assigned and their data types are specified.

In the above example, a record type, switch_info, is declared. This example makes use of the binary enumerated type declared previously. Note that values are assigned to record elements by use of the field names Following is an example of a record type declaration: TYPE optype IS ( add, sub, mpy, div, jmp ); TYPE instruction IS RECORD opcode : optype; src : INTEGER; dst : INTEGER; END RECORD; The first line declares the enumerated type optype, which is used as one of the record field types. The second line starts the declaration of the record. The record type declaration begins with the keyword RECORD and ends with the clause END RECORD. All of the declarations between these two keywords are field declarations for the record. Each field of the record represents a unique storage area that can be read from and assigned data of the appropriate type. This example declares three fields: opcode of type optype, and src and dst of type INTEGER. Each field can be referenced by using the name of the record, followed by a period and the field name. Following is an example of this type of access: PROCESS(X) VARIABLE inst : instruction; VARIABLE source, dest : INTEGER; VARIABLE operator : optype; BEGIN source := inst.src; --Ok line 1 dest := inst.src; --Ok line 2 source := inst.opcode; --error line 3 operator := inst.opcode; --Ok line 4 inst.src := dest; --Ok line 5 inst.dst := dest; --Ok line 6 inst := (add, dest, 2); --Ok line 7 inst := (source); --error line 8

END PROCESS; This example declares variable inst, which is of type instruction. Also, variables matching the record field types are declared. Lines 1 and 2 show fields of the record being assigned to local process variables. The assignments are legal because the types match. Notice the period after the name of the record to select the field. Line 3 shows an illegal case. The type of field opcode does not match the type of variable source. The compiler will flag this statement as a type mismatch error. Line 4 shows the correct assignment occurring between the field opcode and a variable that matches its type. Lines 5 and 6 show that not only can record fields be read from, but they can be assigned to as well. In these two lines, two of the fields of the record are assigned the values from variable dest. Line 7 shows an example of an aggregate assignment. In this line, all of the fields of the record are being assigned at once. The aggregate assigned contains three entries: an optype value, an INTEGER variable value, and an INTEGER value. This is a legal assignment to variable record inst. Line 8 shows an example of an illegal aggregate value for record inst. There is only one value present in the aggregate, which is an illegal type for the record