Chapter-5 Memory Hierarchy Design

Unlimited amount of fast memory - Economical solution is memory hierarchy - Locality - Cost performance Principle of locality - most programs do not access all code or data uniformly. Locality occurs - Time (Temporal locality) - Space (spatial locality) Guidelines Smaller hardware can be made faster Different speed and sizes

Goal is provide a memory system with cost per byte than the next lower level Each level maps addresses from a slower, larger memory to a smaller but faster memory higher in the hierarchy.

Address mapping Address checking. Hence protection scheme for address for scrutinizing addresses are also part of the memory hierarchy.

Memory Hierarchy

Levels of the Memory Hierarchy

Capacity Access Time CPU Registers 500 bytes 0.25 ns Cache 64 KB 1 ns

Upper Faste

Register

Cach Block

Capacit

Spee

Main Memory 512 MB 100ns Disk 100 GB 5 ms

Memor Page I/O File ??? Large Lower

Why More on Memory Hierarchy?

100,000 10,000 Performance 1,000 100 10 1 1980 1985 1990 1995 Year 2000 2005 2010 Memory

Processor

The importance of memory hierarchy has increased with advances in performance of processors.

Prototype When a word is not found in cache Fetched from memory and placed in cache with the address tag. Multiple words( block) is fetched for moved for efficiency reasons.

key design Set associative Set is a group of block in the cache. Block is first mapped on to set. Find mapping Searching the set

Chosen by the address of the data: (Block address) MOD(Number of sets in cache) n-block in a set Cache data - Cache read. - Cache write. Write through: update cache and writes through to update memory. Both strategies - Use write buffer. this allows the cache to proceed as soon as the data is placed in the buffer rather than wait the full latency to write the data into memory. Metric used to measure the benefits is miss rate No of access that miss No of accesses Write back: updates the copy in the cache. Cache replacement is called n-way set associative.

Causes of high miss rates Three Cs model sorts all misses into three categories Compulsory: every first access cannot be in cache Compulsory misses are those that occur if there is an infinite cache Capacity: cache cannot contain all that blocks that are needed for the program. As blocks are being discarded and later retrieved.

Conflict: block placement strategy is not fully associative Block miss if blocks map to its set.

Miss rate can be a misleading measure for several reasons So, misses per instruction can be used per memory reference Misses Instruction = Miss rate X Memory accesses Instruction count

Miss rate X Mem accesses Instruction

Cache Optimizations
Six basic cache optimizations 1. Larger block size to reduce miss rate: - To reduce miss rate through spatial locality. Increase block size. Larger block size reduce compulsory misses. But they increase the miss penalty.

2. Bigger caches to reduce miss rate:

- capacity misses can be reduced by increasing the cache capacity.

- Increases larger hit time for larger cache memory and higher cost and power.

3. Higher associativity to reduce miss rate: - Increase in associativity reduces conflict misses. 4. Multilevel caches to reduce penalty: - Introduces additional level cache - Between original cache and memory. - L1- original cache L2- added cache. L1 cache: - small enough - speed matches with clock cycle time. L2 cache: - large enough - capture many access that would go to main memory.

Average access time can be redefined as Hit timeL1+ Miss rate L1 X ( Hit time L2 + Miss rate L2 X Miss penalty L2) 5. Giving priority to read misses over writes to reduce miss penalty: - write buffer is a good place to implement this optimization. - write buffer creates hazards: read after write hazard. 6. Avoiding address translation during indexing of the cache to reduce hit time: - Caches must cope with the translation of a virtual address from the processor to a physical address to access memory. - common optimization is to use the page offset. - part that is identical in both virtual and physical addresses- to index the cache.

Advanced Cache Optimizations

Reducing hit time Small and simple caches Way prediction Trace caches

Increasing cache bandwidth Pipelined caches Multibanked caches Nonblocking caches

Reducing Miss Penalty Critical word first Merging write buffers

Reducing Miss Rate Compiler optimizations

Reducing miss penalty or miss rate via parallelism Hardware prefetching Compiler prefetching

First Optimization : Small and Simple Caches Index tag memory and then compare takes time Small cache can help hit time since smaller memory takes less time to index E.g., L1 caches same size for 3 generations of AMD microprocessors: K6, Athlon, and Opteron Also L2 cache small enough to fit on chip with the processor avoids time penalty of going off chip Simple direct mapping Can overlap tag check with data transmission since no choice

Access time estimate for 90 nm using CACTI model 4.0 Median ratios of access time relative to the direct-mapped caches are 1.32, 1.39, and 1.43 for 2-way, 4-way, and 8-way caches

2.50 Access time (ns) 2.00 1.50 1.00 0.50 16 KB 32 KB 64 KB 128 KB Cache size 256 KB 512 KB 1 MB 1-way 2-way 4-way 8-way

Second Optimization: Way Prediction

How to combine fast hit time of Direct Mapped and have the lower conflict misses of 2-way SA cache? Way prediction: keep extra bits in cache to predict the way, or block within the set, of next cache access.

Hit Time Way-Miss Hit Time

Miss Penalty

Multiplexer is set early to select desired block, only 1 tag comparison performed that clock cycle in parallel with reading the cache data

Miss 1st check other blocks for matches in next clock cycle

Accuracy 85% Drawback: CPU pipeline is hard if hit takes 1 or 2 cycles Used for instruction caches vs. data caches

Third optimization: Trace Cache

Find more instruction level parallelism? How to avoid translation from x86 to microops? Trace cache in Pentium 4

1. Dynamic traces of the executed instructions vs. static sequences of instructions as determined by layout in memory Built-in branch predictor

2. Cache the micro-ops vs. x86 instructions + Decode/translate from x86 to micro-ops on trace cache miss

1. better utilize long blocks (dont exit in middle of block, dont enter at label

in middle of block) 1. complicated address mapping since addresses no longer aligned to powerof-2 multiples of word size 1. instructions may appear multiple times in multiple dynamic traces due to

different branch outcomes Fourth optimization: pipelined cache access to increase bandwidth Pipeline cache access to maintain bandwidth, but higher latency Instruction cache access pipeline stages: 1: Pentium 2: Pentium Pro through Pentium III 4: Pentium 4 greater penalty on mispredicted branches more clock cycles between the issue of the load and the use of the data

Fifth optimization: Increasing Cache Bandwidth Non-Blocking Caches

Non-blocking cache or lockup-free cache allow data cache to continue to supply cache hits during a miss requires F/E bits on registers or out-of-order execution requires multi-bank memories

hit under miss reduces the effective miss penalty by working during miss vs. ignoring CPU requests

hit under multiple miss or miss under miss may further lower the effective miss penalty by overlapping multiple misses Significantly increases the complexity of the cache controller as there can be multiple outstanding memory accesses Requires multiple memory banks (otherwise cannot support) Pentium Pro allows 4 outstanding memory misses

Value of Hit Under Miss for SPEC

Hit Under i Misses

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Floating Point

FP programs on average: AMAT= 0.68 -> 0.52 -> 0.34 -> 0.26

Int programs on average: AMAT= 0.24 -> 0.20 -> 0.19 -> 0.19 8 KB Data Cache, Direct Mapped, 32B block, 16 cycle miss, SPEC 92

Sixth optimization: Increasing Cache Bandwidth via Multiple Banks

Rather than treat the cache as a single monolithic block, divide into independent banks that can support simultaneous accesses E.g.,T1 (Niagara) L2 has 4 banks

Banking works best when accesses naturally spread themselves across banks mapping of addresses to banks affects behavior of memory system

Simple mapping that works well is sequential interleaving Spread block addresses sequentially across banks E,g, if there 4 banks, Bank 0 has all blocks whose address modulo 4 is 0; bank 1 has all blocks whose address modulo 4 is 1;

Seventh optimization :Reduce Miss Penalty: Early Restart and Critical Word First
Dont wait for full block before restarting CPU Early restartAs soon as the requested word of the block arrives, send it to the CPU and let the CPU continue execution Spatial locality tend to want next sequential word, so not clear size of benefit of just early restart Critical Word FirstRequest the missed word first from memory and send it to the CPU as soon as it arrives; let the CPU continue execution while filling the rest of the words in the block Long blocks more popular today Critical Word 1st Widely used

block
Eight optimization: Merging Write Buffer to Reduce Miss Penalty Write buffer to allow processor to continue while waiting to write to memory If buffer contains modified blocks, the addresses can be checked to see if address of new data matches the address of a valid write buffer entry If so, new data are combined with that entry Increases block size of write for write-through cache of writes to sequential words, bytes since multiword writes more efficient to memory The Sun T1 (Niagara) processor, among many others, uses write merging

Ninth optimization: Reducing Misses by Compiler Optimizations

McFarling [1989] reduced caches misses by 75% on 8KB direct mapped cache, 4 byte blocks in software Instructions Data Merging Arrays: improve spatial locality by single array of compound elements vs. 2 arrays Loop Interchange: change nesting of loops to access data in order stored in memory Loop Fusion: Combine 2 independent loops that have same looping and some variables overlap Reorder procedures in memory so as to reduce conflict misses Profiling to look at conflicts (using tools they developed)

Blocking: Improve temporal locality by accessing blocks of data repeatedly vs. going down whole columns or rows

Merging Arrays Example /* Before: 2 sequential arrays */ int val[SIZE]; int key[SIZE];

/* After: 1 array of stuctures */ struct merge { int val; int key; }; struct merge merged_array[SIZE]; Reducing conflicts between val & key; improve spatial locality

0.1

0.05

Direct Mapped Cache

Fully Associative Cache 0 0 50 Blocking Factor 100 150

Conflict misses in caches not FA vs. Blocking size Lam et al [1991] a blocking factor of 24 had a fifth the misses vs. 48 despite both fit in cache

Tenth optimization Reducing Misses by Hardware Prefetching of Instructions & Data

Prefetching relies on having extra memory bandwidth that can be used without penalty Instruction Prefetching Typically, CPU fetches 2 blocks on a miss: the requested block and the next consecutive block. Requested block is placed in instruction cache when it returns, and prefetched block is placed into instruction stream buffer Data Prefetching Pentium 4 can prefetch data into L2 cache from up to 8 streams from 8 different 4 KB pages Prefetching invoked if 2 successive L2 cache misses to a page, if distance between those cache blocks is < 256 bytes
Performance Improvement 2.20 2.00 1.80 1.60 1.40 1.20 1.00 1.97 1.49

1.45 1.16 1.18 1.20 1.21 1.26 1.29

1.32

1.40

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Eleventh optimization: Reducing Misses by Software Prefetching Data

Data Prefetch Load data into register (HP PA-RISC loads) Cache Prefetch: load into cache (MIPS IV, PowerPC, SPARC v. 9) Special prefetching instructions cannot cause faults; a form of speculative execution Issuing Prefetch Instructions takes time

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Is cost of prefetch issues < savings in reduced misses? Higher superscalar reduces difficulty of issue bandwidth

The techniques to improve hit time, bandwidth, miss penalty and miss rate generally affect the other components of the average memory access equation as well as the complexity of the memory hierarchy.