Digital Design Lec1 Introduction
Digital Design Lec1 Introduction
Digital Design
Lecture 1: Course Overview Fall 2010
Xuan-Tu Tran, PhD Faculty of Electronics and Telecommunication (FET) Key Laboratory on Smart Integrated Systems (SIS) UET-VNU Hanoi Email: [email protected] www.uet.vnu.vn/~tutx
General Information
Lecturer
Xuan-Tu Tran, PhD Office: Room 314, Building G2 (by appointment) Tel.: +84-4-3754 9664 (Office) Email: [email protected] (recommended) Home page: http://www.uet.vnu.edu.vn/~tutx
Teaching Assistants
Van-Huan Tran, Researcher (SIS laboratory) Van-Mien Nguyen, Researcher, M.Sc. student (SIS laboratory) Duy-Hieu Bui, Researcher, MSc. Student (SIS laboratory)
2
Administrative Details
Grading
Take-Home Entry Exam Project Exams Final Exam (writing) 10% 40% 50%
Administrative
Office:
Room 314, G2 building, UET campus
Office hours
Tuesday: 13h00-14h00 Friday: 16h30-17h30 Other times by appointment Sending e-mails is a good way to reach me
Ressources
IEEE Standard 1076-1993
Find using search engines on WWW (Google)
Honor
You are encouraged to collaborate with other students in projects Final VHDL code, project report for each homework should be done by your self Exams are closed book, closed notes (only pen, blank paper, and a prepared computer are allowed)
Administration
Text books
Digital Design: Principles and Practices (4th edition), ISBN 0-13-186389-4
By John F. Wakerly, Prentice Hall, June 2010 Available at Laboratory on Smart Integrated Systems
References
Digital Design Fundamentals
By Kenneth J. Breeding, 2nd Ed., Prentice Hall, 1992 Available at Laboratory on Smart Integrated Systems
Wai-Kai Cheng (Editor). Logic Design. CRC Press, ISBN: 0-8493-1734-7, 2003.
Course Objectives
Students should be able to
Analyzing digital systems Understanding numbering systems, Boolean Algebra (conversion, calculation) Designing, analyzing combinational circuits (adders, multiplexers) Designing, analyzing sequential circuits (flip-flops, registers, counters, FSM, ALU, processors) Hardware description languages and EDA/CAD tools Build their own projects and report related matters
Course outline
Introduction Numbering Systems and Codes Digital Circuits Boolean and Switching Algebra Combinational logic design principles Hardware description languages Combinational logic design practices Sequential logic design principles Sequential logic design practices Memory, CPLD, and FPGAs
10
11
Examples
Digital TVs (Multimedia)
VLSI Systems
(Systems-on-Chip)
IC products
Processors
CPU, DSP, Controllers
Memory chips
RAM, ROM, EEPROM
Analog
Mobile communication, audio/video processing
Programmable
PLA, FPGA
Embedded systems
Used in cars, factories Network cards
System-on-chip (SoC)
13
14
A digital system is one that accepts as input digital information representing numbers, symbols, or physical quantities, processes this input information in some specific manner, and produces a digital output.
Digital inputs
Digital System
Digital outputs
15
???
Computer (digital)
???
Nature (analog)
17
Voltage/Current
Computer Computer
DAC DAC
(0 & 1)
18
Examples
Monitoring the environment for the developer used on a photographic processing lab
We must to measure the temperature of the developer Then, use the results to turn on/off a heating element
Heater H1 S S Monitoring & Control System
Heater
Sensors
20
Examples (cont.)
ATM (Automatic Teller Machine)
We must to measure the temperature of the environment surrounding ATMs Then, use the results to turn on/off air-conditioners
21
22
23
24
Moore law
- Feature sizes are getting smaller : - 0.25 m, 0.18 m, 0.12m, 90nm, 65nm, 45nm, 32nm - Gates counts and memory sizes are increasing : - 10M, 20M, 100M, 1 G! - Clock speeds are increasing : - 100Mhz, 400Mhz, 1 GHz, 3 GHz, - Power cannot increase at the same pace : - 10W, 20W, 50W, 100W, - Design time cannot increase : - 3m, 6m, 12m !!!
25
Deep Submicron
Microprocessor Trends
100 90 Transistors (Millions) 80 70 60 50 40 30 20 10 0 1970 1980 1990
G4 P4 Alpha (R.I.P)
2000
Sources: http://www.intel.com/pressroom/kits/quickreffam.htm
27
100 10 4 1 0.25 0.1 0.01 1975 1980 1985 1990 1995 0.0625 1 16
64
Size (Mb)
2000
2005
28
Vax 11/780
Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed., Morgan-Kaufmann, 2002.
29
Memory
DRAM capacity: (4x every 3 years) Speed: Cost per bit: increases ~ 10% per year decreases ~25% per year increases ~ 60% per year
30
31
Intel 4004
Introduction date: November 15, 1971 Clock speed: 108 KHz Number of transistors: 2,300 (10 microns) Bus width: 4 bits Addressable memory: 640 bytes Typical use: calculator, first microcomputer chip, arithmetic manipulation
33
Process Shrinks
Pentium 4
42M transistors / 1.3-1.8GHz 49-55W L=180nm
Pentium 4
0.18-micron process technology (2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz) Introduction date: August 27, 2001 (2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache (Integrated) System Bus Speed: 400 MHz SSE2 SIMD Extensions Transistors: 42 Million Typical Use: Desktops and entrylevel workstations 0.13-micron process technology (2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 512 KB Advanced Transistors: 55 Million
35
36
Challenges
Complexity Tasks management On-chip communication Chip temperature etc.
38
39
40
nVidia GeForce4
57M transistors / 300MHz / ??W L=0.15m
41
FAUST chip
RAC
TX Units
ARM
AHB System
Year: 2005 130 nm CMOS (STMicroelectronics) 20-node asynchronous NoC 23 NoC units AHB subsystem including an ARM946 core 24 clocks (DFS to save power) 8 M Gates (including 81 RAM blocks) Area: core 70 mm2 - chip 80 mm2 3.3 V 275 functional I/Os - Package : TBGA 420 Power supplies: core 1.2 V I/Os
D. Lattard, et al. ISSCC07
42
RX Units
ETH
DART
FAUST Architecture
NOC1 IF 84 Pads RAC SPort APort EXP OFDM MOD. ALAM. MOD. CDMA MOD. MAPP. BIT INTER. TURBO CODER CONV. CODER Clk & Test CTRL
NoC Perf.
RAM
AHB
CPU
RAM
RAM IF 58 Pads
HouseKeeping NoC Async/Sync IF Async node FRAME SYNC. EXP NOC2 IF 83 Pads SPort DART APort ODFM DEM. CDMA DEM. DEMAPP. DEINTER. ROTOR EQUAL. CHAN. EST. CONV. DEC. ETHER NET ETHERNET IF 17 Pads
43