Session - I MICROPROCESSORS-THE SOLUTION IN SEARCH OF PROBLEMS

In December 1970, Gilbert Hyatt filed a patent application entitled Single Chip Integrated Circuit Computer Architecture, the first basic patent on the microprocessor. The microprocessor was invented in the year 1971 in the Intel labs. The first processor was a 4 bit processor and was called 4004.The following table gives chronologically the microprocessor revolution.

Microprocess Year of ors Introduct ion 4004 8008 1971 1972

Word Length

Memory Addressi ng

Pins

Clock

Remarks

4 bits 8 bits

1KB 16KB

16 18

750KHz 800KHz

Intels 1st P Mark-8 used this; 1st computer for the home.

8080 8085 8086

1973 1976 1978

8 bits 8 bits 16 bits

64KB 64KB 1 MB

40 40 40

2 MHz 3-6 MHz 5-10 MHz

6000trs, Altair-1st PC Popular IBM PC, Intel became one of fortune 500 companies. PC/XT More a Microcontroller PC/AT, 15 million PCs sold in 6 years 2,75,000 transistors

8088 80186 80286

1980 1982 1982

8/16 bits 16 bits 16 bits

1MB 1 MB 16 MB real, 4GBv

40 68 68

5-8MHz 5-8MHz 6012.5MHz

80386DX

1985

32 bits

4GB real,

132

20-33MHz

64TBv 80386SX 1988 16/32 bits 16MB real, 64TBv 80486DX 1989 32 bits 4 GB real, 64TBv Pentium 1993 64 bits 4 GB, 16 KB cache

PGA 100 20MHz 32b int 16b ext

168 PGA 237 PGA

25-66MHz

60-200 MHz

Pentium Pro

1995

64 bits

Pentium II

1997

64 bits

64Gb, 256K/512 K L2 Cache 64Gb

387 PGA

150MHz

Flaot pt cop, Command line to point and click 2 intr. At a time, Process real world data like sound, hand written and photo images. Speedy CAD

242

400MHz

Pentium II Xeon

1998

64 bits

512k/1M/ 2M L2 cache 16 k L1 data + 16 k L1 instr; 512 kB/1 MB/2 MB L2 514,864 KB

528 pins LGA 370 PGA

400MHz

Pentium III Xeon

1999

64 bits

1GHz

Capture, edit & share digital photos via Internet Workstations thriving on business applications e-commerce applications

Pentium 4

2000

64 bits

423 PGA

1.3 - 2GHz

Xeon Itanium

2001 2001

64 bits 64 bits

8 MB iL3 cache 2MB/ 4MB L3 cache 1.5

3.33 GHz 418 pins FCP GA 611 800 MHz

Itanium 2

2002

64 bits

200 MHz

1.5 GHz, Professional quality movies, rendering 3D graphics. Choice of operating system Enabling ecommerce security transactions Business

9MB L3 cache Centrino mobile Pentium 4 processor extreme Centrino M (mobile) 2003 64 bits

pins FCP GA

applications

2003

64 bits

2 MB L2 cache

423 pins PGA

3.80 GHz

2004

64 bits

Mobile specific, increased battery life. Hyper threading technology, games 90nm,2MB L2 cache400MHz power-system optimized system bus

MOTOROLA: Microprocess Year of ors Introduct ion 6800 6809 68000 68008 1974 1979 1979 1982 8 bits 8 bit 16 bit 8 bit Word Length Memory Addressi ng 64 KB 64 KB 16 MB 1/4 MB 40 40 64 48/ 52 pins IIW for VM 84 pins Increased memory addressing capacity 68020 1984 32 bit 4 GB 114P GA 68030 68040 68060 1987 1989 32 bit 32 bit 64 bit 4 GB 4GB 4GB + 16K cache 12.533MHz 20-33MHz 20-25 MHz 50MHz MMU Floating pt cop 256B instr cache 1MHz 4-8 MHz 10-25 MHz More powerful Popular Pins Clock Remarks

68010 68012

1983 1983

16 bit 16/32 bits

16 MB 2GB

PowerPC

64 bit

4GB + 32K cache

Apart from Intel, Motorola, Zylog Corporation, Fairchild and National (Hitachi, Japan) are some of the other microprocessor manufacturers.

Microprocessors are used in all modern appliances, which are Intelligent, meaning that they are capable of different modes of working. For example an automatic washing machine has different wash options, one for woolen and the other for nylon etc., Also in a printing Industry right from type setting to page lay out to color photo scanning and printing and cutting and folding are also taken care of by microprocessors.

The applications of microprocessors can be sub divided into three categories. The first and most important one is the computer applications. The second one is the control application (micro controllers, embedded controllers etc.) and the third is in Communication (DSP processors, Cell phones etc.).

The basis of working of all the microprocessors is binary arithmetic and Boolean logic. The number system used is Hexadecimal (base 16) and the character code used is ASCII. Many assemblers are available to interface the machine code savvy processor to English language like programs of the users.(CP/M, MASM, TASM etc.).

For Games we have joysticks, electronic guns and touch screens. Nowadays laptop and palmtop computers are proliferating and in future nano computing, bio computing, molecular and optical computing also are contemplated.

Session - II ADVANCED MICROPROCESSORS

Contents Microprocessor Based Personal Computer System Different Devices Summary of Simple Microcomputer Bus Operation

Microprocessor Based Personal Computer System

DATA BUS INPUT DEVICE CONTROL BUS I/O PORTS OUTPUT DEVICE ADDRESS BUS CENTRAL PROCESSING UNIT (CPU) CONTROL BUS MEMORY (RAM AND ROM)

Different Components of Computers Microprocessor 8086, 8088, 80186, 80188, 80286, 80386, 80486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium IV Memory System DRAM, SRAM, Cache, ROM, Flash Memory, EEPROM, SDRAM, RAMBUS I/O System Printer, Serial communications, Floppy Disk Drive, Hard Disk Drive, Mouse, CD-ROM drive, Plotter, Keyboard, Monitor, Tape backup, Scanner, DVD, Pen Drive

Execution of a three-step computer program

MEMORY

1C 2C 3C 4C 5C 6C 6A 5A 4A 3A 2A 1A 1B 2B 3B 4B 5B 6B CONTROL BUS

ADDRESS BUS

CPU

CONTROL BUS 6D 2D 2E 6F 2F 6E

I/O

PORT 01 0 1 4 5 8 9 2 6 + 3 7 -

DATA BUS PORT 03 DISPLAY

KEYBOARD

PROGRAM 1. INPUT A VALUE FROM PORT 01 2. ADD 7 TO THIS VALUE 3. OUTPUT THE RESULT TO PORT 02

SEQUENCE 1A 1B 1C 2A 2B 2C 2D 2E 2F 3A 3B 3C 4A 4B 4C 5A 5B 5C 6A 6B 6C 6D 6E 6F CPU SENDS OUT ADDRESS OF FIRST INSTRUCTION TO MEMORY CPU SENDS OUT MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY INSTRUCTION BYTE SENT FROM MEMORY TO CPU ON DATA BUS ADDRESS NEXT MEMORY LOCATION TO GET REST OF INSTRUCTION SEND MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY PORT ADDRESS BYTE SENT FROM MEMORY TO CPU ON DATA BUS CPU SENDS OUT PORT ADDRESS ON ADDRESS BUS CPU SENDS OUT INPUT READ CONTROL SIGNAL TO ENABLE PORT DATA FROM PORT SENT TO CPU ON DATA BUS CPU SENDS ADDRESS OF NEXT INSTRUCTION TO MEMORY CPU SENDS MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY INSTRUCTION BYTE FROM MEMORY SENT TO CPU ON DATA BUS CPU SENDS NEXT ADDRESS TO MEMORY TO GET REST OF INSTRUCTION CPU SENDS MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY NUMBER 07H SENT FROM MEMORY TO CPU ON DATA BUS CPU SENDS ADDRESS OF NEXT INSTRUCTION TO MEMORY CPU SENDS MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY INSTRUCTION BYTE FROM MEMORY SENT TO CPU ON DATA BUS CPU SENDS OUT NEXT ADDRESS TO GET REST OF INSTRUCTION CPU SENDS OUT MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY PORT ADDRESS BYTE SENT FROM MEMORY TO CPU ON DATA BUS CPU SENDS OUT PORT ADDRESS ON ADDRESS BUS CPU SENDS OUT DATA TO PORT ON DATA BUS CPU SENDS OUT OUTPUT WRITE SIGNAL TO ENABLE PORT

Summary of Simple Microcomputer Bus Operation 1. A microcomputer fetches each program instruction in sequence, decodes the instruction, and executes it. 2. The CPU in a microcomputer fetches instructions or reads data from memory by sending out an address on the address bus and a Memory Read signal on the control bus. The memory outputs the addressed instruction or data word to the CPU on the data bus. 3. The CPU writes a data word to memory by sending out an address on the address bus, sending out the data word on the data bus, and sending a Memory write signal to memory on the control bus. 4. To read data from a port, the CPU sends out the port address on the address bus and sends an I/O Read signal to the port device on the control bus. Data from the port comes into the CPU on the data bus. 5. To write data to a port, the CPU sends out the port address on the address bus, sends out the data to be written to the port on the data bus, and sends an I/O Write signal to the port device on the control bus.

Session - III ADVANCED MICROPROCESSORS

Contents Block Diagram of 8086 segment registers 8086 flag register format

8086 Internal Block diagram (Intel Corp.)

The block diagram of 8086 is as shown. This can be subdivided into two parts, namely the Bus Interface Unit and Execution Unit. The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction prefetch queue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First In First Out 6 byte queue.

Execution Unit: The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as source index and destination index registers. The 16-bit scratch pad registers can be split into two 8-bit registers. For example, AX can be split into AH and AL registers. The segment registers and their default offsets are given below. Segment Register CS DS Default Offset IP (Instruction Pointer) SI, DI

SS ES

SP, BP DI

The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of these operations can affect the condition flags.

Different registers and their operations are listed below: Register AX AL AH BX CX CL DX Operations Word multiply, Word divide, word I/O Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic Byte Multiply, Byte Divide Translate String Operations, Loops Variable Shift and Rotate Word Multiply, word Divide, Indirect I/O

8086/8088 MPU IP CS DS SS ES AX BX CX DX SP BP SI DI SR Instruction Pointer Code Segment Register Data Segment Register Stack Segment Register Extra Segment Register AH BE CE DH AL BL CL DL

MEMORY 00000016

Code Segment (64Kb)

Data Segment (64Kb)

Stack Segment (64Kb)

Extra Segment (64Kb)

Stack Pointer Register Break Pointer Register Source Index Register Destination Index Register Status Register

FFFFF16

Generation of 20-bit Physical Address: LOGICAL ADDRESS

SEGMENT REGISTER

0000

ADDER

20 BIT PHYSICAL MEMORY ADDRESS

8086 flag register format

BIT 15 U 14 U 13 U 12 U 11 0F 10
DF

9 IF

8
TF

7
SF

6
ZF

5 U

4
AF

3 U

2
PF

1 U

0
CF

U= UNDEFINED

(a) (b) (c) (d) (e) (f) (g) (h) (i)

(a) (b) (c) (d) (e) (f) (g) (h) (i)

: CARRY FLAG SET BY CARRY OUT OF MSB : PARITY FLAG SET IF RESULT HAS EVEN PARITY : AUXILIARY CARRY FLAG FOR BCD : ZERO FLAG SET IF RESULT = 0 : SIGN FLAG = MSB OF RESULT : SINGLE STEP TRAP FLAG : INTERRUPT ENABLE FLAG : STRING DIRECTION FLAG : OVERFLOW FLAG

There are three internal buses, namely A bus, B bus and C bus, which interconnect the various blocks inside 8086. The execution of instruction in 8086 is as follows: The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the first instruction of a program from the memory. Subsequent addresses are sent out and the queue is filled upto 6 bytes. The instructions are decoded and further data (if

necessary) are fetched from memory. After the execution of the instruction, the results may go back to memory or to the output peripheral devices as the case may be.

Session - IV ADVANCED MICROPROCESSORS

Contents
Real mode memory addressing Segment Over Ride Prefix

Real mode memory addressing

The segment registers have contents of 16-bits. Hence, 216 = 64Kb of memory can be addressed by segment registers. Normally, the segment base register contains three zeroes, so that each segment can start from say E0000 to EFFFF. The segments namely code segment, data segment, stack segment and extra segment for a particular program can be contiguous, separate or in case of small programs overlapping even. i.e., for example, code segment is supposed to have 64Kb and in case of small programs data segment may be within the code segment. To give you an example of the segment base and offset, we can consider the telephone numbers. For example, 23322651 is a telephone number out of which, 2 is a universal code, 332 is the area code, and 2651 is the offset in that area. In other words, the area telephone numbers can occupy 23320000 to 23329999.

Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyte address space of an 8086
PHYSICAL ADDRESS FFFFFH 7FFFFH MEMORY

HIGHEST ADDRESS TOP OF EXTRA SEGMENT

64K

70000H 5FFFFH

EXTRA SEGMENT BASE ES=7000H

TOP OF STACK SEGMENT

64K

50000H

STACK SEGMENT BASE SS = 5000H

TOP OF CODE SEGMENT

4489FH

64K CODE SEGMENT BASE CS=348AH TOP OF DATA SEGMENT

348A0H 2FFFFH

64K

20000H

BOTTOM OF DATA SEGMENT

Fig: Addition of IP to CS to produce the physical address of the code byte

PHYSICAL ADDRESS 4489FH MEMORY TOP OF CODE SEGMENT

38AB4H IP=4214H 348A0H

CODE BYTE

START OF CODE SEGMENT CS=348AH

(a) Diagram

CS IP + PHYSICAL ADDRESS

3 4 8 A 0 4 2 1 4 3 8 A B 4 (b) Computation

HARDWIRED ZERO

Segment Over Ride Prefix

SOP is used when a particular offset register is not used with its default base segment register, but with a different base register. This is a byte put before the OPCODE byte. 0 0 1 S R 1 1 0

SR 00 01 10 11

Segment Register ES CS SS DS

Here SR is the new base register. To use DS as the new register 3EH should be prefix.

Operand Register IP (Code address) SP(Stack address) BP(Stack Address) SI or DI(not including Strings) SI (Implicit source Address for strings) DI (Implicit Destination Address for strings)

Default CS SS SS DS DS

With over ride prefix Never Never BP+DS or ES or CS ES, SS or CS

ES

Never

Examples: MOV AX, DS: [BP], LODS ES: DATA1

S4 0 0 1 1

S3 0 1 0 1

Indications Alternate data Stack Code or none Data

Bus High Enable / Status

BHE

A0 0 1 0 1

Indications Whole word Upper byte from or to odd address Lower byte from or to even address none

0 0 1 1

Segmentation: The 8086 microprocessor has 20 bit address pins. These are capable of addressing 220 = 1Mega Byte memory. To generate this 20 bit physical address from 2 sixteen bit registers, the following procedure is adopted. The 20 bit address is generated from two 16-bit registers. The first 16-bit register is called the segment base register. These are code segment registers to hold programs, data segment register to keep data, stack segment register for stack operations and extra segment register to keep strings of data. The contents of the segment registers are shifted left four times with zeroes (0s) filling on the right hand side. This is similar to multiplying four hex numbers by the base 16. This multiplication process takes place in the adder and thus a 20 bit number is generated. This is called the base address. To this a 16-bit offset is added to generate the 20-bit physical address.

Segmentation helps in the following way. The program is stored in code segment area. The data is stored in data segment area. In many cases the program is optimized and kept unaltered for the specific application. Normally the data is variable. So in order to test the program with a different set of data, one need not change the program but only have to alter the data. Same is the case with stack and extra segments also, which are only different type of data storage facilities.

Generally, the program does not know the exact physical address of an instruction. The assembler, a software which converts the Assembly Language Program (MOV, ADD etc.) into machine code (3EH, 4CH etc) takes care of address generation and location.

Session - V ADVANCED MICROPROCESSORS

Contents Pin Diagram of 8086 Pin Details Pin Diagram of 8088 Comparison of 8086 and 8088

8086 Pin diagram

Maximum Mode Minimum Mode

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 1 13 1 14 15 16 1 17 1 18 19 20 8086

40 29 39 20 29 38 20 29 37 20 29 36 20 29 35 20 29 34 20 29 33 20 29 32 20 29 31 20 29 30 20 29 29 20 20 28 0 27 20 26 0 25 20 24 0 23 0 22 0 21 0

VCC AD15

A16 /S 3 A17 /S 4 A18 /S 5 A19 /S 6

7 MN/ MX
RD RQ/ GT0
(HOLD) (HLDA) ( WR ) ( M/I O ) ( DT/ R ) ( DEN ) (ALE) ( INTA )

BHE/S

RQ/ GT1

LOCK S2
S1 S0 QS0
QS1

TEST READY
RESET

8086 is a 40 pin DIP using MOS technology. It has 2 GNDs as circuit complexity demands a large amount of current flowing through the circuits, and multiple grounds help in dissipating the accumulated heat etc. 8086 works on two modes of operation namely, Maximum Mode and Minimum Mode.

(i) Power Connections

Pin Description:

GND Pin no. 1, 20 Ground CLK Pin no. 19 Type I Clock: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. VCC Pin no. 40 VCC: +5V power supply pin

(ii) Address/ Data Lines

Pin Description AD15-AD0 Pin no. 2-16, 39 Type I/O Address Data bus: These lines constitute the time multiplexed memory/ IO address (T1) and data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of of the data bus, pins D7-D0. It iss low when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus hold acknowledge.

(iii) Address Lines

A19/S6, A18/S5, A17/S4, A16/S3 Pin no. 35-38 Type O Address / Status: During T1 these are the four most significant address lines for memory operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, TW and T4. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. A17/S4 and A16/S3 are encoded as shown. A17/S4 0 (LOW) 0 1(HIGH) 1 S6 is 0 (LOW) This information indicates which relocation register is presently being used for data accessing. A16/S3 0 1 0 1 Characteristics Alternate Data Stack Code or None Data

These lines float to 3-state OFF during local bus hold acknowledge.

(iv) Status Pins S0 - S7

Pin Description
S 2 , S1 , S 0 - Pin no. 26, 27, 28 Type O

Status: active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3 or during TW when READY is HIGH. This status is used by the 8288 Bus Controller to generate all memory and I/O access control signals. Any change by S 2 , S1 or S 0 during T4 is used to indicate the beginning of a bus cycle and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These signals float to 3-state OFF in hold acknowledge. These stat us lines are encoded as shown.
S2 S1 S0

Characteristics Interrupt acknowledge Read I/O Port Write I/O Port Halt Code Access Read Memory

0(LOW) 0 0 0 1(HIGH) 1

0 0 1 1 0 0

0 1 0 1 0 1

1 1 Status Details

1 1

0 1

Write Memory Passive

S2
0 0 0 0 1 1 1 1

Indication
0

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Interrupt Acknowledge Read I/O port Write I/O port Halt Code access Read memory Write memory Passive

S4 0 0 1 1

S3 0 1 0 1

Indications Alternate data Stack Code or none Data

S5 S6

----- Value of Interrupt Enable flag ----- Always low (logical) indicating 8086 is on the bus. If it is tristated another bus master has taken control of the system bus.

S7

----- Used by 8087 numeric coprocessor to determine whether the CPU is a 8086 or 8088

(v) Interrupts

Pin Description: NMI Pin no. 17 Type I Non Maskable Interrupt: an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized. INTR Pin No. 18 Type I Interrupt Request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

(vi) Min mode signals

Pin Description:

HOLD, HLDA Pin no. 31, 30 Type I/O HOLD: indicates that another master is requesting a local bus hold. To be acknowledged, HOLD must be active HIGH. The processor receiving the hold request will issue HLDA (HIGH) as an acknowledgement in the middle of a T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will LOWer the HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. The same rules as RQ/ GT apply regarding when the local bus will be released. HOLD is not an asynchronous input. External synchronization should be provided if the system can not otherwise guarantee the setup time.
WR - Pin no. 29 Type O

Write: indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active LOW, and floats to 3-state OFF in local bus hold acknowledge.

M/I O - Pin no. 28 type O

Status line: logically equivalent to S2 in the maximum mode. It is used to distinguish a memory access from an I/O access. M/IO becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (M=HIGH), IO=LOW). M/IO floats to 3state OFF in local bus hold acknowledge.
DT/ R -Pin no. 27 Type O

Data Transmit / Receive: needed in minimum system that desires to use an 8286/8287 data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically DT/ R is equivalent to S1 in the maximum mode, and its timing is the same as for M/IO . (T=HIGH, R=LOW). This signal floats to 3-state OFF in local bus hold acknowledge.
DEN - Pin no. 26 Type O

Data Enable: provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of T2 until the middle of T4.
DEN floats to 3-state OFF in local bus hold acknowledge.

ALE Pin no. 25 Type O Address Latch Enable: provided by the processor to latch the address into the 8282/8283 address latch. It is a HIGH pulse active during T1 of any bus cycle. Note that ALE is never floated.
INTA - Pin no. 24 Type O INTA is used as a read strobe for interrupt acknowledge cycles. It is active LOW during

T2, T3 and TW of each interrupt acknowledge cycle.

(vii) Max mode signals

Pin Description:
RQ/ GT0 , RQ/ GT1 - Pin no. 30, 31 Type I/O

Request /Grant: pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bidirectional with
RQ/ GT0 having higher priority than RQ/ GT1 . RQ/ GT has an internal pull up resistor so

may be left unconnected. The request/grant sequence is as follows: 1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (hold) to the 8086 (pulse 1) 2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the 8086 to the requesting master (pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter the hold acknowledge state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during hold acknowledge. 3. A pulse 1 CLK wide from the requesting master indicates to the 8086 (pulse 3) that the hold request is about to end and that the 8086 can reclaim the local bus at the next CLK.

Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead CLK cycle after each bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met: 1. Request occurs on or before T2. 2. Current cycle is not the low byte of a word (on an odd address) 3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A locked instruction is not currently executing.

LOCK - Pin no. 29 Type O LOCK : output indicates that other system bus masters are not to gain control of the
system bus while LOCK is active LOW. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and floats to 3-state OFF in hold acknowledge.

QS1, QS0 Pin no. 24, 25 Type O Queue Status: the queue status is valid during the CLK cycle after which the queue operation is performed. QS1 and QS0 provide status to allow external tracking of the internal 8086 instruction queue.

QS1 0(LOW) 0 1 (HIGH) 1

QS0 0 1 0 1

Characteristics No operation First Byte of Op Code from Queue Empty the Queue Subsequent byte from Queue

(viii) Common Signals

Pin Description:
RD

- Pin no. 34, Type O

Read: Read strobe indicates that the processor is performing a memory of I/O read cycle, depending on the state of the S2 pin. This signal is used to read devices which reside on the 8086 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH in T2 until the 8086 local bus has floated. This signal floats to 3-state OFF in hold acknowledge. READY Pin no. 22, Type I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory / IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.

TEST - Pin No 23 Type I TEST : input is examined by the Wait instruction. If the TEST input is LOW execution

continues, otherwise the processor waits in an idle state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

RESET Pin no. 21 Type I Reset: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized.

BHE/S - Pin No. 34 Type O 7

Bus High Enable / Status: During T1 the Bus High Enable signal ( BHE )should be used to enable data onto the most significant half of the data bus, pins D 15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S ,7 status information is available during T2, T3 and T4. The signal is active LOW and floats to 3state OFF in hold. It is LOW during T1 for the first interrupt acknowledge cycle.
BHE

A0 0 1 0 1

Characteristics Whole word Upper byte from / to odd address Lower byte from / to even address None

0 0 1 1

MN/ MX - Pin no. 33 Type - I

Minimum / Maximum: indicates what mode the processor is to operate in. If the local bus is idle when the request is made the two possible events will follow: 1. Local bus will be released during the next clock. 2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

8088 Pin diagram

GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 1 13 1 14 15 16 1 17 1 18 19 20 8088

40 29 39 20 29 38 20 29 37 20 29 36 20 29 35 20 29 34 20 29 33 20 29 32 20 29 31 20 29 30 20 29 29 20 20 28 0 27 20 26 0 25 20 24 0 23 0 22 0 21 0

VCC AD15

A16 /S 3 A17 /S 4 A18 /S 5 A19 /S 6

HIGH (SSO )

MN/ MX
RD RQ0/ GT0

(HOLD) (HLDA)
( WR ) ( IO/ M ) ( DT/ R ) ( DEN ) (ALE) ( INTA )

RQ1/ GT1

LOCK S2
S1 S0 QS0
QS1

TEST READY
RESET

Comparison of 8086 and 8088:

1. In 8088 we have A15-8, instead of AD15-8 of 8086. this is because, the 8088 can communicate with the outside world using only 8 bits o data. However, the registers in 8088 and 8086 are same, and the instruction set is also the same. So, for word operations, the 8088 has to access information twice. Thus the execution time is increased in the case of 8088.

2. In 8086 pin 28 is assigned for the signal M/IO* in the minimum mode. But in 8088, this pin is assigned to the signal IO/M* in the minimum mode. This change has been done in 8088 so that the signal is compatible with 8085 bus structure. 3. The instruction queue length in the case of 8086 is 6 bytes. The BIU in 8088 needs more time to fill up the queue a byte at a time. Thus to prevent overuse of the bus by the BIU, the instruction queue in 8088 is shortened to 4 bytes. 4. To optimize the working of the queue, the 8086 BIU will fetch a word into the queue whenever there is a space for a word in the queue. The 8088 BIU will fetch a byte into the queue whenever there is space for a byte in the queue. 5. Pin number 34 of 8086 is BHE*/S7. BHE* is irrelevant for 8088, which can only access 8 bits at a time. Thus pin 34 o 8088 is assigned for the signal SSO*. This pin acts like SO* status line in the minimum mode of operation. So, in the minimum mode, DT/R*, IO/M*, and SSO* provide the complete bus status as shown below. IO/M* 1 1 1 1 0 0 0 0 DT/R* 0 0 1 1 0 0 1 1 SSO* 0 1 0 1 0 1 0 1 Bus Cycle Interrupt acknowledge Read I/O port Write I/O port Halt Code Access Read Memory Write Memory Passive

6. In the maximum mode for 8088 the SSO* (pin 34) signal is always a 1. In the maximum mode for 8086, the BHE*/S7 (pin 34) will provide BHE* information during the first clock cycle, and will be 0 during subsequent clock cycles. In maximum mode, 8087 will monitor this pin to identify the CPU as a 8088 or a 8086, and accordingly sets its own queue length to 4 or 6 bytes.

Session - VI ADVANCED MICROPROCESSORS

Contents Bus Timing Ready and Wait states 8284 Clock Generator

Minimum Mode 8086 System:

A minimum mode of 8086 configuration depicts a stand alone system of computer where no other processor is connected. This is similar to 8085 block diagram with the following difference. The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two control signals data transmit/ receive are connected to the direction

input of transceiver (Transmitter/Receiver) and DEN* signal works as enable for this block.

Read Cycle Timing Diagram for Minimum Mode

In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for Read operation. To validate the data, DEN* signal goes low. The Address/ Status bus carries A16 to A19 address lines during BHE* (low) and for the remaining time carries Status information. The Address/Data bus carries A0 to A15 address information during ALE going high and for the remaining time it carries data. The RD* line going low indicates that this is a Read operation. The curved arrows indicate the relationship between valid data and RD* signal. The TW is Wait time needed to synchronize the fast processor with slow memory etc. The Ready pin is checked to see whether any peripheral needs more time for data transmission.

Write Cycle Timing Diagram for Minimum Operation

This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating it is a Data Transmission operation for the processor to memory / peripheral. Again DEN* line goes low to validate data and WR* line goes low, indicating a Write operation.

Bus Request & Bus Grant Timings in Minimum Mode System

The HOLD and HLDA timing diagram indicates in Time Space HOLD (input) occurs first and then the processor outputs HLDA (Hold Acknowledge).

Maximum Mode 8086 System

In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type 8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are shared resources between the two processors. The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788. The three status outputs S0*, S1*, S2* from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals perform the same task as the minimum mode operation. However the DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter.

Memory Read Timing in Maximum Mode

Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* are active and are used to generate control signal.

Memory Write Timing in Maximum Mode

Here the maximum mode write signals are shown. Please note that the T states correspond to the time during which DEN* is LOW, WRITE Control goes LOW, DT/R* is HIGH and data output in available from the processor on the data bus.

RQ / GT Timings in Maximum Mode

Request / Grant pin may appear that both signals are active low. But in reality, Request signal goes low first (input to processor), and then the processor grants the request by outputting a low on the same pin.

Read and Write Cycle Timing diagram of 8088

In 8088, the timing diagram for both Read and Write are indicated along with Ready signal and Wait states. In 8088, there are only 8 data lines as compared to 16 lines in the case of 8086. The figure shown above is for a minimum mode operation of 8088.

8284 Clock Generator

The clock Generator 8284 performs the following tasks in addition to generating the system clock for the 8086/8088. 1. Generating the Ready signal for h 8086/8088 2. Generating the Reset signal for h 8086/8088

8284 Block Diagram

8284 Pin Diagram

Clock Logic
The clock logic generates the three output signals OSC, CLOCK, and PCLK.

OSC is a TTL clock signal generated by the crystal oscillator in 8284. Its frequency is same as the frequency of the crystal connected between X1 and X2 pins of 8284. In a PC, a crystal of 14.31 MHz is connected between X1 and X2. thus OSC output frequency will be 14.31MHz. This signal is used by the Color Graphics Adapter (CGA). The Tank input is used by the crystal oscillator only if the crystal is an overtone type crystal. An LC circuit is connected to the TANK input to tune the oscillator to the overtone frequency of the crystal. Generally, in PCs, the TANK input is connected to ground, as fundamental type crystal is used in a PC. The Clock output of 8284 is used as the system clock for the 8086/8088, 8087, and the bus controller 8288. It is having a duty cycle of 33%. It is derived from the OSC frequency generated by the crystal oscillator, or from an External Frequency Input (EFI). These two signals are inputs to a multiplexer. The F/C* (external frequency/crystal) input to the multiplexer decides this aspect. If F/C*=0, OSC frequency is used for deriving Clock. If F/C*=1, EFI input is used for deriving clock. The output of the multiplexer, which is OSC or EFI, is divided by 3 to provide the Clock output. Thus, if F/C*=0, clock frequency will be 14.31MHz/3=4.77MHz. Turbo PCs use 30MHz crystal oscillator circuit for generating EFI input. With F/C*=1, they allow turbo clock speed of 10MHz. Such PCs provide a choice of switching between 4.77MHz and 10MHz using a toggle switch or manual operation. The switching can also be controlled by software using an output port.

The CSYNC input is a synchronization signal for synchronizing multiple 8284s in a system. In a PC, CSYNC is tied to ground, as there is a single 8284. PCLK frequency output is obtained by dividing clock frequency by 2. PCLK is used by dividing clock frequency by 2. PCLK is used by support chips like 8254 timer, which need a lower frequency for their operation. Pin functions of 8284A: X1 and X2 The Crystal Oscillator pins connect to an external crystal used as the timing source for the clock generator and all its functions. EFI The External Frequency input is used when the F/C is pulled high. EFI supplies the timing whenever the F/C* pin is high. F/C* The Frequency/Crystal select input results the clocking source for the 8284A. If this pin is held high, an external clock is provided to the EFI input pin, and if it is held low, the internal crystal oscillator provides the timing signal. CSYNC The clock synchronization pin is used whenever the EFI input provides synchronization in systems with multiple processors. When the internal crystal oscillator is used, this pin must be grounded. OSC The Oscillator output is a TTL level signal that is at the same frequency as the crystal or EFI input. (The OSC output provides and EFI input to other 8284A clock generators in some multiple processor systems). CLK The clock output pin provides CLK input signal to the 8086/8088 microprocessors (and other components in the system). The CLK pin has an output signal that is one-third of the crystal or EFI input frequency and has a 33 percent duty cycle, which is required by the 8086/8088. PCLK The Peripheral Clock signal is one-sixth the crystal or EFI input frequency and has a 50 percent duty cycle. The PCLK output provides a clock signal o the peripheral equipment in

the system.

Clock Generator (8284A and the 8086/8088 microprocessor illustrating the connection for the clock and reset signals (A 15 MHz crystal provides the 5 MHz clock for the microprocessor)

Ready Logic
The Ready Logic generates the Ready signal for the 8086/8088. If the Ready signal is made low by this circuit during T2 state of a machine cycle, the microprocessor introduces a wait state between T3 and T4 states of the machine cycle.

The Ready logic is indicated in the figure. There are two pairs of signals in 8284 which can make the Ready output of 8284 to go low. If (RDY1=0 or SEN1*=1) and (RDY2=0 or AEN2*=1), the Ready output becomes low when the next clock transition takes place. In PCs, RDY2 and AEN2* are not used, and as such RDY2 is tied to Ground and /or AEN2* is tied to +5V. AEN1* is used for generating wait states in the 8086/8088 bus cycle, and RDY1 is used for generating wait state in the DMA bus cycle.

Reset Logic

The Reset logic generates the Reset input signal for the 8086/8088. When the REST* pin goes low, the Reset output is generated by the 8284 when the next clock transition takes place.

In PCs, the RES* input is activated by one of the following. 1. From the manual Reset button on the front panel. 2. From the Power on Reset circuit, which uses RC components. 3. If the Power Good signal from the SMPS is not active.

Session - VII ADVANCED MICROPROCESSORS

Contents

Need for numeric coprocessor 8087 Pin Diagram 8087 Data Types Numeric examples

8087 Numeric Co-processor

Need for a numeric co-processor
The 8086 microprocessor is basically an integer processing unit and works directly on a variety of integer data types. Many programs used in engineering, science, business, need to perform mathematical operations like logarithms of a number, square root of a number, sine of an angle etc. It may also be needed to perform computations with very large numbers like 10+56, or very small numbers like 10-67. There are no instructions in 8086 to directly find sine of an angle etc. Also 8086 can only perform computations on 16 bit fixed point numbers, with a range of 32768 to +32767. In other words, 8086 does not provide any intrinsic support for operations on floating point numbers.

It is possible to perform any calculations using only 8086. But if speed becomes important, it is necessary to use the dedicated Numeric co-processor Intel 8087, to speed up the matters. It typically provides a 100 fold speed increase for floating point operations. A numeric co-processor is also variously termed as arithmetic co-processor, math co-processor, numeric processor extension, numeric data processor, floating point processor etc.

8087 Pin diagram

GND (A14) AD14 (A13) AD13 (A12) AD12 (A11) AD11 (A10) AD10 (A9) AD9 (A8) AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC MI NC CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 1 13 1 14 15 16 1 17 1 18 19 20 8087

40 29 39 20 29 38 20 29 37 20 29 36 20 29 35 20 29 34 20 29 20 33 29 32 20 29 31 20 29 30 20 29 29 20 20 28 0 27 20 26 0 25 20 24 0 23 0 22 0 21 0

VCC AD15

A16 /S 3 A17 /S 4 A18 /S 5 A19 /S 6

BHE/S

RQ/ GT1

INT
RQ/ GT0

NC NC
S2 S1 S0 QS0
QS1 BUSY READY RESET

Description of 8087 pins

INT: This is an active high output pin. The 8087 activates this pin whenever an exception occurs during 8087 instruction execution, provided the 8087 interrupt system is enabled and the relevant exceptions is not masked using the 8087 control register. The INT output of 8087 is connected directly to NMI or INTR input of 8086. Alternatively, INT output of 8087 is connected to an interrupt request input of 8259 Interrupt controller, which in turn interrupts the 8086 on its INTR input.

BUSY: Let us say, the 8086 is used in maximum mode and is required to wait for some result from the co-processor 8087 before proceeding with the next instruction. Then we can make the 8086 execute the WAIT instruction. Then the 8086 enters an idle state, where it is not performing any processing. The 8086 will stay in this idle state till TEST* input of 8086 is made 0 by the coprocessor, indicating that the co-processor has finished its computation. When the 8087 is busy executing an arithmetic instruction, its BUSY output line will be in the 1 state. This pin is connected to TEST*pin of 8086. Thus when the BUSY pin is made 0 by the 8087 after the completion of execution of an arithmetic instruction, the 8086 will carry on with the next instruction after the WAIT instruction.

Internal Structure of the 80X87

Numeric Execution Unit (NEU) Exponent Module Shifter

Control Unit (CU) Control register Status register Instruction Decoder Data Data Buffer Operand Queue T a g Status Address Bus tracking Exceptions r e g i s t e r

Arithmetic Module

Temporary registers (7) (6) (5) (4) (3) (2) (1) (0) 80-bit wide stack

Fig: The internal structure of the 80X87 arithmetic coprocessor

8087 Data Types

The 8087 always works on 80 bit data internally. This 80 bit floating point format is termed as Temporary Real format. However, it can read from memory a number, which is represented using any of the following data types. a. Signed integers of size 16, 32 or 64 bits b. 18 digit signed integer packed BCD number using 80 bits c. Floating point numbers using 32, 64, or 80 bits This number read from memory is internally converted to the 80 bit temporary real format before performing any computations. Similarly, the result is converted automatically by the 8087 to one of the formats mentioned above before storing it in memory.

8087 Data Types: 1. Integer Data Types

(a) Word integer (16 Bit Signed Integer)

S 15 Magnitude 0

Sign bit is 0 for positive and 1 for negative. Range: 32768<=X<=+32767. Negative number representation in 2s complement form.

(b) Short integer (32 Bit Signed Integer)

S 31 Range: 2 x 10 <=X<= 2 x 10
9 9

Magnitude 0

(c) Long Integer (64 Bit Signed Integer)

S 63 This is called binary integer. Range: Magnitude 0 9 x 1018 <=X<= 9 x 1018

2. Packed BCD type Packed Decimal (18 BCD digits) S 79 Dont care Magnitude (BCD)

72 71 0

-99 99<=X<=+99 99(18 digits)

3. 32 Bit Short real

Short real (Single precision) S 31 Biased exponent 23 Significand 0

0,1,2x10-38 <=!X! <=3.4x1038

Example 1: Let us say, we want to represent 23.25 in this the short real notation. First of all we represent 23.25 in binary as 10111.01. Then we represent this as +1.011101x2+4. This is called the Normalized form of representation. In the normalized form, the mantissa will always have an integer part with value 1. The floating point notations supported by 8087 always represent a number in the normalized form. In the 32 bit and 64 bit floating point notations the integer part of mantissa, of value 1, is just implied to be present, but not explicitly indicated in the bit pattern for the number. Thus the LS 23 bits are used to indicate only the fractional part of the mantissa and so will be 011 1010 0000 0000 0000 0000. The MS bit will be 0 to indicate that the number is positive. The next 8 bits provide the exponent in excess 7FH format. Thus the next 8 bits will be 4 + 7F=83H = 1000 0011. Thus the 32 bit floating point representation for 23.25 will be sign 23 bit fractional part of mantissa

Exp. In Ex 7FH
0 1000 0011 011 1010 0000 0000 0000 0000

Example 2:

Now let us see what is the value of the 32 bit floating point number 10111 1100 100 0000 0000 0000 0000 0000. It has its MS bit as a 1. Thus the number is negative. The next 8 bits are 0111 1100 = 7CH. Thus 7CH is the exponent in excess 7FH format. In other words, the actual exponent is 7CH-7FH=-03. the actual mantissa is obtained by appending 1. to the LS 23 bits. Thus the actual mantissa is 1.100 0000 0000 0000 0000 0000. Thus the value of the given 32 bit floating point number would be -1.100 0000 0000 0000 0000 0000 x 2-03 = = = = -1.1 x 2-03 -0.0011 x 20 -0.0011 -0.1875

Thus the given 32 bit number represents the value 0.1875

4. 64 bit Long Real

Long Real (Double precision) S 63 Biased exponent 52 Significand 0

0,2,3 x 10-308 !X!<= 1.7x 10308 In both single and double precision cases the 1 after . is assumed to be present.

Sign 0=+ 1=-

11 bits exponent in Ex3FFH

52 bits for fractional part with implied 1. before the fractional part.

Example 1: Let us say, we want to represent 23.255 in this notation. First of all we represent 23.25 in binary as 10111.01. Then we represent this as +1.011101x2+4. This is called the Normalized form of representation. In the normalized form, the mantissa will always have an integer part with value 1. The floating point notations supported by 8087 always represent a number in the normalized form. In the 32 bit and 64 bit floating point notations the integer part of the mantissa, of value 1, is just implied to be present, but not explicitly indicated in the bit pattern for the number. Thus the LS

52 bits are used to indicate only he fractional part of the mantissa and so will be 0111 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000. The MS bit will be 0 to indicate that the number is positive. The next 11 bits provide the exponent in excess 3FFH format. Thus the next 11 bits will be 4+3FF=403H=100 0000 0011. Thus the 64 bit floating point representation for 23.25 will be

sign

52 bit fractional part of mantissa

Exp. In Ex 7FH
0 100 0000 0011 0111 0100 00.00

Example 2: Now let us see what is the value of the 64 bit floating point number 1 100 0000 0011 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000. It has its MS bit as a 1. Thus the number is negative. The next 11 bits are 100 0000 0011 = 403H. Thus 403H is the exponent in excess 3FFH format. In other words, the actual exponent is 403H 3FFH=+04. The actual mantissa is obtained by appending 1. to the LS 52 bits. Thus the actual mantissa is 1.0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000. Thus the value of the given 64 bit floating point number would be -1.0100 0000 0000 x 2+04 = = = = -1.01 x 2+04 -10100 x 20 -10100 -20

Thus the given 64 bit number represents the value 20.

5. Temporary Real
S 79 0,3.4x10
-4932

Biased exponent

Significand 0
4932

64 63 <= !X! <= 1.1x10

Example 1: Let us say, we want to represent 23.25 in this notation. First of all we represent 23.25 in binary as 10111.01. Then we represent this as +1.011101 x 2+4. This is called the normalized form of

representation. In the normalized form, the mantissa will always have an integer part with value 1. The floating point notations supported by 8087 always represent a number in the normalized form. Thus the LS 64 bits are used to indicate the mantissa and so will be 1011 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000. The MS bit will be 0 to indicate that the number is positive. The next 15 bits provide the exponent in excess 3FFFH format. Thus the next 15 bits will be 4+3FFF = 4003H = 100 0000 0000 0011. Thus the 80 bit floating point representation for 23.25 will be

sign 0

Exp. In Ex. 3FFFH 100 0000 0000 0011

64 bit mantissa 1011 1010 00 .00

Example 2: Now let us see what is the value of the 64 bit floating point number 1 100 0000 0000 0011 1010 0000 . 0000. It has its MS bit as a 1. Thus the number is negative. The next 15 bits are 100 0000 0000 0011 = 4003H. Thus 4003H is the exponent in excess 3FFFH format. In other words, the actual exponent is 4003H-3FFFH=+04. The actual mantissa is 1.010 0000 . 0000, where the binary point is implied to be present after the MS bit of the mantissa. Thus the value of the given 80 bit floating point number would be -1.010 0000 0000 x 2+04 = = = = -1.01 x 2+04 -10100 x 20 -10100 -20

Thus the given 80bit number represents the value 20.

Session - VIII ADVANCED MICROPROCESSORS

Contents
8087 Data types in a nut shell

Interconnection of 8087 with 8086/88 Control Register Status register Exception Pointer Tag register FINIT instruction

8087 Data types in a nut shell

Data format Word integer Short integer Long integer Packed BCD Short real Long real 10+38 10+308 24 bits 53 bits 64 bits SE7 E0 F1 F23 F0 implicit SE10 E0 F1 F52 F0 implicit SE14 E0 F0 F63 1018 18 digits S D17 D16 D0 1018 64 bits 163 10 twos complement 104 32 bits 131 10 twos complement 104 16 bits 115 10 twos complement Range Precision 7 0!7 0!7 0!7 0!7 0!7 0!7 0!7 0!7 0!7 0!

Temporary 10+4932 real

Integer Packed BCD Real

:1 : (-1)S (D17 D0) : (-1)S (2E-Bias) (F0.F1..)

Bias = 127 for short Real = 1023 for long Real = 16383 for Temp. Real

Interconnection of 8087 with 8086/88

8087 can be connected with any of the 8086/8088/80186/80188 CPUs only in their maxim um mode of operation. I.e. only when the MN/MX* pin of the CPU is grounded. In maximum mode, all the control signals are derived using a separate chip known as bus controller. The 8288 is 8086/88 compatible bus controller while 82188 is 80186/80188 compatible bus controller. The BUSY pin of 8087 is connected with the TEST* pin of the used CPU. The QS0 and QS1 lines may be directly connected to the corresponding pins in case of 8086/8088 based systems. However, in case of 80186/80188 systems these QS0 and QS1 lines are passed to the CPU through the bus controller. In case of 8086/8088 based systems the RQ*/GT0* of 8087 may be connected to RQ*/GT1* of the 8086/8088. The clock pin of 8087 may be connected with the CPU 8086/8088 clock input. The interrupt output of 8087 is routed to 8086/8088 via a programmable interrupt controller. The pins AD0 - AD15, BHE*/S7, RESET, A19 / S6 - A16 / S3 are connected to the corresponding pins of 8086/8088. In case of 80186/80188 systems the RQ/GT lines of 8087

are connected with the corresponding RQ*/GT* lines of 82188. The interconnections of 8087 with 8086/8088 and 80186/80188 are shown in fig.

Control Register of 8087

In addition to the 8 registers, which are 80 bits wide, the 8087 has a control register, a status register, and a Tag register each 16 bits wide.

The contents of the control register, generally referred to as the Control word, direct the working of the 8087. A common way of loading the control register from a memory location is by executing the instruction FLDCW src, where src is the address of a memory location. FLDCW stands for Load Control Word. For example, FLDCW [BX] instruction loads the control register of 8087 with the contents of the memory location whose 16 bit effective address is provided in BX register.
The bit description of the control register is shown below. Bit No 15 14 13 12 I C 11 10 9 8 7 Intr mask 6 x 5 P M 4 U M 3 O M 2 Z M 1 D M 0 I M

reserved

Round ctrl

Prec. ctrl

The LS 6 bits are used for individually masking 6 possible numerical error exceptions. If an exception is masked, by setting the corresponding bit to 1, the 8087 will handle the exception internally. It does not set the corresponding exception bit in the status register and it does not generate an interrupt request. This is termed the Masked response.
They LS 6 bits, which correspond to the exception mask bits, are briefly described below. IM bit (Invalid operation Mask) at bit position 0 is used for masking invalid operation. An invalid operation exception generally indicates a stack overflow or underflow error, or an arithmetic error like, divisor is 0 or dividend is infinity. DM bit (Denormalized operand mask) at bit position 1 is used for masking denormalized operand exception. A denormalized result occurs when there is a floating point underflow. Thus, this exception occurs, for example, when an attempt is made to load a denormalized operand from memory. ZM bit (Zero divide mask) at bit position 2 is used for masking zero divide exception. This exception occurs when an attempt is made to divide a valid non zero operand by zero. This can

happen in the case of explicit division instructions as well as for operations that perform division internally like in FXTRACT. OM bit (Overflow exception Mask) at bit position 3 is used for masking overflow exception. A overflow exception occurs when the exponent of the actual result is too large for the destination. UM bit (Underflow exception Mask) at bit position 4 is used for masking underflow exception. An underflow exception occurs when the exponent of the actual result is too small for the destination. PM bit (Precision exception Mask) at bit position 5 is used for masking precision exception. A precision exception occurs when the result of an operation loses significant digits when stored in the destination. Precision control bits (bits 9 and 8) These bits control the internal operating precision of the 8087. Normally, the 8087 uses 64 bit mantissa for all internal calculations. However, this can be reduced to 53 or 24 bits, for compatibility with earlier generation math processors, as shown below. Bit 9 0 0 1 1 Bit 8 0 1 0 1 Length of mantissa 24 bits Reserved 53 bits 64 bits

Rounding control bits (bits 11 and 10) These bits control the type of rounding that is used in calculations, as shown below. Bit 11 0 0 1 1 Bit 10 0 1 0 1 Rounding scheme Round to nearest Round down, towards - Roundup, towards + Chop or truncate towards 0

Infinity control bit (bit 12) This bit controls the way infinity is treated. In the affine model of infinity, + and - are treated as a single unsigned quantity. Bit 12 0 Infinity model Projective

Affine

Contents of Control register after reset of 8087 When the 8087 is reset, the control register is loaded with 037FH = 000 0 00 11 0 1 11 1111, which means the following. The same condition results when FINIT (stands for Initialize) instruction is executed. This condition is generally acceptable to a programmer. So, there is normally no need to explicitly load the control register using FLDCW instruction.

Status register of 8087

The status register is 16 bits wide. The contents of the status register, generally referred to as the Status word, indicates the status of the 8087. A common way of storing the contents of the status register into a memory location is by executing the instruction FSTSW dst, where dst is the address of a memory location. FSTSW stands for Store Status Word. For example, FSTSW [BX] instruction stores the status register of 8087 into the memory location whose 16 bit effective address is provided in BX register. This status can then be read by the 8086, by executing say MOV AX, [BX], to take action depending on the status of 8087.

The bit description of the status register is shown below. Bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Busy C 3

Stack pointer

C 2

C C Intr 1 0 Req

P E

U O Z E E E

D I E E

If the 8087 encounters an error exception during execution of an instruction, the corresponding exception bit is set to the 1 state, if the exception is not masked using the control word. The possible exceptions, as already discussed, are as follows. Invalid operation Exception (IE, bit 0 of the status register) Denormalized operand Exception (DE, bit 1 of status register)

Zero divide Exception (ZE, bit 2 of status register) Overflow Exception (OE, bit 3 of status register) Underflow Exception (UE, bit 4 of status register) Precision Exception (PE, bit 5 of status register) The only way these exception bits are cleared is by the execution of FINIT, FCLEX (stands for clear exceptions), FLDENV (stands for load environment), FSAVE (stands for save environment and stack of registers), and FRSTOR (stands for restore environment and stack of registers). The term Environment stands for the following group of information of size 14 bytes. 1. control word (2 bytes) 2. Status word (2 bytes) 3. Tag word (2 bytes) 4. Exception pointer (8 bytes) The interrupt request bit (bit 7) in the status word is set to 1 by the 8086, if one or more exception bits are set to 1. Then the INT output pin of 8087 is activated if interrupt is not masked using the control word. C2, C2, C1, and C0 (bits 14, 10, 9, and 8) are the condition code flags of the 8087. The 8087 updates these flags depending on the status of arithmetic operations. The FTST (stands for Test) and FCOM (stands for Compare) instructions also use these flags to report the result of their operations. Some of these bits are discusses later when the Compare instruction is described. Bits 13, 12, and 11 provide the address of the register which is currently the stack top. For example, if these bits are 110, it means that R6 is the current stack top. In other words, ST is R6, ST(1) is R7, ST(2) is R0, and so on. The Busy bit (bit 15) is set to 1 when the 8087 is busy executing an instruction, or busy executing an exception routine. When this bit is a 1, the BUSY output pin of 8087 is activated. A programmer needs to read the status register contents after the execution of FTST or FCOM instruction, to know the result of these instructions. In most of other cases, the programmer is not required to read the status register contents.

Exception Pointer of 8087

When the 8086 comes across an 8087 instruction, it saves the following information in a 4 word area termed as the exception pointer. 1. 20 bit physical address of the instruction 2. 11 bit opcode of the instruction

3. 20 bit physical address of the data, if 8087 needs it. 4. Remaining 13 bits are zeros.

However, some instructions like FLDCW which need a memory operand, do not affect the 20 bit area of the exception pointer meant for address of data. The exception pointer is located in the 8086, and not in 8087, but appears to be part of 8087.

Tag register of 8087

The Tag register is 16 bits wide. The contents of the Tag register indicates the status of each of the 80 bit registers of the 8087. A common way of storing the contents of the Tag register is by executing the instruction FSTENV dst, where dst is the address of a memory location. It stores the environment of 8087, of which Tag word is a part. FSTENV stands for Store environment. For example, FSTENV [BX] instruction stores the environment of 8087 into 14 byte memory locations whose 16 bit effective address is provided in BX register. The Tag register is loaded with a new value, when one of FINIT, FLDENV, or FRSTOR instructions are executed. The bit description of the Tag register is as shown below. Bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAG 7

TAG 6

TAG 5

TAG 4

TAG 3

TAG 2

TAG 1

TAG 0

The status of each 80 bit stack register is provided using a 2 bit field in the Tag register. The field labeled TAG 3 indicates the status of R3. It should be noted that TAG 3 is not indicating the status of ST(3). The Tag bits indicate the status of a stack register as shown below. Tag bits 00 01 10 Status Valid data in the register Zero value in the register Special number, like _ or decimal, in the register 11 The register is empty

The Tag word is not normally used in programs. However it can be used to quickly interpret the contents of a floating point register, without the need for extensive decoding.

FINIT instruction
Infinity condition is projective (treats + and - as same) Rounds to nearest Length of mantissa is 64 bits Interrupt is enabled All exceptions are masked No need for FLDCW

Session - IX ADVANCED MICROPROCESSORS

Contents
8087 Instruction Set Data Transfer Instructions Arithmetic instructions Compare Instructions

8087 Instruction Set

The instruction set of 8087 starts with F, stands for floating point. The instruction of 8087 numeric data processor can be classified into following six groups: 1. Data transfer instructions 2. Arithmetic instructions 3. Compare Instructions 4. Transcendental instructions 5. Load constant instructions 6. Processor control instructions

1. Data Transfer Instructions

(a) Real Transfers

S. No. 1

Instruction FLD source

Description with example Decrements stack pointer by one and copies a real number from a stack element or memory to the new ST. A short real or longreal number from memory is automatically converted to temporary real format by the 8087 before it is put in ST. Examples: FLD ST(2) FLD [BX] ST ; Copies ST(2) to ST ; Number from memory pointed by BX copied to

FST Destination

Copies ST to a specified stack position or to a specified memory location. Examples: FST ST(3) FST [BX] ; Copy ST to ST(3) ; Copy ST to memory pointed by [BX]

FSTP destination

Copies ST to a specified stack element or memory location and increments stack pointer by one to point to the next element on the stack. This is a stack POP operation.

FXCH destination

Exchanges contents of ST with the contents of a specified stack element. If no destination is specified, then ST(1) is used. Example: FXCH ST(4) ; Swap ST and ST(4)

(b) Integer transfers S. No. 5 Instruction FILD source Description with example Integer load. Converts integer number from memory to temporary real format and pushes converted number on 8087 stack. Example: FILD DWORD PTR [BX] location pointed by [BX] 6 FIST destination Integer store. Converts number from ST to integer form, and copies to memory. Example: FIST INT_NUM ; ST to memory locations named ; Short integer from memory

INT_NUM 7 FISTP destination Integer store and pop. Similar to FIST except that stack pointer is incremented after copy. (c) Packed Decimal Transfers S. No. 8 Instruction FBLD source Description with example Packed decimal (BCD) load. Convert number from memory to temporary-real format and push on top of 8087 stack. Example: FBLD AMOUNT ; Ten byte BCD number from memory

location AMOUNT to ST 9 FBSTP destination BCD store in memory and pop 8087 stack. Pops temporary real from stack, converts to 10-byte BCD, and stores result to memory. Example: FBSTP MONEY ; Contents from top of stack are

converted to BCD, and stored in memory.

2. Arithmetic Instructions
S. No. 1 Instruction FADD destination, source Description with example Will add real number from specified source to real number at specified destination. Source can be stack element or memory location. Destination must be a stack element. If no source or destination is specified, then ST is added to ST(1) and the stack pointer is incremented so that the result of the addition is at ST. Examples: FADD ST(2), ST FADD ST, ST(5) FADD SUM FADD 2 FADDP destination, source ; Add ST to ST(2), result in ST(2) ; Add ST(5) to ST, result in ST ; Real number from memory + ST ; ST + ST(1), pop stack-result at ST

Adds ST to specified stack element and increments stack pointer by one. Example:

FADDP ST(2)

; Add ST(2) to ST ; Increment stack pointer so ST(2) ; becomes ST

FIADD source

Adds integer from memory to ST, Stores the result in ST. Example: FIADD CARS_SOLD ;Integer number from memory + ST

FSUB destination, source

Subtracts the real number at the specified source from the real number at the specified destination and puts the result in the specified destination. Examples: FSUB ST(3), ST FSUB DIFFERENCE FSUB ; ST(3) ST(2) ST ; STST-real from memory ; ST(ST(1)-ST)

FSUBP destination, source

Subtracts ST from specified stack element and puts result in specified stack element. Then increments stack pointer by one. Examples: FSUBP ST(2) ; ST(2) ST . ST(1) becomes new ST.

FISUB source

Subtracts integer number stored in memory from ST and stores result in ST. Example: FISUB DIFFERENCE ; STST-integer from memory

FSUBR destination, source

These instructions operate same as FSUB instructions discussed earlier except that these instructions subtract the contents of the specified destination from the contents of the specified source and put the difference in the specified destination. [Normal FSUB instruction subtracts source from destination.] Multiply real number from source by real number from specified destination, and put result in specified stack element. Examples: FMUL ST(2), ST FMUL ST, ST(5) ; Multiply ST(2) and ST, result in ST(2) ; Multiply ST(5) to ST, result in ST

FSUBRP destination, source

9 10

FISUBR source FMUL destination, source

FMULP destination, source

Multiplies the real number from specified source by real number from specified destination, puts result in specified stack element,

and increment stack pointer by one. With no specified operands FMULP multiplies ST(1) by ST and Pops stack to leave result at ST. Example: FMULP ST(2) ; Multiply ST(2) to ST. increment stack

pointer so STI(1) becomes ST 11 FIMUL source Multiply integer from memory at ST and put result in ST. Example: FIMUL DWORD PTR [BX] ;Integer number from memory pointed by BX x ST and result in ST 12 FDIV destination, source Divides destination real by source real, stores result in destination. Example: FDIV ST(2), ST ; Divides ST by ST(2) ; stores result in ST 13 FDIVP destination, source Same as FDIV, but also increments stack pointer by one after DIV Example: FDIV ST(2), ST ; Divides ST by ST(2), stores result in ST

and increments stack pointer 14 FIDIV source Divides ST by integer from memory, stores result in ST. Example: FIDIV PERCENTAGE; STST/integer number 15 FDIVR destination, source 16 FDIVP destination, source 17 FIDIVR source These three instructions are identical in format to the FDIV, FDIVP and FIDIV instructions above except that they divide the source operand by the destination operand and put the result in the destination. 18 FSQRT Contents of ST are replaced with its square root.

Example: FSQRT 19 FSCALE Scales the number in ST by adding an integer value in ST(1) to the exponent of the number in ST. Fast way of multiplying by integral powers of two. 20 FPREM Partial reminder. The contents of ST(1) are subtracted from the contents of ST over and over again until the contents of ST are smaller than the contents of ST(1) Example: FPREM 21 FRNDINT Round number in ST to an integer. The round control (RC) bits in the control word determine how the number will be rounded. 22 FXTRACT Separates the exponent and the significant parts of a temporary real number in ST. After the instruction executes, ST contains a temporary real representation of the significant of the number and ST(1) contains a temporary real representation of the exponent of the number. 23 FABS Replaces ST by its absolute value. Instruction simply makes sign positive. 24 FCHS Complements the sign of the number in ST.

3. Compare Instructions
These instructions compare the contents of ST with contents of specified or default source. The source may be another stack element or real number in memory. Such compare instructions set the condition code bits C3, C2 and C0 of the status words use as shown in the table below. C3 0 0 1 1 C2 0 0 0 1 C0 0 1 0 1 Description ST contents is greater than the other operand ST contents is smaller than the other operand ST contents is equal to the other operand The operands are not comparable

Different compare instructions:

S. No. 1

Instruction FCOM source

Description with example Compares ST with real number in another stack element or memory. Examples: FCOM FCOM ST(4) FCOM VALUE memory ; Compares ST with ST(1) ; Compares ST with ST(4) ; Compares ST with real number from

FCOMP source

Identical to FCOM except that the stack pointer is incremented by one after the compare operation.

FCOMPP

Compares ST with ST(1) and increments stack pointer by 2 after compare.

4 5

FICOM source FICOMP source

Compares ST to a short or long integer from memory. Identical to FICOM except stack pointer is incremented by one after compare.

6 7

FTST FXAM

Compares ST with zero. Tests ST to see if it is zero, infinity, unnormalized, or empty. Sets bits C3, C2, C1 and C0 to indicate result.

Session - X ADVANCED MICROPROCESSORS

Contents
8087 Instruction Set Transcendental instructions Load constant instructions Processor control instructions Example Programs

4. Transcendental Instructions (Trigonometric and Exponential Instructions)

S. No. 1 Instruction FPTAN Description with example Computes the values for a ratio of Y/X for an angle in ST. the angle must be expressed in radians, and the angle must be in the range of 0 < angle < /4. (FPTAN does not work correctly for angles of exactly 0 and /4.) 2 FPATAN Computes the angle whose tangent is Y/X. The X value must be in ST, and the Y value must be in ST(1). Also X and Y must satisfy the inequality 0 < Y < X < . The resulting angle expressed in radians replaces Y in the stack. After the operation the stack pointer is incremented so the result is then ST. 3 F2XM1 Computes the function Y = 2x 1 for an X value in ST. the result, Y replaces X in ST. X must be in the range 0 X 0.5 4 FYL2X Calculates Y times the log to the base 2 of X or Y (log2X). X must be in the range of 0 < X < and Y must be in the range - < Y < +. X must initially be in ST and Y must be in ST(1). The result replaces Y and then the stack is popped so that the result is then at ST. 5 FYL2XP1 Computes the function Y times the log to the base 2 of (X+1) or Y (log2 (X+1)). This instruction is almost identical to FYL2X except that it gives more accurate results when computing the logoff a number very close to one.

5. Load constant Instructions

S. No. 1 2 3 4 5 Instruction FLDZ FLDI FLDPI FLD2T FLDL2E Description - Push 0.0 onto stack - Push + 1.0 onto stack - Push the value onto stack - Push log of 10 to the base 2 onto stack (log210) - Push log of e to the base 2 onto stack (log2e)

FLDLG2

- Push log of 2 to the base 10 onto stack (log102)

Note: The load constant instruction will just push indicated constant into the stack.

6. Processor Control Instructions

S. No. 1 Instruction FINIT/FNINT Description Initializes 8087. Disables interrupt output, sets stack pointer to register 7, sets default status. 2 FDISI/FNDISI Disables the 8087 interrupt output pin so that it can not cause an interrupt when an exception (error) occurs. 3 FENI/FNENI Enables 8087 interrupt output so it can cause an interrupt when an exception occurs. 4 FLDCW source Loads a status word from a memory location into the 8087 status register. This instruction should be preceded by the FCLEX instruction to prevent a possible exception response if an exception bit in the status word is set. 5 FSTCW/FNSTCW destination 6 FSTSW/FNSTW destination Copies the 8087 control word to a memory location. You can determine its current value with 8086 instructions. Copies the 8087 status word to a memory location. You can check various status bits with 8086 instructions and take further action on the state of these bits. 7 FCLEX/FNCLEX Clears all of the 8087 exception flag bits in the status register. Unasserts BUSY and INT outputs. 8 FSAVE/FNSAVE destination Copies the 8087 control word, status word, pointers and entire register stack to 94-byte area of memory. After copying all of this the FSAVE/FNSAVE instruction initializes the 8087. 9 FRSTOR source Copies a 94 byte area of memory into the 8087 control register, status register, pointer registers, and stack registers. 10 FSTENV / FNSTENV destination Copies the 8087 control register, status register, tag words, and exception pointers to a series of memory locations. This instruction does not copy the 8087 register stack to memory as the FSAVE / FNSAVE instruction does.

11

FLDENV source

Loads the 8087 control register, status register, tag word and exception pointers from a named area in memory.

12 13 14

FINCSTP FDECSTP FFREE destination

Increment the 8087 stack pointer by one. Decrement the stack pointer by one. Changes the tag for the specified destination register to empty.

15 16

FNOP FWAIT

Performs no operation. Actually copies ST to ST. This instruction is actually an 8086 instruction which makes the 8086 wait until it receives a not busy signal from the 8087 to its TEST* pin.

Note: the processor control instructions actually do not perform computations but they are made used to perform tasks like initializing 8087, enabling intempty, etc.

8087 Programs

1. Calculate area of a circle (A = R2) given R, radius of the circle. ; Procedure that calculates the area of a circle. ; The radius must be stored at memory location RADIUS before calling this procedure. ; The result is found in memory location AREA after the procedure.

AREAS

PROC FAR FINIT FLD RADIUS ; Initialize 8087 ; radius to ST ; square radius ; to ST ; multiply ST=ST X ST(1) ; save area ; wait for coprocessor

FMUL ST, ST(0) FLDPI FMUL FSTP AREA FWAIT RET AREAS ENDP

OR

Program to calculate the area of circle. This program takes test data from array RAD that contains five sample radii. The five areas are stored in a second array called AREA. No attempt is made in this program to use the data from the AREA array.

; A short program that finds the area of five circles whose radii are stored in array RAD . MODEL SMALL .386 ; Select 80386

.387 .DATA

; Select 80387

.CODE .STARTUP MOV SI, 0 MOV DI, 0 MOV CX, 5 MAIN1: FLD RAD [SI] ; radius to ST ; square radius ; to ST ; multiply ST=ST X ST(1) ; save area ; source element 0 ; destination element 0 ; count of 5

FMUL ST, ST (0) FLDPI FMUL FSTP AREA [DI] INC INC SI DI

LOOP MAIN1 .EXIT END

FLD RAD [SI] ST (0) ST (1) ST (2) ST (3) RADIUS ST ST (0) ST (1) ST (2) ST (3)

FMUL ST, ST (0) RADIUS2 ST

FLDPI ST (0) ST (1) ST (2) ST (3) RADIUS2 ST ST (0) ST (1) ST (2) ST (3)

FMUL RADIUS2 ST

FSTP AREA [DI] ST (0) ST (1) ST (2) ST (3) ST

Fig: Operation of the stack for the above program. Note that the stack is shown after the execution of the indicated instruction.

2. Program for determining the resonant frequency of an LC circuit. The equation solved by the program is Fr = 1 / 2 LC. This example uses L1 for inductance L, C1 for capacitor C, and RESO for the resultant resonant frequency.
; A sample program that finds the resonant frequency of an LC tank circuit. . MODEL SMALL .386 ; Select 80386

.387 .DATA RESO DD L1 DD C1 DD TWO DD .CODE .STARTUP FLD L1 ? 0.000001 0.000001 2.0

; Select 80387

; resonant frequency ; inductance ; capacitance ; constant

; get L ; find LC ; find LC ; find 2LC ; get ; get 2LC ; get 1 ; form 1/2LC ; save frequency

FMUL C1 FSQRT FMUL TWO FLDPI FMUL FLD1 FDIVR FSTP RESO .EXIT END

3. Program to find the roots of a polynomial expression (ax2+bx+cc=0) by using the quadratic equation. The quadratic equation is b(b2 - 4ac)/2a Note: In this program R1 and R2 are the roots for the quadratic equation. The constants are stored in memory locations A1, B1, and C1. Note that no attempt is made to determine the roots if they are imaginary. This example tests for imaginary roots and exits to DOS with a zero in the roots (R1 and R2), if it finds them. In practice, imaginary roots could be solved for and stored in a separate set of memory locations.

; A program that finds the roots of a polynomial equation using the quadratic equation. Note ; imaginary roots are indicated if both root1 (R1) and root 2 (R2) are zero. . MODEL SMALL .386 .387 ; Select 80386 ; Select 80387

.DATA TWO DD FOUR DD A1 DD B1 DD C1 DD R1 DD R2 DD .CODE .STARTUP FLDZ FST R1 ;clear roots 2.0 4.0 1.0 0.0 -9.0 ? ?

FSTP R2 FLD TWO ; form 2a

FMUL A1 FLD FOUR FMUL A1 FMUL C1 FLD B1

; form 4ac ; form b2 ; form b2 - 4ac ; test b2 4ac for zero ; copy status register to AX ; move to flags ; if b2 - 4ac is zero ; find square root of b2 - 4ac

FMUL B1 FSUBR FTST FSTSW AX SAHF JZ FSQRT FSTSW AX TEST AX, 1 JZ ROOTS1 ROOTS1

; test for invalid error (negative)

FCOMPP JMP ROOTS1: FLD B1 ROOTS2

; clear stack ; end

FSUB ST, ST (1)

FDIV ST, ST (2) FSTP R1 FLD FADD FDIVR FSTP R2 ROOTS2: .EXIT END ; save root2 B1 ; save root1