Topics
High-density memory architecture
Memories:
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ROM; SRAM; DRAM.
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Datapaths. PLAs.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Memory operation
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Read-only memory (ROM)
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Address is divided into row, column.
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Row may contain full word or more than one word.
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Selected row drives/senses bit lines in columns. Amplifiers/drivers read/write bit lines.
ROM core is organized as NOR gatespulldown transistors of NOR determine programming. Erasable ROMs require special processing that is not typically available. ROMs on digital ICs are generally mask-programmed placement of pulldowns determines ROM contents.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
ROM core circuit
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Static RAM (SRAM)
Core cell uses six-transistor circuit to store value. Value is stored symmetricallyboth true and complement are stored on cross-coupled transistors. SRAM retains value as long as power is applied to circuit.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
SRAM core cell
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SRAM core operation
Read:
precharge bit and bit high; set select line high from row decoder; one bit line will be pulled down. set bit/bit to desired (complementary) values; set select line high; drive on bit lines will flip state if necessary.
Write:
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Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
SRAM sense amp
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Sense amp operation
Differential pairtakes advantage of complementarity of bit lines. When one bit line goes low, that arm of diff pair reduces its current, causing compensating increase in current in other arm. Sense amp can be cross-coupled to increase speed.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
3-transistor dynamic RAM (DRAM)
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3-T DRAM core cell
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First form of DRAMmodern commercial DRAMs use onetransistor cell. 3-transistor cell can easily be made with a digital process. Dynamic RAM loses value due to charge leakagemust be refreshed.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
3-T DRAM operation
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Data paths
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Value is stored on gate capacitance of t1. Read:
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A data path is a logical and a physical structure:
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read = 1, write = 0, read_data is precharged; t1 will pull down read_data if 1 is stored. read = 0, write = 1, write_data = value; guard transistor writes value onto gate capacitance.
bitwise logical organization; bitwise physical design.
Write:
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Datapath often has ALU, registers, some other function units. Data is generally passed via busses.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Typical data path structure
Slice includes one bit of function units, connected by busses:
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Bit-slice structure
Many arithmetic and logical functions can be defined recursively on bits of word. A bit-slice is a one-bit (or n-bit) segment of an operation of minimum size to ensure regularity. Regular logical structure allows regular physical structure.
registers
shift
ALU
bus
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Abutting and pitch-matching
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Wiring plans
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Cells in bit-slice may be abutted togetherrequires matching positions on terminals. Pitch-matching is designing cells to ensure that pins are at proper positions for abutting.
A wiring plan shows layer assignments and directions for major signals. Put most important signals on lowest-impedance, accessible layers.
VDD
cell1
Slides courtesy Modern VLSI Design, 3rd Edition
cell2
cell3
VSS
Slides courtesy Modern VLSI Design, 3rd Edition
Bus circuits
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Pseudo-nMOS bus circuit
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Cannot support full connectivity between all data path elementsmust choose number of transfers per cycle allowed. A bus circuit is a specialized multiplexer circuit. Two major choices: pseudo-nMOS, precharged.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Precharged bus circuit
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Programmable logic array (PLA)
Used to implement specialized logic functions. A PLA decodes only some addresses (input values); a ROM decodes all addresses. PLA not as common in CMOS as in nMOS, but is used for some logic functions.
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
PLA organization
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PLA structure
AND plane, OR plane, inverters together form complete two-level logic functions. Both AND and OR planes are implemented as NOR circuits. Pulldown transistors form programming/personality of PLA. Transistors may be referred to as programming tabs.
p1
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p2 AND plane p3 p4 OR plane
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i0 i0
Slides courtesy Modern VLSI Design, 3rd
i1 i1
Edition
product term
f0
f1
Slides courtesy Modern VLSI Design, 3rd Edition
PLA AND/OR cell
input 1 output 1 output 2 no tab VSS input 2 programming tab
Slides courtesy Modern VLSI Design, 3rd Edition
