Topics

SRAM-based FPGAs
Program logic functions, interconnect using SRAM. Advantages:

SRAM-based FPGA fabrics:

Xilinx. Altera.

Re-programmable; dynamically reconfigurable; uses standard processes.

Disadvantages:

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SRAM burns power. Copyright 2004 Prentice Hall PTR FPGA-Based System Design: Chapter 3to steal, disrupt configuration Possible bits.

Logic elements
Logic element includes combinational function + register(s). Use SRAM as lookup table for combinational function.
inputs

LUT-based logic element

n

Lookup table configuration bits

1 out

Can multiplex at output or address at input

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Example
111

Evaluation of SRAM-based LUT

1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1 0

0 1

N-input LUT can handle function of 2n inputs. All logic functions take the same amount of space. All functions have the same delay. SRAM is larger than static gate equivalent of function. Burns power at idle. Want to selectively add register to LE:

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Registers in logic elements

Other LE features
Multiple logic functions in an LE. Addition logic:

Register may be selected into the circuit:

Configuration bit

carry chain.
LE out

LUT
D Q

Partitioned lookup tables.

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COUT

Xilinx Spartan-II CLB

Each CLB has two identical slices. Slice has two logic cells:

F5IN G4 G3 G2 G1 lookup table

YB Y carry/ control logic D Q YQ

BY SR F4 F3 F2 F1 lookup table carry/ control logic D Q YB Y YQ

LUT. Carry logic. Registers.

BX CE CLK
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CIN

Spartan-II CLB details

Spartan-II CLB operation

Each lookup table can be used as a 16-bit synchronous RAM or 16-bit shift register. Arithmetic logic includes an XOR gate. Each slice includes a mux to ocmbine the results of the two functino generators in the slice. Register can be configured as DFF or latch. Has three-state drivers (BUFTs) for on-chip busses.
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Arithmetic:
Carry block includes XOR gate. Use LUT for carry, XOR for sum.

Each slice uses F5 mux to combine results of multiplexers. F6 mux combines outputs of F5 muxes. Registers can be FF/latch; clock and clock enable. Includes three-state output for on-chip bus.
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FPGA-Based System Design: Chapter 3

FPGA-Based System Design: Chapter 3

Altera APEX II logic element

Each logic array block has 10 logic elements. Logic elements share some logic.

data1 data2 data3 data4 lookup table

carry in

cascade in

load

clear

carry chain

cascade chain

synchronous load/clear logic

labclr1 labclr2 chip reset labclk1 labclk2 labclkena1 labclkena2

asynchronous clear/preset/ load logic

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Apex II LE modes

APEX-II LE normal mode

Modes of operation:
Normal. Arithmetic. Counter.
carry in data1 data2 data3 data4 cascade in enable

4-input lookup table

out D Q out

cascade out

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FPGA-Based System Design: Chapter 3

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APEX-II LE arithmetic mode

carry in data1 data2 3-input lookup table 3-input lookup table out
D Q
data1

APEX-II LE counter mode

carry in synchronous load synchronous clear

cascade in

enable

cascade in

enable

out cascade out

data2

3-input lookup table

out D Q out

data3 3-input lookup table cascade out

carry out
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carry out
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APEX-II LE control logic

dedicated clocks fast global signals local interconnect

Programmable interconnect

MOS switch controlled by configuration bit:

D Q

local interconnect local interconnect

local interconnect
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Programmable vs. fixed interconnect

Switch adds delay. Transistor off-state is worse in advanced technologies. FPGA interconnect has extra length = added capacitance.

Interconnect strategies
Some wires will not be utilized. Congestion will not be same throughout chip. Types of wires:
Short wires: local LE connections. Global wires: long-distance, buffered communication. Special wires: clocks, etc.
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Paths in interconnect

Interconnect architecture
Connections from wiring channels to LEs. Connections between wires in the wiring channels.
Wiring channel

Connection may be long, complex:

Wiring channel LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE

Wiring channel

LE

LE

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FPGA-Based System Design: Chapter 3

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Interconnect richness

Segmented wiring

Within a channel:
How many wires. Length of segments. Connections from LE to channel.
Length 1 Length 2

Between channels:
Number of connections between channels. Channel structure.

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FPGA-Based System Design: Chapter 3

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Offset segments
channel

Switchbox

channel

channel

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channel

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Spartan-II interconnect

Spartan-II general-purpose network

Types of interconnect:
local; general-purpose; dedicated; I/O pin.

Provides majority of routing resources:

General routing matrix (GRM) connects horizontal/vertical channels and CLBs. Interconnect between adjacent GRMs. Hex lines connect GRM to GRMs six blocks away. 12 longlines span the chip.

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Spartan-II routing

Spartan-II three-state bus

Relationship between GRM, hex lines, and local interconnect:

Horizontal on-chip busses:

CLB

CLB

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Spartan-II clock distribution

clock pin clock rows clock rows

APEX II interconnect
row interconnect MegaLAB interconnect

row column
column interconnect local interconnect
LE LE

column interconnect

LE LE LE LE LE LE LE LE LE

LE LE

local interconnect

LE LE LE LE LE LE LE

clock rows clock spine

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Spartan-II I/O

Spartan-II I/O block diagram

Supports multiple I/O standards:

LVTTL, PCI, LVCMOS2, AGP2X, etc.

Provides registers. Programmable delay for pin-dependent hold time. Programmable weak keeper circuit.

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Configuration

Configuration ROM

Need to set all configuration SRAM bits:

minimum pin cost; reasonable speed.

Configured on start-up from ROM:

Configuration memory FPGA

Configuration can also be read back for testing.

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Spartan-II configuration

Scan chain
Scan chain: shift register used to access internal state. Logic-sensitive scan design (LSSD): scan structure that uses some hardware for normal mode and scan.

Configuration length depends on size of chip:

200,000 to 1.3 million bits.

Configuration modes:
Master serial for first chip in chain. Slave serial for follow-on chips. Slave parallel. Boundary-scan.
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FPGA-Based System Design: Chapter 3

FPGA-Based System Design: Chapter 3

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JTAG boundary scan

JTAG: Joint Test Action Group. Boundary scan:

Chip-on-board testing
Boundary scan decouples chips:

provide scan chain at pins; allow control of chip interior; decouple chip from rest of board for test.

board

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FPGA-Based System Design: Chapter 3

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Boundary scan concepts

TAP: test access port.

Requires three pins not shared with other logic. Test reset, test clock, test mode select, test data in, test data out.

TAP controller recognizes pins, controls boundary scan registers. Instruction register defines boundary scan mode.

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