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Sliding Mode Control of SMPS: Ms. A. Jonisha, Mrs. V. Devi Maheswaran

IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
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0% found this document useful (0 votes)
64 views11 pages

Sliding Mode Control of SMPS: Ms. A. Jonisha, Mrs. V. Devi Maheswaran

IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Copyright
© Attribution Non-Commercial (BY-NC)
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IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-ISSN: 2278-1676 Volume 4, Issue 5 (Jan. - Feb.

2013), PP 01-11 www.iosrjournals.org

Sliding Mode Control Of SMPS


Ms. A. Jonisha1, Mrs. V. Devi Maheswaran2
1 2

(Power Electronics and Drives, Rajalakshmi Engineering College, India) (Power Electronics and Drives, Rajalakshmi Engineering College, India)

Abstract: Digital control technique is a technique for high frequency switching mode power supply (SMPS).
Being widely used in the new generation portable systems, the regulation requirement for high frequency integrated DC-DC switching mode power supply becomes more and more demanding in industry, at very high frequency beyond 10 Mega Hertz range. Analysis and experimental study of buck converter is presented to achieve desired output voltage. The SMPS are emerging in terms of higher dynamic response performances, less output ripple, smaller size and weight. The sliding mode controller is associated with a digital pulse width modulation (DPWM) block to operate at high switching frequency. Sliding mode control (SMC) can reduce the voltage ripple voltage ripple of SMPS. Sliding mode controller will be used by means of analog to digital conversion (ADC) and Digital pulse width modulation (DPWM). Keywords-Analog to Digital converter(ADC), Digital pulse width modulation(DPWM), Sliding mode control

I.

INTRODUCTION

Switching mode power supplies provide high efficiency, easy integration small weight and dimension. SMPS used in the portable personal communication system, cell phones, telephones, MP3 players and the other PDA products, have grown explosively in recent years. They are also used in a various applications including computer systems, wireless communication systems, medical instrumentations, motor drives, lighting and consumer electronics. Especially the miniaturization is always a critical consideration for the portable devices. Even now in some portable application, the size of the DC-DC power converters is becoming the primary focus in the overall design. Therefore the technology for high switching frequency operation to reduce size of passive components like inductors and capacitors to obtain miniaturization is urgently needed. Advanced semiconductor integrated technology over the last decade has resulted in a noticeable reduction in the size and weight of electronic components.

II.

ANALOG SLIDING MODE CONTROL

SMPS has simplicity and low cost which are operated with analog controllers applications.The analog controlled SMPS operates as follows:The output voltage Vo and the reference voltage Vref are compared, and obtained the erreo signal e=Vref-Vo. The closed loop operation offers large performance in keeping the output voltage constant and restraining the overshoot during the input voltage or external load changes. The error signal constitutes the input of the controller. The controller can be realized by using an operational amplifier and the network of passive components such as capacitors and resistors. The output of the controller is the control signal is u. The pulse width modulator (PWM) is used to transform the control signal u. The analog components are sensitive to the environment influence, such as temperature, noise, tolerance of fabrication, which results in lack of flexibility, low reliability .It is difficult to apply sophisticated control algorithm with an analog approach implementation. In addition, to meet the size miniaturizations demand the high switching frequency is indispensable. However in higher switching frequency operation the analog controller signal transmission through the process will suffer from the limitation of band width and the large gain variation. The variability of the integration technology is more critical with higher switching frequency. The sliding surface is d S = K1 Vref Vo + K 2 V Vo + dt ref K 3 Vref Vo dt The control signal of the switched mode power supply with buck converter is + , > 0 , < 0 The control signal of the boost converter is Ueqn = Vc = k p1 ic + k p2 Vref Vo + (Vo Vs ) Where, = www.iosrjournals.org (1)

(2) (3)

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Sliding Mode Control Of SMPS


k p1 =
1 2

3 2

1 R1C

(4) (5)

k p2 = LC

III.

DIGITAL SLIDING MODE CONTROL

In order to reduce size and improve the system performance, the digital controllers are used. The digital controller consists of three blocks: analog to digital converter (ADC), digital control law and digital PWM (DPWM), and all these blocks should be integrated in one chip. In classical PWM control schemes, the control signal is compared to the ramp waveform to generate a discrete gate pulse signal. The advantage of PWM based SMC are that it does not need additional hardware circuitries since the switching function is performed by the PWM modulator, which can be implemented inside the digital controller. However in order to preserve the original sliding mode control laws, the practical implementation of PWM based SMC is nontrivial, when both current and voltage state variable are involved. The digital controller SMPS operates similarly as the analog controller as follows: The output voltage V o subtracted from the reference voltage Vref results in the voltage error. The ADC transfers the analog error to discrete in digital signals. During each switching period, the error value is sent to the control law block, where the controller makes algorithm calculation to regulate the output by new digital control duty of PWM ratio. Through the DPWM block, the digital duty value is converted into time analog signal to drive MOSFET switches.

.
Figure 1. Block diagram of Sliding mode control.

The algorithm of control law can be implemented with internal structure of logic circuits, without any external analog component. Thus the digital controller should be less sensitive to environment than analog counterpart. Also digital control law offers possibility to implement more sophisticated control strategies and other intelligent interface functions that are impractical in analog.

IV.

SIMULATION CIRCUITS OF CONVENTIONAL METHODS

The simulation circuits of the control techniques are simulated with the help of MATLAB/SIMULINK software. A. Open loop Buck Converter Fig.2 shows the circuit diagram of buck converter. It consists of MOSFET, inductance, DC source and load. The external triggering pulse is given to each MOSFET. This converter is used to decrease the output voltage. It converts high voltage DC supply to low voltage DC supply.

Figure 2. Simulation circuit diagram of open loop buck converter.

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Sliding Mode Control Of SMPS


B. Closed loop Buck Converter using Pulse Width Modulation Control The closed loop buck converter with pulse width modulation control is simulated with the output voltage and the reference voltage. These voltages are added. The error signal is produced, which is compared with the external repeating sequence. The compared pulse is given to the MOSFET switch. It controlled the buck converter of switched mode power supply.

Figure 3. Simulation circuit of closed loop buck converter using pulse width modulation

C. Closed loop buck converter with Sliding Mode Control The control circuit consists of a liner part; usually for simplicity it is represented with integrator and gain part; usually for simplicity it is represented with integrator and gain part. The second part is the non linear control. The non linear part represented by the hysterisis block could be implemented as the switch off and switch on points, here it is represented with current ripple.

Figure 4. Simulation circuit of closed loop buck converter with Sliding mode control.

D. Open loop boost converter Fig.5 shows the simulation circuit of open loop boost converter. It consists of MOSFET, inductance, DC source and load. The external triggering pulse is given to each MOSFET. This converter is used to increase the output voltage. It converts low voltage to high voltage. The output voltage is controlled by controlling the firing angle of the MOSFET.

Figure 5. Simulation circuit of open loop boost converter.

E. Closed loop boost converter with Pulse Width Modulation Control The closed loop boost converter with pulse width modulation control is simulated with the output voltage and the reference voltage. These voltages are added. The error signal is produced, which is compared with the www.iosrjournals.org 3 | Page

Sliding Mode Control Of SMPS


external repeating sequence. The compared pulse is given to the MOSFET switch. It controlled the boost converter of switched mode power supply.

Figure 6. Simulation circuit of closed loop boost converter using pulse width modulation.

F. Closed loop boost converter with Sliding Mode Control Using control voltage equation, the sliding mode controller for boost converter can be modeled as shown in fig.7. The pulse is generated and triggered the MOSFET.

Figure 7. Simulation circuit of boost converter with sliding mode control.

V.

SIMULATION CIRCUITS OF PROPOSED METHOD


M1 IRF140 L1 4.7u

The simulation circuit of the proposed method is simulated with the help of ORCAD PSPICE software.

V1 3
12

11 U17F 7404

U16E 10 7404

10 M2 C1 2u

IRF9133

13

U2 4 5 PWM0 PWM1 DPWM1 B0 B1 B2 1 2 3 1 2 3

U1 B0 B1 B2 ADC GND VO VREF 4 5 6

V17 TD = 0 TF = .1ns

0 PW = .5us
PER = 1us V1 = 0 TR = .1ns V2 = 1.5

Figure 8. Simulation circuit of Digital sliding mode control

The simulation circuit of the digital sliding mode control of switched mode power supply consists of analog to digital converter (ADC), control of switched mode power supply consists of analog to digital converter(ADC), control and digital pulse width modulation(DPWM). The analog to digital converter is a flash type analog to digital converter. The conversion involves quantization of the input, so it introduces a small amount of error. Instead of doing a single conversion, an ADC often performs the conversion of samples periodically. The result is a sequence of digital values that have converted continuous amplitude and continuous time analog signal to discrete amplitude and discrete time signal. The output voltage of the DC-DC converter and reference voltage are the input of the analog to digital converter gives three bit output they are B0, B1, B2.

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Sliding Mode Control Of SMPS


R1 30k R2 20k R3 20k R4 20k R5 20k R6 20k R7 20k R8

0
10k

Vo
+ -

+ +

S1 Sbreak

S2 Sbreak

S3 Sbreak

S4 Sbreak Vref

+ +

+ +

V2 5

10 R9

V3 5

R10 10

V4 5

R11 10

V5 5 R12 10

+ +

+ -

+ -

S5 Sbreak

S6 Sbreak

S7 Sbreak

V8 V6 5 R13 10 V7 5 R14 10 5

R15 10

0 0

U1A 1 3 2 7408 U3A 1 2 13 U4C 8 10 9 7402 B0 11 13 12 U5B 7402 3 4 7404 U4D 7427 U5A 12 1 2 7404 B2

U5D 9 8 7404 U5C 5 6 7404 9 8 10 U4A 7408 2 1 3 7402 B1 U2C 4 5

U2B 6 3 4 5 7427 4 6 7402 U3B 6

7408 U4B 5

B0 B1 B2

Figure 9. Simulation circuit of analog to digital converter

In classical PWM control schemes, the control signal is compared to the ramp waveform to generate a discrete gate pulse signal. The advantages of the PWM based SMC are that it does not need a additional hardware circuits. A high resolution, high frequency digital pulse width modulator (DPWM) can be constructed using a fast clocked counter and digital comparator. To achieve n bit resolution at the switching frequency Fs takes the digital value d of the duty ratio and produces the pulsating waveform that controls the power MOSFETs in the power converter. The inputs of the ADC are sensed output voltage and the reference voltage and the outputs are 3 bit digital output the ADC having encoder part to converter the 8 bit analog signal to digital signal. The DPWM having digital circuits like flip flops, multiplexers, digital compactors. The switching pulse generated by these digital pulse width modulators. The pulse is given to the switching voltage of the MOSFETs.
OFFTIME = .5uSDSTM1 ONTIME = .5uS CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1 U1A 23 2 C 5 3 D1 Q1 4 22 D2 Q2 19 D3 Q3 21 20 D4 Q4 74100 Q1 V5 V1 = 0 V2 = 5 V4 TD = .015us TR = .1ns TF = .1ns PW = .5us 0 PER = 1us U8 14 2 A B 1 6 1G 5 1C0 7 4 1C1 1Y 3 1C2 1C3 15 10 2G 11 2C0 9 12 2C1 2Y 13 2C2 2C3 74F153 U5A 1 3 A QA 4 QB 5 QC 6 QD
CLR 2

U11A 2 1 V6 5 7404

V1 = 0 V2 = 5 TD = 0 TR = .1ns TF = .1ns PW = .5us PER = 1us

V2 V3 V1 = 0 V2 = 5 TD = .01us TR = .1ns TF = .1ns V1 = 0 0= 5 PW = .5us V2 PER = 1us TD = .05us TR = .1ns TF = .1ns PW = .5us PER = 1us

74LS393

LO

DSTM7

S1

1 15 14 13 11 12 9 10 2 3 4

U7 B3 A3 B2 A2 7 B1 A<B 6 A1 A=B 5 B0 A>B A0 A<B_IN A=B_IN A>B_IN 7485 Q4

Q2 Q3

DSTM6

1 15 14 13 11 12 9 10 2 3 4

U6 B3 A3 B2 A2 7 B1 A<B 6 A1 A=B 5 B0 A>B A0 A<B_IN A=B_IN A>B_IN 7485

S1

U9A 1 3 2 74ALS08 U10B 4 6 5 OFFTIME = .5uSDSTM8 ONTIME = .5uS CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1 V1 = 0 V2 = 5 TD = 0 TR = .1ns TF = .1ns PW = .5us PER = 1us V7 U12A 23 2 C 5 pwm0 3 D1 Q1 4 22 D2 Q2 19 21 D3 Q3 20 pwm2 D4 Q4 74100

OFFTIME = .5uSDSTM4 ONTIME = .5uS CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1

pwm0 pwm2

OFFTIME = .5uSDSTM5 ONTIME = .5uS CLK DELAY = 0 STARTVAL = 0 OPPVAL = 1

74ALS08

V1 = 0 V2 = 5 TD = .02us TR = .1ns TF = .1ns PW = .5us PER = 1us

V8

B2 B0 B1

Figure 10. Simulation circuit of digital pulse width modulator.

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Sliding Mode Control Of SMPS VI.


SIMULATION RESULTS

The simulation results of conventional techniques and digital sliding mode control of buck converter shows the result of output voltage and the output current. The simulation results of boost converter control techniques also shown. A. Open loop buck converter Fig.11 depicts the input dc source of magnitude 3V. This voltage is fed to the buck converter, reduce the input source voltage into 1.4V.

Figure 11. Simulation result of open loop buck converter.

B. Closed loop Buck Converter with Pulse Width Modulation Control Fig.12 depicts the input dc source of magnitude 3V. This voltage is fed to the buck converter, reduces the input source voltage. The output waveforms of output voltage, output current depends the pulse width in PWM control.
Output Current(A)

0.2 0.1 0 0 1 Time (sec) 2 x 10


-4

Output Voltage (V)

3 2 1 0 0 1 Time (sec) 2 x 10
-4

Switching Pulse

1 0.5 0

1 Time (sec)

2 x 10
-4

Figure 12. Closed loop buck converter with Pulse width modulation

Fig.13 depicts the input dc source of magnitude 3V. This voltage fed to the buck converter, which reduce the input source voltage. The ripple of the circuit is 0.3V

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Sliding Mode Control Of SMPS

Figure 13. Simulation result of closed loop buck converter with pulse width modulation

C. Closed loop buck converter with Sliding Mode Control Fig.14 depicts the input dc source of magnitude 3V. This voltage feed to the buck converter, reduce the input source voltage. The overshoot also reduced.
Inductance current(A)

0.4 0.2 0 0.2 0.1 0 2 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Vo ( V ) Switching Pulse

Io (A)

1 0 1 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

0.5 0 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 Time (sec)

Figure 14. Closed loop buck converter with sliding mode control

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Sliding Mode Control Of SMPS


Fig.15 depicts the input dc source of magnitude 3V. This voltage feed to the buck converter, which reduce the input source voltage. The ripple voltage is 0.01V

Figure 15. Simulation result of closed loop buck converter with sliding mode control

D. Open loop boost converter Fig.16 depicts the input dc source of magnitude 24V. This voltage fed to the boost converter, which increase the input source voltage to 47.15V.

Figure 16. Simulation result of open loop boost converter.

E. Closed loop boost converter with Pulse Width Modulation Control Fig.17 depicts the input dc source of magnitude 24V. This voltage fed to the boost converter, which increase the input source voltage.

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Sliding Mode Control Of SMPS


Output Current(A)

Output Current 0.2 0.1 0 0 0.01 0.02 0.03 0.04 0.05 0.06 Time(sec) 0.07 0.08 0.09 0.1

Output Voltage(V)

40 20 0 0 0.01 0.02 0.03 0.04 0.05 0.06 Time(sec) 0.07 0.08 0.09 0.1

Switching Pullse

1 0.5 0 0 0.01 0.02 0.03 0.04 0.05 Time 0.06 0.07 0.08 0.09 0.1

Figure 17. Closed loop boost converter with pulse width modulation.

Fig.18 depicts the input dc source of magnitude 24V. This voltage fed to the boost converter increase the voltage to 29.8V. The ripple voltage of the boost converter is 0.5V

Figure 18. Simulatiion result of closed loop boost converter with pulse with modulation

F. Closed loop boost converter with Sliding Mode Control Fig.19 depicts the input dc source of magnitude 24V. This voltage is fed to the boost converter increase the input source voltage. The output waveforms of output voltage, depends the sliding mode

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Sliding Mode Control Of SMPS


Switching Pulse

1 0.5 0

0.05

0.1

0.15

0.2

0.25

0.3

Capacitor current(A)

5 2 0 0 0.05 0.1 0.15 0.2 0.25 0.3

Output Voltage(V)

50 40 20 0 0 0.05 0.1 0.15 Time 0.2 0.25 0.3

Figure 19. Closed loop boost converter with sliding mode control.

Fig.20 depicts the input dc source of magnitude 24V. This voltage fed to the boost converter. The output voltage increased to 30.4V. The output ripple voltage is 0.1V

Figure 20. Simulation result of closed loop boost converter with sliding mode control

G. Simulation circuit result of the proposed method:Digital Sliding Mode Control Fig.21 depicts the input dc source of magnitude 3V. This voltage fed to the buck converter, reduce the input source voltage. The output waveforms of output voltage is reduced to 1.36V with very low ripple voltage 0.2mV.

Figure 21. Simulation result of Digital sliding mode control.

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Sliding Mode Control Of SMPS VII.


CONCLUSION

The simulation circuit of sliding mode control and PWM control of SMPS was explained. Simultaneous output voltage, output current and ripple voltage were observed with respect to input. Table I shows the comparsion of output voltage, output currenta and the ripple voltage of control techniques.

TABLE I. OUTPUT COMPARISON OF CONTROL TECHNIQUES


Converter Control Technique Input Voltage (V) 3 3 Output Current (A) 0.18 0.15 Output Voltage (V) 1.8 1.505 Ripple Voltage (V) 0.3 0.01

Buck Converter

Boost Converter

PWM control Sliding mode control Digital Sliding mode control PWM control Sliding mode control

0.11

1.36

0.0002

24 24

0.125 0.126

29.5 30.4

0.5 0.1

REFERENCES
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[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] B. Patella, A. Prodic, A. Zirger, and D. Maksimovic, High -frequencydigital PWM controller IC for DC-DC converters, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 438 446, January 2003. J. Xiao, A. Peterchev, J. Zhang, and S. Sanders, An ultra -low-powerdigitally-controlled buck converter IC for cellular phone applications, in Proc. 19th Annu. IEEE Appl. Power Electron. Conf. Expo. (APEC 2004), vol. 1, pp. 383391. Z. Lukic, N. Rahman, and A. Prodic, Multibit PWM digital controller IC for DCDC converters operating at switching frequencies beyond 10 MHz, IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1693 1707, September 2007. A. Peterchev and S. Sanders, Quantization resolution and limit cyclingin digitally controlled PWM converters, IEEE Trans. Power Electron.,vol. 18, no. 1, pp. 301 308, January 2003. M. Batarseh, W. Al Hoor, L. Huang, C. Iannello, and I. Batarseh, Segmented digital clock manager -FPGA based digital pulse width modulator technique, in Proc. 39th IEEE Annu. Power Electron. Spec. Conf. (PESC 2008), June, pp. 30363042. C. Coleman and D. Godbole, A comparison of robustness: Fuzzy logic,PID, and sliding mode control, in Proc. 3rd IEEE Conf. World Congr.Comput. Intell., June 1994, vol. 3, pp. 1654 1659. S. Tan, Y. Lai, and C. Tse, General design issues of sliding -mode controllers in DCDC converters, IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 1160 1174, March 2008. V. Utkin, Sliding Mode and Their Applications in Variable Structure Systems. Moscow, Russia: Mir, 1978. M. Castilla, L. Vicuna, M. Lopez, O. Lopez, and J. Matas, On the designof sliding mode control schemes for quantum resonant converters, IEEETrans. Power Electron., vol. 15, no. 6, pp. 960973, November 2000. S. Tan, Y. Lai, and C. Tse, Indirect sliding mode control of power converters via double integral sliding surface, IEEE Trans. Power Electron.vol. 23, no. 2, pp. 600 611, March 2008. R. Ramos, D. Biel, E. Fossas, and F. Guinjoan , A fixed-frequency quasi sliding control algorithm: Application to power inverters design by meansof FPGA implementation, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 344355, January 2003. J. Ackermann and V. Utkin, Slidingmode control design based on Ackermanns formula, IEEE Trans. Autom.Control, vol. 43, no. 2, pp. 234237, June 1998. M. Norris, L. Marco, P. E. Alarcon, and D. Maksimovic, Quantizatio n noise shaping in digital PWM converters, in Proc. 39th IEEE Annu. Power Electron. Spec. Conf. (PESC 2008), June, pp. 127133. Vahid Yousefzadeh and Shamim Choudhury Nonlinear Digital PID Controller for DC -DC Converters Proceedings of 39th IEEE Conference, pp. 12311241,January 2008 Xiao J., Peterchev A., Zhang J. and Sanders S. An ult ra-low-power digitally- controlled buck converter IC for cellular phone applications Proceedings of 19th IEEE Conference vol. 1, pp. 383391,March 2004.

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