Combinational Logic Circuits
Combinational Logic Circuits
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 2.
A. C.
a c
B. D.
b d
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
3.
A.
B.
C.
D.
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
4.
For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the be LOW. What is the status of the Y output?
input
A. B. C. D.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
5.
For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the be HIGH. What is the status of the Y output?
input
A. B. C. D.
6.
Answer: Option A Convert BCD 0001 0010 0110 to binary. A. C. 1111110 1111000 B. D. 1111101 1111111
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 7.
A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are HIGH? A.
B.
C.
D.
Answer & Explanation
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
8.
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
9.
A. C.
a c
B. D.
b d
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
10. How many data select lines are required for selecting eight inputs?
A. C.
1 3
B. D.
2 4
Answer: Option C Explanation: No answer description available for this question. Let us discuss. 11. The simplest equation which implements the K-map shown below is:
A. B. C. D.
Answer & Explanation
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 12. How many 1-of-16 decoders are required for decoding a 7-bit binary number? A. C. 5 7 B. D. 6 8
Answer: Option D
Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
13. Which of the following logic expressions represents the logic diagram shown?
A. B. C. D.
Answer & Explanation
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
14. The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.) A. C. AND/OR NOR B. D. NAND OR/AND
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
15. Which of the following statements accurately represents the two BEST methods of logic circuit simplification? A. B. C. D. Boolean algebra and Karnaugh mapping Karnaugh mapping and circuit waveform analysis Actual circuit trial and error evaluation and waveform analysis Boolean algebra and actual circuit trial and error evaluation
Answer: Option A Explanation: No answer description available for this qu 16. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs?
A. B.
C.
All but
are LOW.
D.
All but
are HIGH.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
17. Which of the following combinations cannot be combined into K-map groups? A. B. C. D. Corners in the same row Corners in the same column Diagonal corners Overlapping combinations
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
18. As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem. A. B. C. D. A defective IC chip that is drawing excessive current from the power supply A solar bridge between the inputs on the first IC chip on the board An open input on the first IC chip on the board A defective output IC chip that has an internal open to Vcc
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
19. Which gate is best used as a basic comparator? A. C. NOR Exclusive-OR B. D. OR AND
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
A. B. C. D.
Answer: Option C Explanation: 21. In VHDL, macrofunctions is/are: A. B. C. D. digital circuits. analog circuits. a set of bit vectors. preprogrammed TTL devices.
No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 22. Which of the following expressions is in the product-of-sums form? A. B. C. D. (A + B)(C + D) (AB)(CD) AB(CD) AB + CD
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
23. Which of the following is an important feature of the sum-of-products form of expressions? A. B. C. All logic circuits are reduced to nothing more than simple AND and OR operations. The delay times are greatly reduced over other forms. No signal must pass through more than two gates, not including inverters. The maximum number of gates that any signal must pass through is reduced by a factor of two.
D.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
24. For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW. What is the status of the outputs?
A. B.
C.
All but
are LOW.
D.
All but
are HIGH.
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
25. An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem? A. B. C. D. Current tracer Logic probe Oscilloscope Logic analyzer
Answer: Option A Explanation: 26. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? A. A > B = 1, A < B = 0, A < B = 1
B. C. D.
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 27. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong? A. The output of the gate appears to be open. The dim indication on the logic probe indicates that the supply voltage is probably low. The dim indication is a result of a bad ground connection on the logic probe. The gate may be a tristate device.
B.
C. D.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
28. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output? A. B. C. D.
4 3 2 1
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
29. Each "1" entry in a K-map square represents: A. B. C. D. a HIGH for each input truth table condition that produces a HIGH output. a HIGH output on the truth table for all LOW input combinations. a LOW output for all possible HIGH input conditions. a DON'T CARE condition for all possible input truth table combinations.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
30. Looping on a K-map always results in the elimination of: A. B. variables within the loop that appear only in their complemented form. variables that remain unchanged within the loop. variables within the loop that appear in both complemented and uncomplemented form. variables within the loop that appear only in their uncomplemented form.
C.
D.
Answer: Option C 31. What will a design engineer do after he/she is satisfied that the design will work? A. B. Put it in a flow chart Program a chip and test it
C. D.
Give the design to a technician to verify the design Perform a vector test
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 32. Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?
A.
The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the technician to the problem. The output appears to be shorted to Vcc, but is being pulsed by the pulser. The output appears to be LOW, but is being pulsed by the pulser. Nothing appears to be wrong at that point.
B. C. D.
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
A. B. C.
Only the output of the defective gate is affected. There is a signal loss to all gates on the node. The affected node will be stuck in the LOW state. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.
D.
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
34. In HDL, LITERALS is/are: A. B. C. D. digital systems. scalars. binary coded decimals. a numbering system.
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
35. Which of the following expressions is in the sum-of-products form? A. B. C. D. (A + B)(C + D) (AB)(CD) AB(CD) AB + CD
C.
D.
Answer & Explanation
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 37. Which of the K-maps given below represents the expression X = AC + BC + B?
A. C.
a c
B. D.
b d
No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
38. A decoder can be used as a demultiplexer by ________. A. B. C. D. tying all enable pins LOW tying all data-select lines LOW tying all data-select lines HIGH using the input lines for data selection and an enable line for data input
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
39. How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010? A. C. 1 3 B. D. 2 4
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
40. Which statement below best describes a Karnaugh map? A. B. C. D. A Karnaugh map can be used to replace Boolean rules. The Karnaugh map eliminates the need for using NAND and NOR gates. Variable complements can be eliminated by using Karnaugh maps. Karnaugh maps provide a visual approach to simplifying Boolean expressions.
Answer: Option D Explanation: 41. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?
A. C.
a c
B. D.
b d
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 42. A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001? A. B. C. D. 0 3 9 None. All outputs are HIGH.
Answer: Option C
Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
A. B. C. D.
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
44. A full-adder has a Cin = 0. What are the sum ( A. B. C. D. = 0, Cout = 0 = 0, Cout = 1 = 1, Cout = 0 = 1, Cout = 1
Answer: Option B Explanation: No answer description available for this question. Let us discuss.
45. What type of logic circuit is represented by the figure shown below?
A. C.
XOR XAND
B. D.
XNOR XNAND
Answer: Option B Explanation: 46. The device shown here is most likely a ________.
A. B. C. D.
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 47. The design concept of using building blocks of circuits in a PLD program is called a(n):
A. B. C. D.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
48. When adding an even parity bit to the code 110010, the result is ________. A. C. 1110010 110010 B. D. 1111001 001101
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
49. Which of the following combinations of logic gates can decode binary 1101? A. B. C. D. One 4-input AND gate One 4-input AND gate, one OR gate One 4-input NAND gate, one inverter One 4-input AND gate, one inverter
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50. What is the indication of a short to ground in the output of a driving gate? A. B. C. D. Only the output of the defective gate is affected. There is a signal loss to all load gates. The node may be stuck in either the HIGH or the LOW state. The affected node will be stuck in the HIGH state.
Answer: Option B How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have? A. C. 3 5 B. D. 4 6
Answer & Explanation Answer: Option B Explanation: No answer description available for this question. Let us discuss.