Unit - Iii 3.0) Introduction: Digital Logic and Computer Organization
Unit - Iii 3.0) Introduction: Digital Logic and Computer Organization
0) Introduction
A microcomputer performs a task by reading and executing the set of instructions written in its memory. This set of instructions, written in a sequence, is called a program. Each instruction in the program is a command, in binary, to the microprocessor to perform an operation. This chapter explains in detail the basic instructions, their operations and addressing modes.
3.1) Objectives
In this Unit you will learn about: Introduction Computer Internals Types of Instructions Classification of Instructions Looping and Counting Interconnection of Units Internal working of CPU. Modes of Addressing Stacks and Queues Subroutines Parameter Passing
3.2.2. Registers
Besides the primary memory, the CPU has other special storage locations called the Registers. Registers may be defined as special purpose temporary storage locations in the CPU, which are distinct from the primary memory. Even though the primary memory storage locations and the registers of the CPU are both used for storing data or program instructions and are designed with the same elements of circuits, they are quite distinct from one another by usage. The primary memory locations
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Figure 5.1: General Registers Floating-Point Registers Register %st %st(0) - %st(7) Segment Register Register Description %cs code segment register %ss stack segment register %ds data segment register %es data segment register (string operation destination segment) %fs data segment register %gs data segment register
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10001001
An instruction word normally stores one program instruction in machine language. Instructions in machine language are generally micro instructions as against the instruction in a high level language which are macro instructions. A macro instruction is a complex instruction which has to be broken down to several simple instructions of machine language. For instance, an instruction such as A = B+C 2 in a High Level Language will result in the following set of simple instructions in machine language. Clear the accumulator and add C Multiply the contents of the accumulator by C Add B to the contents of the accumulator = CLA C = MUL C = ADD B
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The number of bits in these two parts will be decided by the number of distinct instruction that the computer is expected to execute and the memory size of the computer. Suppose the instruction word of a machine is 32-bits long. Of these let 6 bits be allocated for the op-code and 26 bits for the operand address. Since the op-code has 6 bits it can represent 26=64 distinct combinations. Therefore, if each combination represents an instruction, the machine is capable of performing 64 instructions. The address part has 26 bits and therefore, the memory size can be atmost 226=216K words. If op-code is allocated a bit less and is allocated a bit more to the address part, then The no. of possible instructions Maximum memory size possible = 25 = 32 = 227 = 217 K words
The number of instructions that the computer is capable of executing is halved, while the maximum possible memory size is doubled. Both these can be simultaneously increased or decreased by increasing or decreasing the word size. The optimal values of the word size, the op-code size and the operand address size are decided at the time of designing the computer.
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The first two addresses give the addresses of the two operands on which the binary operation is to be done. The third address is the address where the result of the operation is to be stored. The fourth address gives the address of the memory word which contains the next instruction.
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Address 1 and 2 will give the addresses of a and b respectively. Address 3 will be the address of c while address 4 will be the address of the next instruction. The op-code will contain the code for addition. All the address fields may not be always used. Even though bigger instructions can be represented with this format, the 4-address instruction is not popular because of the following reasons: The execution of these instructions is very slow The word length is divided among five fields thus making each short. This is turn restricts the accessible memory size of the computer. The word size cannot be arbitrarily increased without adding other constraints in the design of a computer. The Three address instruction In this format, the op-code is followed by three addresses, the two operand addresses and the address where the result of the operation is to be stored. The address of the next instruction is not given. Then how does the computer know where to find the next instruction? Instructions are kept sequentially in adjacent memory locations and they are taken up one after the other automatically. OP-CODE ADD Add 1 A Add 2 B Add 3 C
The three address instruction format is only a small improvement over the four address format and suffers from all the drawbacks of the four address format. The Two address instruction In this type of instruction format, both the operand addresses are not given. One of the operands is made available on a register called the accumulator and its address is therefore not required. The operation code, the address of one operand and the address of the result are given. OP-CODE ADD Address of A A Address of C C
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The addresses of the operands as well as the locations where the results are to be stored are available in a stack in memory. These are of course special types of instruction and find use in special procedures in machine language programs. 3.2.5. Classification of Instructions For the convenience of programmers, the 8085 instructions have been classified into the following five groups:
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The term copy is equally valid for input/output functions because the contents of the source are not altered. However, the term data transfer is used so commonly to indicate the data copy function. Apart from data copy instructions, the following machine control operations are also used in programs. HLT NOP : : Halt No operation Stop processing and wait. Do not perform any operation.
The following example illustrates various operations. Instructions. The data transfer instructions copy data from a source into a destination without modifying the contents of the source. The previous contents of the destination are replaced by the contents of the source. Opcode MOV Operand Rd, Rs Description Move This is a 1-byte instruction Copies data from source register Rs to destination register Rd Move Immediate
MVI
Rd, 8-bit
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IN in the
NOP
substitute
The first instruction is a 2-byte instruction that loads the accumulator with the data byte 82H and the second instruction MOV B, A copies the contents of the accumulator in register B without changing the contents of the accumulator.
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These arithmetic operations are performed in relation to the contents of the accumulator. However, the Increment or the Decrement operations can be performed in any register. Addition The microprocessor performs addition with 8-bit binary numbers and stores the sum in the accumulator. If the sum is larger than eight bits (FFH), it sets the Carry flag. Addition can be performed either by adding the contents of a source register (B, C, D, E, H, L or memory) to the contents of the accumulator (ADD) or by adding the second byte directly to the contents of the accumulator (ADI). Subtraction The microprocessor performs subtraction by using the method of 2's complement. Subtraction can be performed either by using the instruction SUB to subtract the contents of a source register or the instruction SUI to subtract an 8-bit number from the contents of the accumulator. In either case, the accumulator contents are regarded as the minuend (the number from which to subtract). The microprocessor performs the following steps internally to execute the instruction SUB (or SUI). Step 1: Converts subtrahend (the number to be subtracted) into its 1's complement. Step 2: Adds 1 to 1's complement to obtain 2's complement of the subtrahend. Step 3: Adds 2's complement to the minuend (the contents of the accumulator). Step 4: Complements the Carry flag. These steps are illustrated in the following example. Features Of Arithmetic Operations The arithmetic operations implicitly assume that the contents of the accumulator are one of the operands. The results of the arithmetic operations are stored in the accumulator; thus the previous contents of the accumulator are altered. The flags are modified to reflect the data conditions of an operation. The contents of a register are not changed as a result of an arithmetic operation Page 88
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Figure 5.2: (a) AND Gate (b) Simulated ANA Instruction Figure 5.2(b) shows that each bit of register B is independently ANDed with each bit of the accumulator, thus simulating eight 2-input AND gates. To simulate one 2-input AND gate, all other bits can be masked or eliminated, as illustrated in the next program. OR, Exclusive-OR and NOT The instructions ORA (and ORI) simulates logic ORing with eight 2-input OR gates; this process is similar to that of ANDing, explained in the previous section. The instruction XRA (and XRI) performs Exclusive-ORing of eight bits and the instruction CMA inverts the bit of the accumulator. Example Assume register B holds 93H and the accumulator holds 15H. Illustrate the results of the instructions ORA B, XRA B and CMA The instruction ORA B will perform the following operation: (B) OR (A) = 0 0 0 1 0 1 0 1 ___________________________ (A) = 1 0 0 1 0 1 1 1 Page 91 (15H) (97H) = 1 0 0 1 0 0 1 1 (93H)
The result 86H will be placed in the accumulator and the flags will be modified as
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Note the sequence of the machine code. The 16-bit memory address of the jump location is entered in the reverse order, the low-order byte (00H) first followed by the high-order byte (20H). The microprocessor is designed for such a reverse sequence. The jump location can also be specified using a label. While writing a program, the exact memory location to which a program sequence should be directed may not be known. In that case, the memory address can be specified with a label (or a name). This is particularly useful and necessary for an assembler. However, both a label and its 16-bit address should not be specified in a Jump instruction. Furthermore, the same label cannot be used for different memory locations. Page 93
All the Jump instructions are listed here for an overview. The Zero and Carry flags and related Jump instructions are used frequently. They are illustrated in the following examples.
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Figure 5.4: Flowcharts to Indicate Number of Repetitions Completed 3.2.6. Interconnection of Units As all data to be processed by a computer has to be stored in memory, the characteristics of the interconnection paths are determined by the memory structure. In order to achieve reasonable speed, all the bits in a word are transmitted simultaneously. A set of wires, which carries a group of bits in parallel and has an associated control scheme is known as a bus. A bus, which carries a word to or from memory is known as a data bus. Its width will equal the word length (in bits) of the memory. In order to retrieve a word from memory it is necessary to specify its address. A Memory address bus whose width equals the number of bits in the MAR of the memory carries the address. Thus if a computers memory has 64KB, 32 bit words, then the data bus will be 32 bits wide and the address bus 16 bits wide. Besides buses to carry address and data, control signals are needed between the units of a computer. For instance, if a command to I-O units is to be sent, a control bus carries suchDAB signals. A system bus will thus MAB consist of a data bus, a memory address bus and a control bus. Figure 5.4 shows the processor memory interconnection.
DB
DB
Communication
CB
MEMORY
DAB DB
Bus
CB MAB
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MEMORY
MAB
CB
DB DAB
DC and DB
PROCESSOR REGISTER
CB
DATA REGISTER DB
MAB DB DAB CB DC
- Memory Address Bus - Data Bus - Device Address Bus - Control Bus - Device Control
Figure 5.6: Interface unit Interrupt Structures An interrupt signal is a signal sent by an I-O interface to the processor when the I-O is ready to send or receive data to or from memory. The processor completes the instruction it is processing and acknowledges the interrupt signal. It then preserves the information needed to resume the program it was executing and jumps to another program called an interrupt service routine to cater to the I-O read/write requirement. An interrupt servicing procedure consists of the following steps: Step 1: An interrupt signal is received by the processor. Step 2: The processor completes the present instruction being executed. Step 3: The processor stores the contents of the program counter and other register in the processor in a reserved area in memory. This information is required to enable the processor to resume the program it was executing. Step 4: The processor sends an interrupt acknowledge signal to the interrupting Page 99
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Figure 5.7: Fetch Cycle The Execute Cycle During this cycle, the instruction found in the CIR is interpreted and executed by the control unit. The following operations are involved in an execute cycle: The control unit moves the operand address from the instruction word and passes it on to the decoder. The decoder interprets the address (The address is not at all given directly in an instruction.) and puts the address of the operand on the MAR. The data from this address as given by MAR is fetched and moved to the MDR (if necessary). The control unit simultaneously interprets the op-code part of the instruction and the necessary operations is done by moving (if necessary) the data from the MDR to the accumulator.
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Instruction ADD A is kept in the location 512. A is the location 1326 and contains the value 5.3 in it. The following steps will be involved in the fetch cycle of executing this instruction. The address 512 will be available on the PC. This is passed to the MAR. The address 512 as given by MAR is accessed and the instruction ADD A is copied on MDR. The instruction ADD A from MDR is moved to the CIR. The PC is incremented to 513. During the Execute cycle, the following are done: The instruction in the CIR is interpreted. The operand address A is passed through the decoder to the MAR (1326 is written on MAR). The control unit looks into the MAR and fetches the address 1326 (of A) found in it. The data value 5.3 is moved from this location 1326 and written on the MDR. The op-code of the instruction ADD is interpreted and accordingly the value 5.3 from MDR is moved to the accumulator. The value 5.3 is added to the previous contents of the accumulator and the result left in it. Example Instruction STO is in the location 513 where C is the location 1046. During the fetch cycle The PC address 513 is written on the MAR. The MAR address 513 is fetched. The instruction STO C found in 513 is copied on the MDR. The instruction is moved to the CIR from the MDR. The PC is incremented to 514. During the Execute cycle The instruction in CIR is interpreted. The operand address 1046 of C is put on MAR through the decoder. The op-code is interpreted and the contents of the accumulator moved to MDR. The data given by MDR is written into the address given by MAR. 3.2.7. Modes of Addressing The manner in which the operand addresses are given in the address part of an instruction word is known as addressing.
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This instruction is ADD A. The address 1195 of A is given in binary in the address part of the instruction word. The control unit fetches the data from this location and adds it to the accumulator. Direct addressing is the simplest and the fastest to execute among the various types of addressing. But it suffers from some of the drawbacks discussed earlier. A memory, larger than that permitted by the word size cannot be accessed by this mode of addressing. Extended Addressing When more than one word is used for an instruction, it is known as extended addressing. When two words are used instead of the one 16-bit word shown in direct addressing, a 32bit instruction word results. Then a much longer memory can be easily accessed. The disadvantage is that, due to certain practical reasons, however, extended mode of addressing is not considered a viable alternative to direct addressing. Indirect Addressing In this method of addressing, the address part of the instruction word does not directly give the address where the operand is kept. Instead, it gives the address of another location, which in turn gives the address of the operand. For example, let the operand A(value 13.4) be in the location 1195. This address 1195 will not be given in the
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1195
ADD
43 -13.4
1195
The advantage in this approach is that the number of bits available for the operand address is equal to 1 word (number of bits in the op-code). Hence, if the word size is 16 bits and op-code 5 bits, the address part can have 11 bits only. When a different location is used for giving the operand address, the full word of 16 bits is available for giving the address. Hence these sixteen bits can access a bigger memory of 216 K. Direct accessing can access a memory of only 211 words. This means that indirect addressing can access a memory 32 times bigger. Thus, indirect addressing mode provides for a much larger memory size for the same word length. At the same time, it is not achieved at no loss. The fetchexecute cycle will be longer, as each accessing actually involves accessing two memory locations. The overall processing time will therefore be much longer. To put it simply, such computer will be a slower machine. Most computer architecture permit both direct and indirect addressing. Then how does the control unit understand whether the addressing is in direct or indirect mode? The first bit (or the leftmost bit or the most significant bit) of the address part of the instruction word is used for indicating the mode of addressing. When this bit is 0, it means that the addressing is direct, when it is 1, it implies that the address following it is in the indirect mode. Indexed Addressing In this method also the address part of the instruction does not directly give the operand address. Instead, the contents of this part are added to the contents of another register called the index register. Thus, large numbers are obtained which permits the accessing of a bigger memory. However, the contents of the index register have to be first determined and loaded through appropriate instruction. It is a more complex process and also slows down the execution of the instruction.
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Op-code
operand address
As in indirect addressing, the first bit of the address part is reserved for indicating the mode of addressing. This bit is called the index bit. When it stores a 1 it indicates indexed addressing. When it stores a 0 the addressing is direct. Indexed addressing can be combined with indirect addressing, that is, we may have direct indexed addressing or indirect indexed addressing. Immediate Addressing When the value of the operand instead of the address where it is located, is given in the instruction, the mode of addressing is called immediate. ADD -13.4
The above instruction will instruct the control unit to add -13.4 to the accumulator. This is a very simple method of addressing, as data are readily available on the instruction word itself. However, the number of bits available for the data is more or less than a full word and hence only smaller value can be handled. Moreover, it is not always possible to know the value of the data at the time of writing the instructions. This method of addressing cannot, therefore, be adopted everywhere. Addressing modes are the ways how architectures specify the address of an object they want to access. An addressing mode can specify a constant, a register or a location in memory.
Addressing modes Register Immediate Displacement Register deffered Indexed Direct Memory deferred Autoincrement Example Instruction Add R4,R3 Add R4, #3 Meaning R4 <- R4 + R3 R4 <- R4 + 3 When used When a value is in a register For constants Accessing local variables Accessing using a pointer or a computed address Useful in array addressing: R1 - base of array R2 - index amount Useful in accessing static data If R3 is the address of a pointer p, then mode yields *p Useful for stepping through arrays in a loop. R2 - start of array d - size of an element
Add R4, 100(R1) R4 <- R4 + M[100+R1] Add R4,(R1) Add R3, (R1 + R2) R4 <- R4 + M[R1] R3 <- R3 + M[R1+R2]
Add R1, (1001) R1 <- R1 + M[1001] Add R1, @(R3) R1 <- R1 + M[M[R3]] Add R1, (R2)+ R1 <- R1 +M[R2] R2 <- R2 + d
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Add R1,-(R2)
Notation: <- - assignment, M - the name for memory, M[R1] refers to contents of memory location whose address is given by the contents of R1. Table 5.1: The most common names for addressing modes Encoding of Addressing Modes How the addressing modes of operands are encoded depends on: the range of addressing modes. the degree of independence between opcodes and modes. For small number of addressing modes or opcode/addressing mode combinations, the addressing mode can be encoded in opcode. For a larger number of combinations, typically a separate address specifier is needed for each operand. The architect has to balance several competing forces when encoding the instruction set: The desire to have as many registers and addressing modes as possible. The impact of the size of the register and addressing mode fields on the average instruction size and hence on the average program size. 3.2.8. Stacks and Queues A stack is a storage device that stores and retrieves information using Last In First Out (LIFO) concept. The stack in digital computers is a memory unit with an address registers, that can count only after loading a initial value. The register that holds the address of the stack is called the stack pointer (SP). The two operations of a stack are PUSH for insertion and POP for deletion. As the items in the stack are inserted the stack pointer is incremented and when the items are retrieved, the stack pointer is decremented. The following figure shows the 64 word register stack. The stack pointer SP is currently pointing to the 3rd element. Removing the item, decrements the stack pointer. The data register DR holds the binary data to be written into or read from the stack. The stack during insertion is checked if it is full and during retrieval of items is checked if it is empty.
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63
SP
3 2 1 0
DR
Figure 5.9: Block diagram of a 64-word Stack Memory Stack A stack can be implemented in a random-access memory attached to the CPU. The implementation of stack in the CPU is done by assigning a portion of memory to a stack operation and using processor register as a stack pointer. The following figure shows a portion of the computer memory partitioned into three segments namely program, data and stack. The program counter points at the address of the next instruction in the program. The address registers AR points at an array of data. The three registers are connected to the common address bus and either one can provide an address for the memory. PC is used during the fetch phase to read an instruction and AR is used to during the execute phase to read an operand. SP is used to PUSH or POP items into or from the stack.
1000 Address
PC AR
2000 3000
SP
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X, Y, OR,
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3.5) Summary
A microcomputer performs a task by reading and executing the set of instructions written in its memory. Registers are used to load data directly or to save data bytes. In data transfer (copying), the destination register is modified but the source register retains its data. The microprocessor transfers data from an input port to the accumulator (IN) and from the accumulator to an output port (OUT). The instruction OUT cannot send data from any other register. The microprocessor performs subtraction by using the method of 2's complement. A microprocessor is basically a programmable logic chip. The branch instructions are the most powerful instructions because they allow the microprocessor to change the sequence of a program, either unconditionally or under certain test conditions.
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3.8) Assignments
Write a Detailed essay on Classification of Instructions.
3.11) Keywords
Registers, Accumulator, Instruction formats for instruction are the four-address instruction word, the three-address instruction word, the two-address instruction word, the single address instruction word, the zero address instruction word, Looping, Indexing, Direct addressing, Extended addressing, Indirect addressing, Indexed addressing, Immediate addressing, Stack, Queue, Subroutine.
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