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F08vhdltutorial 100321210740 Phpapp02

VHDL stands for Very High Speed Integrated Circuit Hardware Description Language. Allows complex digital circuits to be easily created. Strong understanding of your code is more important than syntax and style.

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34 views

F08vhdltutorial 100321210740 Phpapp02

VHDL stands for Very High Speed Integrated Circuit Hardware Description Language. Allows complex digital circuits to be easily created. Strong understanding of your code is more important than syntax and style.

Uploaded by

manojpeehu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Introduction to VHDL

Fall 2008

Jason Lor [email protected]

Outline

Brief Overview of VHDL Structural Elements of VHDL


Entity Architecture Signals

Data Types & Operators in VHDL Assignment Execution


Concurrent Sequential (Process)

Brief Overview of VHDL


VHDL
... stands for Very High Speed Integrated Circuit Hardware Description Language ... can be translated into an actual hardware implementation ... allows complex digital circuits to be easily created
In VHDL, strong understanding of your code is more important than syntax & style.

Structural Elements

Entity

Interface

Example: Ports, I/O

Architecture

Implementation Behaviour Function

Entity
Describes the interactions of a module
entity GarageDoorOpener is port( i_button : in std_logic; i_sensor : in std_logic; i_stop : in std_logic; o_active : out std_logic; o_direction : out std_logic entity BlockName is port( clock_gen : in std_logic; input1 : inout boolean; input2 : in std_integer; output output1 : out string; : buffer character

); end entity;

); end entity;

Port is a keyword that describes the data ow PortName : Mode DataType ; is used to separate elements, not for terminating the statement

Entity
Clock Generator 1 0 Rising Edge Falling Edge
Periodic Function

Architecture
Species the implementation of the module One entity can have several architectures
architecture ArchitectureName of EntityName is begin a AND b => c; end ArchitectureName;

Entity ports are available as signals within the architecture

Signals
are intermediary ports within the architecture represents wires and storage elements

statements are concurrent


architecture rtl of GarageDoorOpener is signal stop_door signal SignalName : std_logic; : datatype

begin <architecture code here> end rtl;

Data Types
similar to programming, all signals and ports should have a data type all signals and port must have a data type
Data Types Boolean Bit Character Integer Real std_logic_vector std_logic type

Data Types
std_logic_vector is an array of std_logic variables
std_logic U : uninitialized X : unknown 0 : logic 0 1 : logic 1 Z : high impedance W : weak signal (either 1 or 0) L : weak signal (leaning 0) H : weak signal (leaning 1) - : dont care

Data Types
type enumerable type
... is an array of data types and values similar to std_logic_vector & std_logic ... can be dened by you

type TrafcLightState is (INIT, RED, REDYELLOW,YELLOW, GREEN); type LightSwitchState is (0, 1); type TypeName is (datatype, variablename);

Typical Operators
Logical Operators
AND NOR NOT

Relational Operators
= /= < Equal Not Equal Less than Greater than

OR

NAND

XOR

XNOR

>

Mathematical Operators
+ * / Addition Subtraction Multiplication Division

Assignment Execution
Concurrent/Continously or Combinational Logic To give a signal a concurrent assignment SignalName <= expression; Once your VHDL les compile, the compiler will assign your specications to hardware components which operate in parallel with one another Sequential Logic Sequential logic is like programming in that your code executes in sequence You can use conditional assignments like if, case etc.

Assignment Execution
In order to utilize sequential logic you have to use process statements There are two types of process statements, inside processes and outside processes Process Statements
... species a block of sequentially executed statements ... run concurrently with each other ... allows the use of if, else if, case, when, with, select statements

Assignment Execution
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

Entity
entity TrafcLight is port( i_clock : in std_logic; i_pedestrian : out std_logic; o_red : out std_logic; o_yellow : out std_logic; o_green : out std_logic;

Architecture continued, Processes, Cases and If/elses


process(i_clock) begin if rising_edge(trafc_clock) then if i_pedestrian = 1 then current_state = YELLOW; else case current_state is when RED => current_state <= GREEN; when GREEN => current_state <= RED; when YELLOW => current_state <= RED; end case; end if; end if; end process; end rtl;

); end entity;

Architecture, Signal, Type


architecture RTL of TrafcLight is type state_t is (RED, YELLOW, GREEN); signal current_state : state_t; begin o_red <= 1 when (current_state = RED) else 0; o_yellow <= 1 when (current_state = YELLOW) else 0; o_green <= 1 when (current_state = GREEN) else 0;

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