Assignment Two CSNB123 Computer Organization and Architecture

Bachelor of Information Technology (Information System) (Hons.)

Prepared for: Dr. Asmidar Binti Abu Bakar

Prepared by:
No Name ID Signature

Tony Kennedy Anthonysamy

IS090112

2 3 4 5 6

Shalini Ramasamy Honnie Fiona Clement Saravanan Raja Rubanesh Chantharan Sarmila Gunalan

IS090099 IS090119 IS090094 IS090092 IS090095

Last Updated: December 20, 2012

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Reduced Instruction Set Computer One of the primary goals of computer architects is to design computers that are more cost

effective the machine, the cost of programming, and costs incurred related to the architecture in debugging Set Computer (RISC) being as cost-effective as a Complex Instruction Set Computer (CISC). This paper will argue that the next generation of VLSI computers may be more effectively implemented. 2.0 The reason why computers are become more complex is: Speed of Memory vs. Speed of CPU - John Cocke says that the complexity began with the transition in speeds; it is not clear that architects have asked themselves whether this imbalance still holds. Microcode and LSI Technology - Micro programmed control allows the implementation of complex circuit memories made in the late 60's and early 70's have caused micro programmed control to be control, the cost to expand an instruction set is very small; only a few more words of control. Code Density - The cost of 10% more memory is often far cheaper than the cost of squeezing 10% out of the CPU Cost for a large scale CPU is in additional circuit packages needed while cost for a single chip CPU is more likely to be in slowing down performance due to larger. Marketing Strategy - Unfortunately, the primary goal of a computer company is not to design the most cost-effective computer; the primary goal of a computer company is to make the most money by selling computers. Complex instruction sets are certainly primary "marketing" evidence of a better computer. Upward Compatibility - New architectures tend to have a habit of including all instructions found in the machines of successful competitors, perhaps because architects and customers have no real grasp over what defines a "good" instruction set. Support for High Level Languages - As the use of high level languages becomes increasingly popular, manufacturers have become eager to provide more powerful instructions to support them. Use of Multiprogramming - This complexity largely disappears on a machine without complicated instructions or addressing modes with side effects. Compilers and assembly language programmers also rightfully ignore parts of the instruction set which are not useful under the given time-space tradeoffs. Therefore the compiler writer is replacing the assembly-language programmer in deciding which instructions the machine will execute. 3.0 Rapid changes in technology and the difficulties in implementing CISCs have resulted in several interesting effects as stated below: Faster memory - The advances in semiconductor memory have made several changes to the assumptions about the relative difference in speed between the CPU and main memory. Irrational Implementations - One example was discovered by Peuto and Shustek for the IBM 370 [Peuto,Shustek77]; they found that a sequence of load instructions is faster than a load multiple instruction for fewer than 4 registers. We found that for the VAX 11/780, replacing this single "high level" instruction by several simple instructions (COMPARE, JUMP LESS UNSIGNED, ADD, MULTIPLY) that we could perform the same function 45% faster.

 Lengthened Design Time Now takes at least three years to go through the same cycle for a machine like the VAX.1 This long design-time can have a major effect on the quality of the resulting implementation; the machine is either announced with a three year old technology or the designers must try to forecast a good implementation technology and attempt to pioneer that technology while building the machine. Increased Design Errors - The control store is loaded from a floppy disk allowing microcode to be maintained similarly to operating systems; bugs are repaired and new floppies with updated versions their solution was to use a Field Programmable Logic Array and 1024 words of Writable Control Store (WCS) to patch microcode errors. 4.0 The factors indicate a Reduced Instruction Set Computer as a reasonable design alternative is: Implementation Feasibility - Improvement in VLSI technology will eventually make a single chip version feasible, but only after less complex but equally functional 32-bit architectures can be realized. Design Time - If VLSI technology continues to at least double chip density roughly every two years, a design that takes only two years to design and debug can potentially use a much superior technology and hence be more effective than a design that takes four years to design and debug. If leaving out an instruction or address mode causes the machine to speed up the minor cycle by 10%, then the addition would have to speed up the machine by more than 10% to be cost effective. Better use of chip area - We feel that the area gained back by designing a RISC architecture rather than a CISC architecture can be used to make the RISC even chip, the RISC will have the silicon area to use pipelining techniques; when the CISC gets pipelining the RISC will have on chip caches, etc. 5.0 A High-Level Language Computer System has been defined as having the following characteristics: Uses high-level languages for all programming, debugging and other user system interactions. Discovers and reports syntax and execution time errors in terms of the high-level language source program. Does not have any outward appearance of transformations from the user programming language to any internal languages. A High-Level Language Computer System whether it is implemented with a CISC that maps onetoone with the tokens of the language, or if the same function is provided with a very fast but simple machine. 6.0 Below are the examples of work on RISC architectures: At Berkeley - By a judicious choice of the proper instruction set and the design of a corresponding architecture, we feel that it should be possible to have a very simple instruction set that can be very fast. At Bell Labs - Johnson used an iterative technique of proposing a machine, writing a compiler, measuring the results to propose a better machine, and then repeating the cycle over a dozen times. Though the initial intent was not specifically to come up with a simple design, the result was a RISC-like 32-bit architecture whose code density was as compact as the PDP11 and VAX [Johnson79].

 At IBM - They are able to benchmark programs in a subset of PL/I that runs about five times the performance of an IBM S/370 model 168. 7.0 Conclusion As a conclusion we can conclude that there are undoubtedly many examples where particular "unique" instructions can greatly improve the speed of a program. Rarely have we seen examples where the same benefits apply to the system as a whole. For a wide variety of computing environments we feel that careful pruning of an instruction set leads to a cost-effective implementation. Computer architects ought, to ask themselves the following questions when designing a new instruction set. If this instruction occurs infrequently, is it justifiable on the grounds that it is necessary and not synthesizable. We have assumed that it is worthwhile to minimize the

"complexity" and maximize "performance" while meeting the definition of a High-Level Language Computer System. In particular, we feel that VLSI computers will benefit the most from the RISC concepts. Too often, the rapid advancements in VLSI technology have been used as a panacea to promote architectural complexity. We see each transistor as being precious for at least the next ten years. While the trend towards architectural complexity may be one path towards improved computers, this paper proposes another path, the Reduced Instruction Set Computer.