i

SYSTEM BUSSES
And their architecture

University of Engineering and Technology, Lahore Department

of Electrical Engineering

Table of Contents
Abstract .......................................................................................................... Error! Bookmark not defined. List of Figures ............................................................................................................................................. iv 1. Introduction ........................................................................................................................................ 1 a. Bus ..................................................................................................................................................... 1 b. Terms to characterize the buses ....................................................................................................... 1 c. Major categories of buses ................................................................................................................. 2 i. Control Bus. .................................................................................................................................... 2

ii. Address Bus. ................................................................................................................................... 2 iii. Data Bus. ........................................................................................................................................ 2 2. Key features of buses ......................................................................................................................... 3 a. Bus Arbitration................................................................................................................................... 3 b. Interrupt Request Lines (IRQs) .......................................................................................................... 4 c. Input/output Address ........................................................................................................................ 4 d. Direct Memory Access (DMA) Channels ........................................................................................... 5 e. Bus Mastering .................................................................................................................................... 5 3. System Bus ........................................................................................................................................... 6 ii

a. Memory Bus ....................................................................................................................................... 6 b. I/O bus................................................................................................................................................ 7 4. Major Bus Architectures ................................................................................................................... 8 a. Industry Standard Architecture (ISA) ................................................................................................ 8 b. Micro-channel Architecture (MCA) ................................................................................................... 9 d. VESA Local Bus (VLB) ....................................................................................................................... 11 e. Peripheral Component Interconnect Local Bus .............................................................................. 12 f. Accelerated graphic port ................................................................................................................. 13

g. Universal Serial Bus (USB) ............................................................................................................... 14 Conclusion: ............................................................................................................................................... 14 References .................................................................................................................................................. 15

iii

List of Figures
Figure 1 Bus replaces the multiple pathways between components (kioskea.net n.d.) ____________________ 1 Figure 2 Control bus, address bus and data bus (integrated publishing n.d.) ____________________________ 3 Figure 3 System Buses- Memory Bus and I/O Bus (System bus n.d.) ___________________________________ 7 Figure 4 8-bit ISA connector (kioskea.net n.d.) ____________________________________________________ 8 Figure 5 16-bit ISA connector (kioskea.net n.d.) ___________________________________________________ 8 Figure 6 EISA slot (wikipedia n.d.) _____________________________________________________________ 10 Figure 7 VL-Bus connection (kioskea.net n.d.) ___________________________________________________ 11 Figure 8 PCI connections (integrated publishing n.d.) _____________________________________________ 12 Figure 9 AGP connector (integrated publishing n.d.) ______________________________________________ 13 Figure 10 USB (Wikipedia n.d.) _______________________________________________________________ 14

iv

1. Introduction a. Bus A bus is simply a channel of communication of information between two or more devices. In computing, it is a physical pathway (wires, cable, and printed circuit board) over which the communication between multiple hardware devices can be carried out. The purpose of busses is to reduce the number of pathways required to carry out communication between different peripherals and the CPU by replacing the multiple pathways with a single communication bus.

Figure 1 Bus replaces the multiple pathways between components (kioskea.net n.d.)

b. Terms to characterize the buses The amount of data that a bus can transfer simultaneously characterizes a bus. The following terminology is generally used to characterize a bus: i. Width. The width of the bus specifies the number of physical lines (wires) in the bus. Each line can transmit a bit and the number of lines in a bus- its width, determines the number of bits the bus can transfer simultaneously. Frequency. Frequency is used to determine the number of data packets that are transferred (sent or received) over the bus per second. A cycle is whenever the data is sent or received.

ii.

iii.

Maximum transfer speed. Maximum transfer speed is the amount of data that a bus can transfer per unit time. It is the product of the width and the frequency of the bus.

c. Major categories of buses A system bus usually consists of 50 to 100 physical lines that can be further categorized depending on the type of information that flows through them. The three major sub-categories are: i. Control Bus. The control bus is the pathway that the CPU uses to send and receive different control signals from the processor to different devices and vice versa. These control signals are required to monitor and coordinate the operations of the devices and include signals like read, write, acknowledge, interrupt and synchronization signal etc. the control bus is bidirectional bus since it carries the signals from the hardware to the processor also. Address Bus. The address bus carries the signals that specify the address of the memory locations on which an operation such as read or write is to be performed. The processor has to keep the track of the accessible memory locations and has to specify these locations to the other devices attached in order for them to access any data stored. The CPU communicates the memory locations via the address bus which carries the physical addresses. The width of the address bus directly determines the number of accessible memory locations. For example an 8-bit address bus can access 28 memory locations while a 16-bit address bus can access 216 memory locations. The address bus is a unidirectional bus i.e. it carries the address in one direction only- from the processor to the devices. Data Bus. The data bus bidirectional bus as it carries information (data) to and from the CPU and memory. It carries the instructions and operands from the memory to the CPU and vice versa and also from the memory to the input/output devices for different input/output operations to be performed. The data bus can only operate in one direction at one time.
2

ii.

iii.

The data bus determines the performance of the system. The wider the system bus the more the information transferred simultaneously and the higher the performance of the system. The speed of the data bus is determined by the system clock speed which also determines the systems performance.

Figure 2 Control bus, address bus and data bus (integrated publishing n.d.)

2. Key features of buses

a. Bus Arbitration The bus is being used by a number of devices connected to it for the purpose of communication. Since so many devices share the bus, it is mandatory that a method is determined for the devices to decide which one of them gets to use the bus first. The method that is employed to determine the usage of the bus by different devices id call the bus arbitration. This method is based on the priority assigned to different devices. The high priority devices like the processor and the RAM can access the bus first while the low priority devices like the video card and the CD-ROM are assigned low priority and hence often have to wait.

b. Interrupt Request Lines (IRQs) The interrupt request lines are special pathways dedicated to the communication of the interrupt signals. Earlier microprocessors performed the input/output operations by waiting in loop for the peripherals to get ready. This meant that the microprocessor had to waste a considerable amount of time doing nothing, waiting for the peripherals to signal. This time while not so significant for the older computers meant eternity for the newer and faster processors that could get a number of other tasks performed in the time that was wasted. The interrupts were hence designed to allow the processor to carry out its routine tasks during the time that was wasted earlier. This was achieved by the interrupt signals that were generated by the peripherals indicating their need of attention by the processor. The processor halts whatever task it is performing when an interrupt is received and gives attention to the device that generated the interrupt. After catering the demand of the particular device, the processor resumes its processing. The devices indicate their need of attention by generating interrupt request signals that are carried to the processor through the interrupt request lines. These lines pass through an interrupt controller and each line usually has a specific number that the CPU associates with a specific device. The interrupts are often referred to as a hexadecimal value. Whenever an interrupt is received, the processor immediately drops whatever it is currently processing and the request is handled. However if the task that the processor is performing has a higher priority than the interrupt received, the processor will continue performing the task and would turn to the interrupt request once the task is finished. c. Input/output Address Each devise is allocated a specific amount of memory to allow the CPU to communicate with it by exchanging data and information. The size of the memory allocated to each device may vary between different devices. The Input/output address is the starting address of the memory segment allocated to the devices. It is represented as a hexadecimal number. The CPU sends instructions to the devices using the unique I/O address allotted to the particular device.

d. Direct Memory Access (DMA) Channels The direct memory access channels are data lines through which the devices such as the CD-ROM, sound cards etc can directly interface with the RAM to retrieve and write data without involving the CPU at all. This saves the CPU a considerable amount of overhead since know the CPU does not have to supervise the flow of data between two devices but is free to perform its usual tasks although a considerable width of the bus is still being used for the direct memory access. The clock cycles during which the busses are not under the use of the processor can be utilized by the devices to access memory directly. For DMA each device needs a separate channel. A conflict of channels may result in the seizure of the systems. e. Bus Mastering In earlier computers, buses were essentially backplane connected directly or via amplifiers to the CPU. The CPU was in charge of supervising the communication via the buses and all the devices used the same clock system that controlled the operations of the CPU. This meant that all devices had to work on the same speed. Thus the CPU either had to wait for the slower devices to get ready or work at a slower speed. It was in charge of accepting the data from on device and directing it towards the other. With the introduction of the bus controller the CPU was relieved of its task to supervise the flow of data over the buses. The bus controller is now responsible of taking care of the communication protocol instead of the CPU. This allowed the CPU and the memory to evolve independently. The data can now be transferred between devices without the intervention of the CPU. This process is called bus mastering.

3. System Bus

The system bus is a term used collectively for two sub-categories of buses namely The memory bus The I/O bus The memory bus and the I/O bus both are composed of the control, address and data buses. a. Memory Bus This particular bus is basically used for connecting the processor with the memory systems and cache. Modern computers are capable of processing at very high rates. This leads to a high demand of information and data from the memory by the processor. As a result a greater width a speed of the memory bus is need. The development of the microprocessor has rapidly outrun the rate of development of the memory bus. As a result the CPU spends a lot of its time idle waiting for the data to process. This bottleneck in the efficiency of the system has been removed by the introduction of the Dual Independent Bus (DIB) architecture. According to this architecture the memory bus is split into two buses The frontside bus The backside bus. The frontside bus connects the CPU to the chipset, the Northbridge, which in turn interfaces the processor with the other devices and the memory subsystems. The backside bus on the other hand connects the CPU with the Level 2 cache. The backside bus runs independently than the frontside bus and therefore can operate on higher speed and width to fetch the data from the cache.

Figure 3 System Buses- Memory Bus and I/O Bus (System bus n.d.)

b. I/O bus The I/O bus is basically designed to connect the devices such as the hard disk, floppy drive, CD-ROM, modems and network card to the CPU and the system memory. These devices do not demand a faster and efficient mode of transfer unlike the memory bus; therefore they are operated on lower widths and speeds. The I/O bus are also subdivided into two categories as follows The local I/O bus: This bus is used to connect the performance critical input/ output devices with the CPU. This is a high speed bus and connects devices like video cards, disk storage devices and high speed network cards etc with the processor and the memory systems. Standard I/O bus: it is a low speed bus and connects the slower peripherals like the mouse, modem slower network cards etc.

4. Major Bus Architectures

a. Industry Standard Architecture (ISA) This is the original bus architecture that was employed by the IBM PC 8088. The original 8088 had an 8-bit system bus with a speed of 4.77 MHz and since all the components were required to work with same specifications at that time, the original ISA was also 8-bit wide and had a speed of 4.77 MHz with 20 address lines and 8 data lines, 6 interrupt lines and 3 DMA lines. The bandwidth was 1.2MB/sec.

Figure 4 8-bit ISA connector (kioskea.net n.d.)

With the advancement of PC technology and the introduction of 286, the ISA was later upgrade to 16-bit bus with a speed of 8 MHz. This resulted in a theoretical speed of 16MB/second, even though the actual speed at which the bus runs is much lower. One of the reasons is that since the ISA and the computer clock works asynchronously, many cycles are wasted which results in slower speed.

Figure 5 16-bit ISA connector (kioskea.net n.d.)

The upgraded ISA had a 16-bit data path for new 16 bit processors. ISA also allowed bus mastering and DMA but it only allowed the hardware to access the first 16MB of RAM. It could use one busmastering device and had four additional DMA channels. This version also incorporated five edge triggered IRQs. The maximum bandwidth provided by this version was 5.3 MB/sec. ISA provides a communication medium for less demanding and slower devices and many computers still come with ISA ports.
8

b. Micro-channel Architecture (MCA) MCA- micro-channel architecture was introduced by IBM in an attempt to replace the ISA. With the introduction of the 32-bit data bus of 386 micro-processor, IBM was driven into developing an address bus with the same width. The MCA was in many ways ahead of its time. The following were a few of its key features. 32-bit bus width: the MCA featured an impressive 32-bit bus width which was a feature it shared with the much advanced buses like VESA and PCI local buses. Hence the MCA was far more advanced than the ISA. 10MHz speed: the MCA bus operated at a clock speed of 10 MHz. 20 MB/sec maximum bandwidth 32-bit memory addressing: this provided a maximum addressable memory of 4GB. 11 level triggered interrupts: level triggered interrupts were introduced as opposed to the edge triggered interrupts supported by ISA. Level trigger interrupts allowed the sharing of interrupt lines which solved the shortage of interrupt lines- a problem in case of ISA. Bus mastering: the MCA supported multiple bus mastering with proper bus arbitration. Plug and Play: the most startling feature of MCA was that it could be configured by software. This was an amazing feature since Microsoft had not introduced PnP yet. The major drawback of MCA was that it was not compatible with ISA and its DMA controller circuitry was rather poor. Moreover the MSA bus was proprietary. Hence the MCA was rather short-lived.

c. Extended ISA (EISA) The Extended Industrial Standard Architecture bus was launched by Compaq and as its name implies was an extended version of the ISA bus. It was quite similar in features to the MCA bus but unlike the MCA , it was compatible with the ISA. Even though it was not proprietary and was

compatible with the ISA bus, EISA failed to be as successful as the ISA itself. Some of its key features are as follows. ISA compatibility: EISA was compatible with the ISA which meant that the ISA cards would still work on the EISA architecture slots. 32 bit width: like the MCA it too had a bus width of 32-bits. 32-bit memory addressing: this provided a maximum addressable memory of 4GB like the MCA. Level or edge triggered interrupts: these were also programmable. Bus Mastering: EISA also supported bus mastering and proper bus arbitration. Automatic board configuration. Plug and Play: EISA could automatically configure the adapter cards quite like the modern day plug and play software. 8 MHz bus speed.

Figure 6 EISA slot (wikipedia n.d.)

10

d. VESA Local Bus (VLB) With the advent of the graphical user interface, the requirements of the video cards for communication rapidly outgrow the speed and width of the current busses. The Video Electronics Standards Association address introduced the VESA local bus in order to improve the video performance in the PCs. The key features are: 32-bit bus: a direct extension of 486 memory bus. 33 MHz speed: although the bus speed of up to 66 MHz is supported Future compatibility: the feature of future compatibility was introduced so that all the VESA compatible devises would be able to operate on the current and the future VL-bus without any need of modification. A theoretical bandwidth of 160 MB/sec was supported. Caching: caching was supported for CPU and the motherboard devices. 3 bus masters: the VL-bus supported 3 bus masters. Although the performance of the VL-Bus was greatly improved as compared to the ISA bus, it still had a few disadvantages. A few are listed as follows. Poor adaptability for the Pentium: since the VL-bus was build especially for the 486, adapting it to Pentium resulted in a number of compatibility problems. Low number of cards that could be used on the bus: timing problems would also be created if more than one card was used occasionally. No support for bus mastering: there was no arbitration scheme either. No support for plug and play.

Figure 7 VL-Bus connection (kioskea.net n.d.)

11

e. Peripheral Component Interconnect Local Bus PCI is the most popular and successful local bus. It was introduced by INTEL and its key features are as follows 32-bit bus: the bus it 32-bit wide and is synchronous; It can carry both data and addresses. 33 MHz speed: the future version of the bus had a speed up to 66 MHz. Burst mode: PCI can transfer the data in burst mode. 132 MB/sec bandwidth Can operate on 2 logic voltages: 5 V and 3.3 V Full multiple master capabilities: allow multiple hard disk controllers to operate at the same time. PCI supports full bus mastering. The bus arbitration is provided via the chipset. The PCI built to accommodate multiple bus mastering of several devices at the same tome. The arbitration circuitry supervises the arbitration and ensures that no conflict between devices is encountered. And it also allows a device to use the full throughput if no other device is currently using the bus. Use of latency timer: the latency timer is supported by the PCI devices and it determines the maximum amount of time that each device is allowed to use the bus. Plug and play: the plug and play architecture of the bus can be utilized if a plug and play OS like Windows 95/98/2000 is run and if the BIOS supports plug and play.

Figure 8 PCI connections (integrated publishing n.d.)

12

f. Accelerated graphic port The AGP caters the rising demand of faster data transmission for the graphics. It does not share the I/O bus and therefore is referred to as a port. A port only connects two peripherals. The features of AGP are as follows 32 bit wide: like the PCI Double speed and bandwidth: the advantage of AGP is that it utilizes the full bus speed unlike the PCI and hence its speed is 66 MHz instead of 33 MHz. this also results in twice as much bandwidth which is 254.3 MHz. Theoretical speed of 508.6 MB/sec: AGP has defined a 2X mode according to which the data is transmitted both, the falling and the rising end of the clock cycle. While the PCI only uses one of these transitions to transmit data. 4X mode: the AGP can also run in 4X mode and the bandwidth is quadrupled in this mode which becomes 1018 MB/sec.

Figure 9 AGP connector (integrated publishing n.d.)

13

g. Universal Serial Bus (USB) Universal Serial Bus is a high speed serial bus with a transfer rate of 12Mbps. One of the biggest advantages of the USB it the connector that it uses which similar for all USB devices. USB also supports Daisy Chaining and up to 127 devices can be connected to the USB chain. Modern USB operates at about 480Mbps and is one of the most popularly used interconnection means used in personal computing.

Figure 10 USB (Wikipedia n.d.)

Conclusion: The buses play an important role in the efficiency and performance of a system and along with rest of the components they also underwent some drastic improvements over the years and are still evolving to make better and more efficient computing possible.

14

References
integrated publishing. http://www.tpub.com/content/fc/14100/css/14100_129.htm (accessed December 26th, 2009). kioskea.net. http://en.kioskea.net/contents/pc/bus.php3 (accessed December 26th , 2009). PC guide. http://www.pcguide.com/ref/mbsys/buses/types/agp.htm (accessed December 28, 2009). System bus. http://www.just2good.co.uk/systemBus.php (accessed December 27th, 2009). wikipedia. http://en.wikipedia.org/wiki/File:EISA_Bus.jpg (accessed December 27, 2009). Wikipedia. http://en.wikipedia.org/wiki/Universal_Serial_Bus (accessed December 28, 2009).

15