DVD-Video Recorder

DVDR3305/02/05/19/51

DVDR3355/02/05/19/51 & DVDR3365/02/05/19/51

Back End Repair

CLASS 1 LASER PRODUCT

Contents
1 2 3 4 5 6 Technical Specications and Connection Facilities Safety Information, General Notes & Lead Free Requirements Directions for Use Mechanical Instructions Upgrade Software & Repair Chart Block Diagrams,Waveforms, Wiring Diagram Overall block diagram Control block diagram Wiring diagram Waveforms of Analog Board Waveforms of Digital Board Test Point Overview for Analog Board Test Point Overview for Digital Board Circuit Diagram and PWB Layout Analog: Frontend Video (FV) Analog: Video In / Out (IOV) Analog: Audio In / Out (IOA) Analog: Power Supply (PS) Analog: Multi Sound Processing (MSP) Analog: Audio Converter (DAC_ADC) Analog: Digital In / Out 1 (DIGIO 1) Layout: Analog-Main Part (Top View) Layout: Analog-Main Part (Bottom View) Front: Front Panel

Page
2 5 7 9 12 19 19 20 21 22 23 24 25 26 26 27 28 29 30 31 32 33 34 35

Contents
Front: Front Panel Layout: Front Panel (Top View) Front: Standby Layout: Standby (Top View) Digital: Back-end Processor Digital: Memory Digital: IEEE 1394 Physical Layer Digital: Video Input Processor Digital: Interfaces Layout: Digital-Main Part (Top View) Layout: Digital-Main Part (Bottom View) 8 Circuit- and IC Description Front Board (Panel Display + Key) Analog Board Digital Board IC Description Analog Board Digital Board 9 Exploded View & Spare Parts List Exploded View of the set Spare Parts List 10 Revision List

Page
36 37 38 38 39 40 41 42 43 44 45 47 47 47 52 55 55 60 71 71 72 73

Copyright 2005 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips. Published by KC-TE 0530 AV Systems Printed in the Netherlands Subject to modication EN 3139 785 30931

Version 1.1

EN 2

1.

3139 785 3093x

Technical Specications and Connection Facilities

1.
1.1

Technical Specications and Connection Facilities

PCB Locations

Front boards (Behind the metal bracket)

Analog Board

Digital Board

Basic Engine

1.2

General:
Mains voltage Mains frequency Power consumption (typical) Standby Power Consumption : : : : 220V 240V 50 Hz 25 W <4W

1.3.4

Video Performance: Channel 25 / 503,25 MHz, Test pattern: PAL BG PHILIPS standard test pattern, RF Level 74dBV Measured on SCART 1 Frequency response : 0.1 4.00 MHz 3dB Group delay (0.1 MHz - 4.4 MHz) : 0 nsec 150 nsec

1.3

RF Tuner
Test equipment: Fluke 54200 TV Signal generator Test streams: PAL BG Philips Standard test pattern 1.3.5

Audio Performance: Audio Performance Analogue - HiFi: Frequency response at SCART 1 (L+R) output : 100 Hz 12 kHz / 0 3dB S/N according to DIN 45405, 7, 1967 and PHILIPS standard test pattern video signal : 50dB, unweighted Harmonic distortion (1 kHz, 25 kHz deviation) : 1.5% Audio Performance NICAM: Frequency response at SCART 1 (L+R) output

1.3.1

System PAL B/G, PAL D/K, SECAM L/L, PAL I

1.3.2

RF - Loop Through: Frequency range Gain: (ANT IN - ANT OUT) : 45 MHz 860 MHz : -6dB to 0dB

1.3.3

Receiver: PLL tuning with AFC for optimum reception Frequency range : 45.25 MHz 857 MHz Sensitivity at 40dB S/N : 60dBV at 75 (video unweighted)

: 40 Hz 15 kHz / 0 3dB

S/N according to DIN 45405,7,1967 and PHILIPS standard test pattern video signal : 60dB, unweighted Harmonic distortion (1kHz) : 0.5%

Technical Specications and Connection Facilities

1.3.6 Tuning Automatic Search Tuning Scanning time without antenna Stop level (vision carrier) Maximum tuning error of a recalled program Maximum tuning error during operation : typ. 3 min. : 37dBV : 62.5 kHz : 100 kHz 1.4.3

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EN 3

Audio/Video Front Input Connectors Audio - Cinch Input voltage Input impedance Video - Cinch Input voltage Input impedance : 2.2Vrms : > 10k : 1Vpp 3dB : 75

Tuning Principle Automatic B, G, I, DK and L/L detection Manual selection in STORE mode

1.4
1.4.1

Analogue Inputs / Outputs

SCART 1 (Connected to TV) Pin Signals: 1 - Audio R 2 - Audio R 3 - Audio L 4 - Audio GND 5 - Blue / GND 6 - Audio L 7 - Blue out 8 - Function switch 9 10 11 12 13 14 15 16 17 18 19 20 21 - Green GND - NC - Green - NC - Red GND - Fast switch GND - Red out - Fast switch RGB / CVBS - CVBS GND OUT - CVBS GND IN - CVBS out - CVBS in - Shield 1.8V RMS 1.8V RMS

Video - YC (Hosiden) According to IEC 933-5 Superimposed DC-level on pin 4 (load > 100k) < 2.4V is detected as 4:3 aspect ratio > 3.5V is detected as 16:9 aspect ratio Input voltage Y : 1Vpp 3dB Input impedance Y : 75 Input voltage C : burst 300mVpp 3dB Input impedance C : 75 1.4.4 Audio/Video Output rear Connectors Audio - Cinch Output voltage Output impedance Video - Cinch Output voltage Output impedance : 2Vrms max. : > 10k : 1Vpp 3dB : 75

< 2V = TV > 4.5V / < 7V = asp. Ratio 16:9 DVD > 9.5V / < 12V = asp. Ratio 4:3 DVD 0.7Vpp 0.1V into 75 (*)

0.7Vpp 0.1V into 75 (*) < 0.4V into 75 = CVBS >1V / < 3V into 75 = RGB 1Vpp 0.1V into 75 (*) 1.5.1

Video - YC (Hosiden) According to IEC 933-5 Superimposed DC-level on pin 4 (load > 100k) < 2.4V is detected as 4:3 aspect ratio > 3.5V is detected as 16:9 aspect ratio Output voltage Y : 1Vpp 10/-15% Output voltage C : 300mVpp 1/-4dB

1.5

Video Performance
All outputs loaded with 75 SNR measurements over full bandwidth without weighting. SCART (RGB) SNR Bandwidth : > -65dB on all output : 4.8MHz 2dB

1.4.2

SCART 2 (Connected to AUX) Pin Signals: 1 - Audio R 2 - Audio R 3 - Audio L 4 - Audio GND 5 - Blue GND 6 - Audio L 7 - Blue in 8 - Function switch 9 - Green GND 10 - NC 11 - Green in 12 - NC 13 - Red GND 14 - Fast switch GND 15 - Red in 16 - Fast switch RGB / CVBS 17 - CVBS GND OUT 18 - CVBS GND IN 19 - CVBS / RGB out sync 20 - CVBS in 21 - Shield (*) for 100% white 1.8V RMS 1.8V RMS

1.6
1.6.1

Audio Performance CD
Cinch Output Rear Output voltage 2 channel mode Channel unbalance (1kHz) Crosstalk 1kHz Crosstalk 16Hz-20kHz Frequency response 20Hz-20kHz Signal to noise ratio Dynamic range 1kHz Distortion and noise 1kHz Distortion and noise 16Hz-20kHz Intermodulation distortion Mute Outband attenuation: : : : : : : : : : : : : 2Vrms 2dB < 1dB > 95dB > 87dB 0.2dB max > 85dB > 83dB > 83dB > 75dB > 70dB > 95dB > 40dB above 30kHz

1Vpp 0.1V into 75 (*)

EN 4
1.6.2

1.
Scart Audio

3139 785 3093x

Technical Specications and Connection Facilities

Output voltage 2 channel mode Channel unbalance (1kHz) Crosstalk 1kHz Crosstalk 16Hz-20kHz Frequency response 20Hz-20kHz Signal to noise ratio Dynamic range 1kHz Distortion and noise 1kHz Distortion and noise 16Hz-20kHz Intermodulation distortion Mute Outband attenuation:

: : : : : : : : : : : :

1.6Vrms 2dB < 1dB > 85dB > 70dB 0.2dB max > 80dB > 75dB > 75dB > 50dB > 70dB > 80dB > 40dB above 25kHz

1.7
1.7.1

Digital Output
Coaxial CDDA / LPCM (incl MPEG1) MPEG2, AC3 audio DTS : according IEC958, IEC60958-1,-3 : according IEC1937, IEC61937 : according IEC1937, IEC 61937 amendment 1

1.8
1.8.1

Digital Video Input (IEEE 1394)

Applicable Standards Implementation according: IEEE Std 1394-1995 IEC 61883 - Part 1 IEC 61883 - Part 2 SD-DVCR (02-01-1997) Specication of consumer use digital VCRs using 6.3 mm magnetic tape - dec. 1994 Annex A of 61883-1

1.9

Dimensions and Weight

Height of feet Apparatus tray closed Apparatus tray open Weight without packaging Weight with packaging : : : : : 5.5mm WxDxH:435x285x65mm WxDxH:435x422x65mm app. 4.0kg 0.5kg app. 6kg

1.10 Laser Output Power & Wavelength

1.10.1 DVD Output power during reading Output power during writing Wavelength 1.10.2 CD Output power Wavelength : 0.3mW : 780nm : 0.8mW : 20mW : 660nm

Safety Information, General Notes & Lead Free Requirements

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EN 5

2.
2.1
2.1.1

Safety Information, General Notes & Lead Free Requirements

Safety Instructions
General Safety Safety regulations require that during a repair: Connect the unit to the mains via an isolation transformer. Replace safety components, indicated by the symbol , only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of re or electrical shock hazard. Safety regulations require that after a repair, you must return the unit in its original condition. Pay, in particular, attention to the following points: Route the wires/cables correctly, and x them with the mounted cable clamps. Check the insulation of the mains lead for external damage. Check the electrical DC resistance between the mains plug and the secondary side: 1. Unplug the mains cord, and connect a wire between the two pins of the mains plug. 2. Set the mains switch to the on position (keep the mains cord unplugged!). 3. Measure the resistance value between the mains plug and the front panel, controls, and chassis bottom. 4. Repair or correct unit when the resistance measurement is less than 1 M. 5. Verify this, before you return the unit to the customer/ user (ref. UL-standard no. 1492). 6. Switch the unit off, and remove the wire between the two pins of the mains plug.

2.2
2.2.1

Warnings
General All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD, ). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are at the same potential as the mass of the set by a wristband with resistance. Keep components and tools at this same potential. Available ESD protection equipment: Complete kit ESD3 (small tablemat, wristband, connection box, extension cable and earth cable) 4822 310 10671. Wristband tester 4822 344 13999. Be careful during measurements in the live voltage section. The primary side of the power supply, including the heatsink, carries live mains voltage when you connect the player to the mains (even when the player is off!). It is possible to touch copper tracks and/ or components in this unshielded primary area, when you service the player. Service personnel must take precautions to prevent touching this area or components in this area. A lightning stroke and a stripe-marked printing on the printed wiring board, indicate the primary side of the power supply. Never replace modules, or components, while the unit is on.

2.2.2

Laser The use of optical instruments with this product, will increase eye hazard. Only qualied service personnel may remove the cover or attempt to service this device, due to possible eye injury. Repair handling should take place as much as possible with a disc loaded inside the player. Text below is placed inside the unit, on the laser cover shield:

2.1.2

Laser Safety This unit employs a laser. Only qualied service personnel may remove the cover, or attempt to service this device (due to possible eye injury). Laser Device Unit Type Wavelength Output Power : Semiconductor laser GaAlAs : 650 nm (DVD) : 780 nm (VCD/CD) : 20 mW (DVD+RW writing) : 0.8 mW (DVD reading) : 0.3 mW (VCD/CD reading) : 60 degree

CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM ADVARSEL SYNLIG OG USYNLIG LASERSTRLING VED BNING UNDG UDSTTELSE FOR STRLING ADVARSEL SYNLIG OG USYNLIG LASERSTRLING NR DEKSEL PNES UNNG EKSPONERING FOR STRLEN VARNING SYNLIG OCH OSYNLIG LASERSTRLNING NR DENNA DEL R PPNAD BETRAKTA EJ STRLEN VARO! AVATTAESSA OLET ALTTIINA NKYVLLE JA NKYMTTMLLE LASER STEILYLLE. L KATSO STEESEEN VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEFFNET NICHT DEM STRAHL AUSSETSEN DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS DOUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU

Figure 2-2 2.2.3 Notes Dolby Manufactured under licence from Dolby Laboratories. Dolby, Pro Logic and the double-D symbol are trademarks of Dolby Laboratories. Condential Unpublished Works. 1992-1997 Dolby Laboratories, Inc. All rights reserved.

Beam divergence

CLASS 1 LASER PRODUCT

Figure 2-1 Note: Use of controls or adjustments or performance of procedure other than those specied herein, may result in hazardous radiation exposure. Avoid direct exposure to beam.

Figure 2-3 Trusurround TRUSURROUND, SRS and symbol (g 2-4) are trademarks of SRS Labs, Inc. TRUSURROUND technology is manufactured under licence frm SRS labs, Inc.

Figure 2-4

EN 6

2.

3139 785 3093x

Safety Information, General Notes & Lead Free Requirements

Due to lead-free technology some rules have to be respected by the workshop during a repair: Use only lead-free solder alloy Philips SAC305 with order code 0622 149 00106. If lead-free solder-pate is required, please contact the manufacturer of your solder-equipment. In general use of solder-paste within workshops should be avoided because paste is not easy to store and to handle. Use only adequate solder tools applicable for lead-free solder alloy. The solder tool must be able o To reach at least a solder-temperature of 400C, o To stabilize the adjusted temperature at the solder-tip o To exchange solder-tips for different applications. Adjust your solder tool so that a temperature around 360C 380C is reached and stabilized at the solder joint. Heating-time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400C otherwise wear-out of tips will rise drastically and ux-uid will be destroyed. To avoid wear-out of tips switch off un-used equipment, or reduce heat. Mix of lead-free solder alloy / parts with leaded solder alloy / parts is possible but PHILIPS recommends strongly to avoid mixed solder alloy types (leaded and lead-free). If one cannot avoid or does not know whether product is lead-free, clean carefully the solder-joint from old solder alloy and re-solder with new solder alloy (SAC305). Use only original spare-parts listed in the Service-Manuals. Not listed standard-material (commodities) has to be purchased at external companies. Special information for BGA-ICs: - always use the 12nc-recognizable soldering temperature prole of the specic BGA (for de-soldering always use the lead-free temperature prole, in case of doubt) - lead free BGA-ICs will be delivered in so-called drypackaging (sealed pack including a silica gel pack) to protect the IC against moisture. After opening, dependent of MSL-level seen on indicator-label in the bag, the BGA-IC possibly still has to be baked dry. (MSL=Moisture Sensitivity Level). This will be communicated via AYSwebsite. Do not re-use BGAs at all. For sets produced before 1.1.2005 (except products of 2004), containing leaded solder-alloy and components, all needed spare-parts will be available till the end of the service-period. For repair of such sets nothing changes. On our website www.atyourservice.ce.Philips.com you nd more information to: BGA-de-/soldering (+ baking instructions) Heating-proles of BGAs and other ICs used in Philips-sets

Video Plus Video Plus+ and PlusCode are registered trademarks of the Gemstar Development Corporation. The Video Plus+ system is manufactured under licence from the Gemstar Development Corporation.

Figure 2-5 Macrovision This product incorporates copyright protection technology that is protected by method claims of certain U.S. patents and other intellectual property rights owned by Macrovision Corporation and other rights owners. Use of this copyright protection technology must be authorized by Macrovision Corporation, and is intended for home and other limited viewing uses only unless otherwise authorized by Macrovision Corporation. Reverse engineering or disassembly is prohibited.

2.3

Lead Free Requirement

Information about Lead-free produced sets Philips CE is starting production of lead-free sets from 1.1.2005 onwards. INDENTIFICATION: Regardless of special logo (not always indicated) One must treat all sets from 1 Jan 2005 onwards, according next rules.

Example S/N:

Bottom line of typeplate gives a 14-digit S/N. Digit 5&6 is the year, digit 7&8 is the week number, so in this case 1991 wk 18 So from 0501 onwards = from 1 Jan 2005 onwards

You will nd this and more technical information within the magazine, chapter workshop news. For additional questions please contact your local repair-helpdesk.

Important note: In fact also products of year 2004 must be treated in this way as long as you avoid mixing solder-alloys (leaded/ lead-free). So best to always use SAC305 and the higher temperatures belong to this.

Directions For Use

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EN 7

3.

Directions For Use

The following except of the Quick Use Guide serves as an introduction to the set. The Complete Direction for the Use can be downloaded in different languages from the internet site of Philips Customer care Center: www.p4c.philips.com

QUICK START GUIDE 1 whats in the box

A Main Unit B Remote
Control
includes 2x AA batteries

DVDR3365
12nc: 3139 246 15861

3 Start initial setup

3a
Press STANDBY-ON 2 on the DVD recorder to turn it on. Note: For successful installation, your cable/satellite box must be turned on.

C RF coaxial
cable

D Scart cable

3b

Turn on the TV to the correct programme channel for the input socket (EXT, 0, AV).
The blue PHILIPS DVD background screen will appear on the TV.

2 connect DVD recorder

System Menu - General

3c

Press SYSTEM MENU on the remote control.

Use 3 4 keys to go through the menu. Select an item by pressing 2, and confirm a setting by pressing OK.

2a 2c 2b

Screen Saver Country Video Output Format Restore Factory Settingd

On
Germany

3d

PAL OK

Highlight and press 2. Select the country of your residence..

Select { Country } and press OK on the remote control.

System Menu - Channel Setup

Channel Search
Search

3e

Modify Channel Information Edit

Highlight and press 2. Setup and install TV channels.

Select { Channel Search } and press OK on the remote control to start automatic TV channel search.

2d

DVD recorder back panel

Sort Channel

Sort

2a 2b 2c 2d

Connect existing antenna cable/satellite signal (or from the Cable/Satellite Box [RF OUT or TO TV]) to the ANTENNA input socket at the back of the DVD recorder. Use the supplied RF coaxial cable to connect the DVD output socket to your TVs antenna recorders TV input socket. Use the supplied Scart cable to connect the DVD recorders EXT 1 TO TV-I/O socket to the matching SCART input socket at the back of your TV. Connect the power cable from the DVD recorders ~ MAINS to the AC power outlet. Helpful Hint: For additional connection diagrams, see User Manual pages 12~19.

System Menu - Language

On Screen Display Language English Default Disc Menu LanguageEnglish Default Subtitle Language Default Audio Language
English English

3f

Highlight and press 2. Select the language.

select TV On-Screen Display language. select default Disc Menu language. select default subtitle language. select default audio language.

System Menu - Clock

Date (dd/mm/yy) Time (hh:mm:ss}
31/01/05 10 : 33 : 57 OK

3g

Highlight and press 2. Set the Date and Time.

Use the numeric keypad 0-9 to input the date/time, then press OK to confirm.

Show DivX Registration Code

3h

Press SYSTEM MENU to exit.

The DVD recorder is ready for use!

See next page for basic recording and playback.

EN 8

3.

3139 785 3093x

Directions For Use

4 start manual recording

4a
Insert a recordable DVD+R/+RW with the label facing up.

5 start playback
To playback a disc

5a

Insert a disc with the label side facing up.

4b

SUPER VIDEO

To record TV programme, press REC SOURCE to select { Tuner }. To record from an external device connected to this DVD Recorder, press REC SOURCE repeatedly to select the corresponding external input channel : { Front CVBS } { Front S-Video }, { DV }, { EXT 2 }.

5b

If a disc menu appears, use 1 2 3 4 keys to navigate within the menu, highlight a title and press OK to start playback.

Playback may start automatically. If not, press PLAY 2.

5c

To stop playback, press STOP 9.

4c

Press REC MODE to select a desired recording mode. It defines the picture quality and the maximum recording time for a disc.
Record Mode 1 Hour Mode 2 Hour Mode 4 Hour Mode 6 Hour Mode

To watch the TV programmes

Maximum Recording Time per Disc 1 hour 2 hours 4 hours 6 hours

Picture Quality High quality DVD quality-Standard Play VHS quality-Extended Play VHS quality-Super Long Play

5d

Press REC SOURCE to select { Tuner }, then use 3 4 keys to select the programme number.

4d

Press REC 0 to start recording.

GET PICTURE
Check the AV mode on TV. It may be called FRONT, A/V IN, or VIDEO. Choose the different modes using TV remote control. Or, use the TV remote control to select Channel 1 on TV, then press Channel down button until you get the picture. See your TV manual for more details.

4e

To pause the recording, press ;. To resume recording, press REC 0. To stop the recording, press STOP 9.

GET SOUND
Use the supplied scart cable to connect the DVD recorder to your TV, the picture and sound will output through the TV. Or, connect the AUDIO L/R (red/white) sockets at the back of the DVD recorder to the corresponding AUDIO input sockets on a TV, stereo system or receiver. Turn on the connected system and select the appropriate channel.

Wait until the message disappears from the display panel before you remove the disc.

NEED HELP? Read the accompanying User Manual or visit our website www.philips.com/support

Mechanical Instructions

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4.

EN 9

4.
4.1

Mechanical Instructions
Dismantling and Assembly of the Set
For item numbers please see the exploded view in Chapter 9. 4.1.2 Dismantling of the Front Panel Assembly 1) Remove the 3 screws 188 and release the 2 snap hooks on the side before removing the front assembly. 1

4.1.1

Dismantling of the DVD Loader Tray Cover 1) Inserting a minus screw driver and push the lever in the direction as shown in Figure 4-1 to unlock the tray before sliding it out.

Figure 4-1 2) Remove the Tray Cover as shown in Figure 4-2.

Figure 4-3 2) Remove the 5 screws 186 to remove the front plate 184 as shown in Figure 4-4.

Figure 4-2

2 Figure 4-4

EN 10
4.1.3

4.

3139 785 3093x

Mechanical Instructions
4.1.4 Dismantling of the Digital Board 1) Remove the 4 screws 272 to loose the Digital Board as shown in Figure 4-7.

Dismantling of the Basic Engine 1) Remove the Cover Tray (See 4.1.1). 2) Remove the 4 screws 260 to free the Basic Engine.

Figure 4-5 3) Place the Basic Engine in the service position by ipping the basic engine to the vertical position

Figure 4-7 2) Service Position can be achieved by ipping the Digital board to the Vertical Position as shown in Figure 4-8.

Figure 4-6

Figure 4-8 Note: The cable (just to transfer the service connection to the analog board) from socket 1101 can be removed and use for hyperterminal connection.

Mechanical Instructions
4.1.5 Dismantling of the Analog Board 1) Remove 5 screws 244 and 4 screws 252 and screw 230. 2) Remove 4 screws 270 and 3 screws 268. 3) Service Position can be achieved by ipping the analog board to the Vertical Position as shown in Figure 4-9.

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4.

EN 11

Figure 4-9 Note: Please cover the Live Area during trouble-shooting. (Figure 4-10)

Figure 4-10

Figure Live Area

EN 12

5.

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Upgrade Software & Repair Chart

5.
5.1

Upgrade Software & Repair Chart

Upgrade Software A. Preparation to upgrade rmware:
1. Unzip the zip-archive le 2. Start the CD Burning software and create a new CD project (data disc) with the following settings: File system : Joliet Format : MODE 1: CDROM Recording mode : SINGLE SESSION (TRACKAT-ONCE), FINALIZED CD Note: Long le name is necessary for the preparation of the upgrade disc 3. Place the content of the zip-archive into the root directory of the new CD project. 4. Burn the data onto a blank CDR or CD-RW

C. How to Restore Factory setting (Default setting)

1. Power up the set and with no disc in the tray 2. Press <System Menu> <Right> and 4x <Down> buttons on the Remote control to reach the Restore Factory setting option. 3. Press <OK> button and the TV connected to the set will display: System will reset to the Factory settings. Select OK to conrm or CANCEL to exit. 4. Select OK or CANCEL with the <Right> or <Left> button and press <OK> button to conrm. Note: All customers settings will be lost.

B. Procedure to apply the rmware upgrade:

1. Power up the set and open tray. 2. Insert the prepared Upgrade CDROM and close the tray. 3. The TV connected to the set will display: Software Upgrade Disc detected Select OK to start or CANCEL to exit 4. Select OK or CANCEL with the <Right> or <Left> button and press <OK> button to conrm. 5. The TV connected to the set will display: Upgrading Software, Please wait Do not switch off the power 6. When the upgrading process is successful the tray will open and the TV connected to the set will display: System is successfully upgraded. Remove disc from tray & reset system 7. Remove the Upgrade Disc and press <OK> button on Remote control to conrm 8. The TV screen goes blank and the Philips Logo screen appear again after the tray door has closed.

D. How to read out the rmware version to conrm set has been upgraded.
1. Power up the set and with no disc in the tray 2. Press <0009> and <OK> buttons on the Remote control 3. The TV connected to the set will display: DVDR3365_75_BT3_2, Drive: 43.02.11 Build: FAE6206 Apr 21 2005, 18:49:43 where DVDR3365_75 = Type/version BT3_2 = Application (Backend) rmware version 43.02.11 = Drive (Basic Engine) rmware version

Upgrade Software & Repair Chart 5.2 Repair Chart

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5.

EN 13

5.2.1 Completely Dead Set

EN 14

5.

3139 785 3093x

Upgrade Software & Repair Chart

5.2.2 Cannot Read Disk

5.2.3 Disk Unknown

Upgrade Software & Repair Chart 5.2.4 Audio No Sound (Playback)

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EN 15

EN 16

5.

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Upgrade Software & Repair Chart

5.2.5 Audio No Sound (TV & External Source)

Upgrade Software & Repair Chart 5.2.6 No Video Out Upon Power ON (Assume set is not dead)

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EN 17

EN 18

5.

3139 785 3093x

Upgrade Software & Repair Chart

5.2.7 No Video In Only

5.2.8 Tuner Not Functioning

Block Diagrams, Waveforms, Wiring Diagram.

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EN 19

6.

Block Diagrams, Waveforms, Wiring Diagram

Overall Block Diagram of the Set

Front Keyboards
CONTROL LINES

1201
CONTROL LINES, AND SUPPLY LINES

ANALOG BOARD

1922
AFCRI AFCLI CVBSFIN

9 7 5 4 3 2 1

CONTROL UNIT SLAVE MICROPROCESSOR VPD 16316GB-006

AUDIO L
CFIN YFIN

AUDIO R

1803
CONTROL LINES SCK,D_FM,D_HOST,RDY_FM,ATN_FM,HOST_RESET

CVBS

ANALOG AUDIO / VIDEO

S-VIDEO

7 9 11 12 13 14 15

1204
AINFR AINFL CVBSFIN

CFIN

21
YFIN

19

DIGITAL BOARD - DIMENSION

1551

1800

INPUT/OUTPUT PROCESSING & SOURCE SELECTION

TV-I/O

For Digital Video version only

1205
2 1

Digital Video Input IEEE1394

PHY
1512

FLASH
12 14 16 18 20 22

YUV-YC-CVBS
F439 F440 F441 F442 F443 F444

D_CVBS D_Y D_C D_V D_Y1 D_U

EXT1

1522

CVBS-YUV-Y/C
1
A_V A_U A_Y A_C
F438

21 19

ANALOG VIDEO

3 5 7 9

DVD+RW ENGINE D4.3

1600-1

A_YCVBS

DIG.VIDEO
1571

DOMINO DMN-8602 MPEG 2, AC3 CODEC TRAY CONTROL SERVO DISC

LASER

VIDEO INPUT PROCESSING

DIGITAL AUDIO DIGITAL AUDIO

AUX-I/O
1536
A_xCLK

21 20 18

A_BCLK A_WCLK A_DATA

1600 AUDIO ENCODER I2S

ADC
2 1

IDE BUS
40

IDE BUS

16 A_PCMCLK
D_xCLK

14 12

D_BCLK D_WCLK

11 D_DATA0 D_PCMCLK 9 D_KILL 7

DAC
AUDIO PCM I2S

EXT2

READ DDRAM WRITE

I2C

SPDIF_OUT

EEPROM
(OPTION)
RS232
1111
-5V GND ION +5V GND GND +12V GND +3V3 +3V3 +3V3 +3V3

S-VIDEO

CVBS
1501

A/V OUT

12 GND +12V GND +5V

AUDIO L/R

SERVICE

1600-2

PSU
PSU
12 5N GND 1 5V GND GND 12V GND 3V3 3V3 3V3 3V3

RF IN - ANTENNA

BUFFER
1403

TUNER
RF OUT - TV (LOOP THROUGH) DIGITAL AUDIO OUT

1934

FAN

(OPTION)

POWER SUPPLY
1804

MAINS AC

Block Diagrams, Waveforms, Wiring Diagram.

3139 785 3093x

6.

EN 20

Control Block Diagram Control Block Diagram Analog Board

FAN_CTRL

Fan

RC

Front Keys

2 I2C 3V3 INT I2C Bus Repeater Reset ASP Analog Slave Processor NEC uPD-16316GBT 2 1

35

HOST_Reset I2C 5V
DIGITAL BOARD DIMENSION

>=1 Reset 5VSTBY Supply VFT Display FRONT Board

DVDR

IDE0

Multi Sound Processor MSP34x5

RSA1,RSA2

Audio Switches HEF4052B

>=1 KILL AKILL

POWER_FAIL Frontend Tuner AIN_SEL0, AIN_SEL1 STBY

D_KILL

>=1 KILL BKILL

Power Supply

Block Diagrams, Waveforms, Wiring Diagram.

3139 785 3093x

6.

EN 21

Wiring Diagram
Interconnection Diagram Architecture
MAINS CORD 1 2 MAINS P MAINS L 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AIO 1600 GND DAOUT GND DAINOPT NO_CONNECT DAINCOAX MUTE GND D_PCMCLK GND D_DATA0 D_WLCK GND D_BLCK GND A_PCMCLK GND A_DATA GND A_WCLK A_BCLK GND 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 COM 1800 GND SCL0 SDA0 RDY_FM D_FM D_HOST GND SCK ATN_FM HOST_RESET CVBS_Y SW AIN_SEL0 AIN_SEL1 TU_DET FAN CTRL FBIN SC 2 pin 8_1 SC 2 pin 8_2 RC GND 1205 VIO 1206 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A_YG GNDV A_UB GNDV A_VR GNDV Y_FIN GNDV C_FIN CVBS_FIN GNDV C_REAR GNDV Y_REAR GNDV CVBS_REAR GNDV CVBS_TU GNDV D_CVBS GNDV D_C GNDV D_Y GNDV D_VR GNDV KB_FC 1802 FAN 1803 1 2 FAN_P FAN_N FRONT PCB KB_FC 1201

PDUDIG 1401 1 2 3 4 5 6 7 8 9 10 11 12 3V3 3V3 3V3 12VEF GND 12V GND GND 5V 5V GND 5N

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

14 13 12 11 10 9 8 7 6 5 4 3 2 1

GND SCK D_FM D_HOST GND RDY_FM ATN_FM HOST_RESET RC_IN 5VSTBY STBY(POWER_CTRL) IPFAIL VGNSTBY 12VSTBY PSUDRIVE 1402

8008 tbc mm

1 2 3 4

12VE GND GND 5VE

1 2 3 4 5 6 7 8 9

IPFAIL 1205 YFIN GND CFIN GND CVBS_FIN GND AL_FIN GND AINFR

to be confirmed if 8008 and 8013 needs to be combined

14 13 12 11 10 9 8 7 6 5 4 3 2 1

GND SCK D_FM D_HOST GND RDY_FM ATN_FM HOST_RESET RC_IN 5VSTBY STBY(POWER_C IPFAIL VGNSTBY 12VSTBY FAV 1300 YFIN GND CFIN GND CVBS_FIN GND AL_FIN GND AR_FIN

8013 tbc mm

ANALOG BOARD

1 2 3 4 5 6 7 8 9

D_YG
GNDV D_UB

Not for DVDR 3305 8001 120mm 8002 140mm 8003 140mm Front DV-In 8007 180m

Drive PSUDRIVE JST LC 1 2 3 4 12VE GND GND 5VE

to be confirmed if 8011 and 8012 needs to be 8012 140mm

USB 1401/1402 1 2 3 4 5VUSB1 USB1_D+ USB1_DGND For DVDR 3365 only

PSDIG 1501 1 2 3 4 5 6 7 8 9 10 11 12 3V3 3V3 3V3 3V3 GND 12V GND GND 5V 5V GND NC

AIO 1536 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND BCKI WCKI GND DAI (0) GND MCKI GND BCKO GND WCKO DAO (0) GND MCKO GND MUTE NC NC NC GND SPO GND

COM 1551 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND SCL0 SDA0 RDY_FM D_FM D_HOST GND FPSCK ATN_FM HOST_RESET VIOSW AIN_SEL0 AIN_SEL1 COM_ARST FAN CTRL FBIN SBS0 SBS 1 FPIR GND

1522 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

VIO 1521 VIA_GY GNDV VIA_BPb GNDV VIA_RPr GNDV VIA_SY_FR GNDV VIA_SC_FR VIA_CVBS_FR GNDV VIA_SC_RE GNDV VIA_SY_RE GNDV VIA_CVBS_RE GNDV VIA_CVBS_TU GNDV VOA_CVBS GNDV VOA_SC GNDV VOA_SY GNDV VOA_RPr GNDV

IDE_ 1571

IDE_

DIGITAL BOARD

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

1 2 3 4 5 6 7 8
PH2mm 1512 1 2 3 4 5 6 TPBn TPB GND TPAn TPA GND 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

RESETn
GND DD[7] DD[8] DD[6] DD[9] DD[5] DD[10] DD[4] DD[11] DD[3] DD[12] DD[2] DD[13] DD[1] DD[14] DD[0] DD[15] GND Keypin DMARQ GND DIOW_n GND DIOR_n GND IORDY CSEL DMACK_n GND INTRQ IOCS16 DA1 PDIAG_n DA0 DA2 CS0_n CS1_n DASP_n GND

8010 280mm

VOA_GY
GNDV VOA_BPb 1 2 3 4

USB 1502 5VUSB1 USB1_D+ USB1_DGND

For DVDR 3365 only

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

RESETn GND DD[7] DD[8] DD[6] DD[9] DD[5] DD[10] DD[4] DD[11] DD[3] DD[12] DD[2] DD[13] DD[1] DD[14] DD[0] DD[15] GND Keypin DMARQ GND DIOW_n GND DIOR_n GND IORDY CSEL DMACK_n GND INTRQ IOCS16 DA1 PDIAG_n DA0 DA2 CS0_n CS1_n DASP_n GND

1 2

STDBY KEY 0100 KEY1 KEY2

8014 220mm

1 2

STDBY KEY 1302 KEY1 KEY2

Block Diagrams, Waveforms, Wiring Diagram.

3139 785 3093x

6.

EN 22

Waveforms

Waveforms of Analog Board

F204 BOUT F206 GOUT F207 ROUT F209 YCVBS_OUT1 F417 VDrain (No Disc) F417 Vdrain(Standby) F602 CVBS

F604 Y_OUT

F605 C_OUT

I110 SIFOUT

I303 AFER

I304 AFEL

I310 ARADC

I311 ALADC

I315 AOUT1L

I317 AOUT1R

I407 Vgate (No Disc)

I407 Vgate (Standby)

I409 VSource (No Disc)

I409 VSource (Standby)

I719 ALDAC

I721 ARDAC

I906 Tstpoint

7500MSP XTAL IN

7500MSP XTAL OUT

Block Diagrams, Waveforms, Wiring Diagram.

3139 785 3093x

6.

EN 23

Waveforms of Digital Board

IC 7211 PIN 45 IC 7211 PIN 46 IC 7401 PIN74 IC 7401 PIN75 T121

T122

T351 IC7301 PIN 42

T352 IC 7301 PIN 43

T525, T526,T529 CVBS_TU, CVBS_RE,CVBS_FR

T527,T531,T535 SY_RE,SY_FR, CY

T528,T530 SC_RE, SC_FR

T532 BPr

T533 BPb

T537 BCK

T538 WCK

T539 DA

T540 MCK

Block Diagrams, Waveforms, Wiring Diagram.

3139 785 3093x

6.

EN 24

Test Points Overview for Analog Board

Analog Board TestPoint.pdf 2005-07-15

Block Diagrams, Waveforms, Wiring Diagram.

3139 785 3093x

6.

EN 25

Test Points Overview for Digital Board

Digital Board TestPoint.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 26

7.

Circuit Diagrams and PWB Layouts

Analog: Frontend Video (FV)

A
from PS
5VSTBY 5V 33VSTBY 5V 5V_FV 5100

B
5VSTBY 5V 33VSTBY

B
2101 10n 3102 1K0 2102 100n 5V_FV

7100 BC857BW I101 3100 100R

not used

CVBS_TV
to IOV

I100

3101

3103

47K

100R

5V_FV

D
3104 47K 2103 22n 33VSTBY

5101

19 MT2

18 MT1

not used

I111

10u

0803 H2 1100 G1 2100 C2 2101 C3 2102 B6 2103 D4 2104 E5 2105 E6 2106 F5 2107 G3 2108 G3 2109 H5 2110 H5 2145 F5 3100 C4 3101 C4 3102 B5 3103 D4 3104 D3 5100 B2 5101 E6 5102 F3 5103 G4 5104 G5 5105 G5 7100 C5 I100 C5 I101 C4 I102 F5 I103 G5 I104 G5 I105 G6 I106 G6 I107 E2 I108 F2 I109 G2 I110 F3 I111 E5 c710 G1

47u 6.3V

2100

22u

F
1100 TMQZ2

I109

5103
Bead

2107

100n

2108

20

21

5VSTBY

MT3

MT4

VIDOUT AFT GND2 VTU NC5 MB RFAGC SDA SCL GND1 SIFOUT AOUT NC4 NC3 NC2 NC1 BB

E
17 16 15 14 13 12 11
10 9

4u7 50V

2104

2105

I107 5V_FV I102 22u 25V

TUNER

2106

2145

I108 I110 SIF1

to MSP

10n

50V

8 7 6 5 4 3 2 1

5102

Bead

10n

c710

I103

5104
Bead

I105 SDA_5V
from/to CU

1u0

I104 GND_TU
not used

5105
Bead

I106 SCL_5V
from CU

BARCODE 0803

not used

2109

2110

47p

47p

Frontend Video FV
3139 243 31893 2005-04-13

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 27

Analog: Video In / Out (IOV)

1
from PS
12VSTBY 5VSTBY 5V 5NSTBY

2
from CINCH

4
YCVBSOUT1

9
CVBSOUT2 YCVBSIN2

10

11

12

13

14

MT2 1201-3
P50 (NC) AOUT1L AOUT1R to IOA,MSP to IOA,MSP FBOUT from/to CU A IN1R ROUT GOUT BOUT AIN1L

S2_FS_I

from MSP

AOUT2L

RCIN

AIN2R

AIN2L

MT2

MT1
GND

AIN2R

AOUT1R

AOUT1L

from IOA

from IOA

NC

E1

AIN1R

AIN1L

035 0 8081 90

100R

100R

100R

12VSTBY 5VSTBY

5V

5NSTBY

5NESD

1201-1 ROW_A 035 0 8081 90

3202

3203

19B

17B

14B

18B

21A

20A

19A

18A

12A

17A

16A

15A

14A

13A

11A

10A

16B

15B

13B

10B

21B

20B

12B

11B

9B

8B

4B

2B

9A

8A

6A

5A

4A

7A

3A

2A

1A

1B

7B

6B

5B

3B

100R

3200

3201

E2

AOUT2R

AIN2L

to IOA

to IOA

from MSP

CVBSIN1

8SC1

G ND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GIN

AOUT2R

AOUT2L

5NESD

A
1201-2 ROW_B

100K

BZX384-C12

150R

3216

3215

3217

100K

2207

470p 6215

2209

470p 6217

B
12VSTBY 7202 BC847BW

1%

1%

1%

B
S2_FS_I

75R

75R

5NESD

5NESD 5NESD 5NESD 5NESD

5NESD

75R 1%

1%

1%

5NESD

5NESD 3221 BZX384-C6V8

5NESD 75R

6220

3222 820R

BZX384-C12

5V

BZX384-C12

5NESD 150R 6221 3225

150R

3228

8SC2_1 3230 3233 3K9 22K 7203 BC847BW

3227 390R 3229 27K

5NESD 5VSTBY 75R 1%

7205 BC847BW

5200

10u

3234

39K

5V

3239

I200 5VSTBY 100n 2212 2211 100K 3238 47u 6.3V 5201

4K7

7206 BC847BW

5VSTBY

D
3240 3242 33K 150K

10u

8SC2_2 3243 56K 7208 BC847BW

2213 100n 2214 100n

I201 47u 6.3V

3245

30

20

36

VCCB-REC

VCCB1

VCCB2

VCCB3

VDD

VCC

24

32

7210 STV6618

Video Aspect ratio Detection

9 I202 10 I203 11 4 I204 6 7 2218 1u0 2221 1u0 2225 1u0 2227 47n 3250 27K 2217 D_VR 1u0 2219 1u0 2222 1u0 D_Y 5V 5V 5V
to CINCH to CINCH

I220 31

E
3246 75R 1%

I219 29 I218 27 I217 34 I216 33 150R 2226 1u0 3247 2224 1u0 I215 41 40

VIDEO SWITCH R|PR|COUT-TV MATRIX R|PR|CIN-ENC

G|YOUT-TV B|PBOUT-TV FBOUT-TV Y|CVBSOUT-TV CIN-TV Y|CVBSIN-TV DECV G|YIN-ENC B|PBIN-ENC CVBSIN-ENC CIN-ENC YIN-ENC

D_YG
to CINCH

D_UB
to CINCH

D_CVBS
to CINCH

FROM FV
3253 10K

CVBS_TV 470p

Y|CVBSIN-TUN Y|CVBSOUT-REC CIN-TUN COUT-AUX

I205 21

2230 1u0

43

23 25 100n I222

I214 28 I213 I212 DGO2 5VSTBY DGO4 10K 3254 I211 42 44 2 14 16 18 I208 GNDB-REC SDA_5V 7217 BC857BW S2_FS_I 100K 3267 8SC1 38 I207 37 SDA SCL C-GATE 1 2 3 DIGOUT 4 5 6

I223

1K0

3251

3257 100R 7213 BC847BW I224 3258 22K 3259 2236 I225

2229

100n

5VSTBY

2228

Y|CVBSOUT-AUX

7212 BC857BW

R|PR|CIN-AUX G|YIN-AUX B|PBIN-AUX FBIN-AUX Y|CVBSIN-AUX

17 15 13 I206 35 19

2233 1u0 2235 1u0 2237 1u0 2234

2232

150R

I209

3261 150R 3262 C_FIN CVBS_FIN CVBS_TV 150R Y_FIN

3272 150R 1% 3273 150R 1% 3274 150R 1% 3275 150R 1% 3276 9160 9161 9168 150R 3269 F239 F237 F238 GND_V F234 F233 F236 F235 150R 1% 3277 F232 F231 F230 F229 F228 F226 F227 F225 F224 150R 1% F240 1204 24FMN-BTRK-A GND_D

3260

100n

I210

1u0

150R

G
CRout
to CINCH

SCL_5V

22

26

GNDB

12

39

GNDD

GND2

GND1

FROM CU

H
9239 16V 10u Y_FIN 1205 YFIN GND CFIN GND CVBSFIN GND AINFL GND AINFR 1 2 3 4 5 6 7 8 9 B9B-PH-K 4240

5VSTBY

3268

100K 3252 10K

*
3270 10K

H
c200 GND_D

* *

2239 3271 DGO2 9241 C_FIN 22K

7219 BC847BW

Video In/Out IOV

*
F250 F253 F251 F252

2240 1u0

CVBS_FIN 2241 AINFL AINFR

FBIN

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

16V 10u

#
SCART FS (Pin 8) In/Out loop through

I
from/to DIGTAL BOARD

to CU

GND_V

A_YG GND_V A_UB GND_V A_VR GND_V Y_FIN GND_V C_FIN CVBS_FIN GND_V C_REAR GND_V Y_REAR GND_V CVBS_REAR GND_V CVBS_TV GND_D D_CVBS GND_D D_C GND_D D_Y GND_D D_VR GND_D D_YG GND_D D_UB

*
2 3 4 5 6 7 8 9

3139 243 31893

2005-04-13

1201-1 A8 1201-2 A14 1201-3 A9 1204 I12 1205 I1 1206 I10 2201 B3 2202 B12 2203 B12 2207 B7 2209 B8 2211 D8 2212 D8 2213 D8 2214 D7 2215 E9 2216 E9 2217 E9 2218 E9 2219 E9 2221 E9 2222 E9 2224 F7 2225 F9 2226 F6 2227 F9 2228 F7 2229 F14 2230 F11 2232 G13 2233 G9 2234 G9 2235 G9 2236 G14 2237 G9 2239 I3 2240 I3 2241 I3 3200 A13 3201 A14 3202 A8 3203 A8 3206 B4 3207 B9 3208 B11 3209 B11 3210 B12 3211 B13 3213 B7 3214 B8 3215 B4 3216 B5 3217 B5 3218 B4 3219 B5 3221 C10 3222 C4 3224 C12 3225 C11 3226 C13 3227 C3 3228 C11 3229 C3 3230 C13 3233 C13 3234 D3 3235 D10 3236 D10 3238 D4 3239 D13 3240 D4 3242 D3 3243 D13 3245 D13 3246 E7 3247 F7 3250 F13 3251 F13 3252 H4 3253 F4 3254 G7 3257 F13 3258 G13 3259 G14 3260 G13 3261 G9 3262 G10 3267 H5 3268 H5 3269 H10 3270 H5 3271 I4 3272 G12 3273 G12 3274 H12 3275 H12 3276 H12 3277 H12 4240 I3 5200 D8 5201 D9 6200 B4 6201 B4 6202 B5 6203 B5 6204 B5 6205 B6 6206 B9 6207 B10 6208 B11 6209 B11 6210 B12 6211 B13

6215 B7 6217 B8 6218 B6 6219 C10 6220 C12 6221 C11 7202 C3 7203 C14 7205 D3 7206 D4 7208 D14 7210 E8 7212 F14 7213 G13 7217 H5 7219 I5 9160 H10 9161 H10 9168 H10 9239 H3 9241 I3 F200 A7 F201 A7 F202 A7 F203 A6 F204 A6 F205 A6 F206 A5 F207 A5 F208 A5 F209 A4 F210 A4 F211 A4 F212 A12 F213 A12 F214 A12 F215 A12 F216 A11 F217 A11 F218 A11 F219 A10 F220 A10 F221 A10 F222 A10 F223 A9 F224 H12 F225 H12 F226 H12 F227 H12 F228 H12 F229 H11 F230 H11 F231 H11 F232 H11 F233 H11 F234 H11 F235 H11 F236 H11 F237 H10 F238 H10 F239 H10 F240 I12 F250 I2 F251 I2 F252 I2 F253 I2 I200 D8 I201 D9 I202 E9 I203 E9 I204 E9 I205 F9 I206 G9 I207 H7 I208 G7 I209 G7 I210 G7 I211 G7 I212 G7 I213 G7 I214 F7 I215 F7 I216 E7 I217 E7 I218 E7 I219 E7 I220 E7 I222 G13 I223 F13 I224 G13 I225 G14 c200 H14

P50 (NC)

FBIN

G ND

GND

GND

F211

F223

F204

F202

F200

F222

GND

NC

BIN

F209

F205

F216

F215

F214

F203

F213

F210

F207

F220

F219

F206

F201

F208

F221

620 C BZX384-2 6V8

BZX384-C6V8

BZX384-C6V8

BZX384-C6V8

BZX384-C6V8

BZX384-C12

BZX384-C12

BZX384-C12

F218

F217

3208 BZX384-C12

BZX384-C12 3210

F212

3209 BZX384-C12

BZX384-C12

75R 1% 6200

not used

3206

2201

6204

100p

6201

6203

6206

6205

6207

3207

100K

1% 75R

BZX384-C12 3213

BZX384-C12 3214

3218

3219

75R

6218

6219

100K

6209

6208

470p 6210

2202

2203

470p 6211

3211

75R

75R

3226

150R

3235

3236

3224

75R

2215

100n 2216

1206 30FMN-BTRK-A

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

10

11

7 6 5 4 3 2 1

12

13

3K9

3K3

1%

14

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 28

Analog: Audio In / Out (IOA)

5
5VSTBY

8
from PS
5VSTBY 5NSTBY

2320

2321

A
I305 RSA2 RSA1
from MSP

16

7302 HEF4052B 10 9

5VSTBY 2311 VDD 3310 100n 5 2310 100p 6 4 2312 100n 5NSTBY 3 5VSTBY 7300-2 MC33078D 7 8 5VSTBY 5NSTBY

0 0 4X 1 3 G4 0 1 2 3 0 1 2 3

I306

6 12 14 15 11 1 5 2 4

I310 ARADC
to DAC_ADC

MDX

1K0 13

2300 AINFR
from IOV

I300

1u0 I301 2302 1u0 2303 1u0 2304 1u0 2305 1u0 I307 I320 100K 100K 3302 3303

2301 AINFL
from IOV

1u0

VEE VSS

AIN2L
from IOV

3311 2313 100p 1K0

3 2

7300-1 MC33078D 1

I311 ALADC
to DAC_ADC

I309

AIN2R
from IOV

100K

100K

3300

3301

I318

AIN1L
from IOV

5NSTBY 5VSTBY 5VSTBY 16 7303 HEF4052B 10 9

5NSTBY

I302

AIN1R
from IOV from CU from IOA

2306 1u0 2307 1u0 2308 1u0 2309

AFER
from MSP

6 12 14 15 11 1 5 2 4

G4 0 1 2 3 0 1 2 3

5 6

I303

0 0 4X 1 3

VDD 3312 I312

2314 100n 7301-2 MC33078D 7 false type

I308

3313 220R

I314

2317 10u 16V 820R 100K

I315 7304 BC817-25W 3315 3316 AKILL 4K7

from DAC_ADC

I304

MDX

1K0 13

AOUT1L
to IOV

AFEL
from MSP

ALDAC
from DAC_ADC

I313

1n0 3314

2316

2315 100n 5NSTBY VEE VSS 7 8

ARDAC
from DAC_ADC

1u0 100K 3306 100K 3307 100K 3308 100K 3309 100K 100K 3304 3305 5V

5VSTBY

5VSTBY 3323 10K

false type

3322

10K

* E
AIN_SEL1

3317 5NSTBY 1K0 I316

3 2

7301-1 MC33078D 1

3318 220R

2319 10u 16V 820R 100K 2318 1n0 3319 3320

I317 7305 BC817-25W 3321 4K7 AOUT1R

to IOV

7307 BC847BW 7306 BC847BW

*
5VSTBY

5NSTBY

5V

from CU

7309 BC847BW AIN_SEL0 7308 BC847BW

Options
1 2

Audio In/Out IOA

3139 243 31893 2005-04-13

2300 B1 2301 B1 2302 C2 2303 C2 2304 C2 2305 C2 2306 D2 2307 D2 2308 D2 2309 D2 2310 B6 2311 A7 2312 B7 2313 C6 2314 C7 2315 D7 2316 D7 2317 D8 2318 E7 2319 E8 2320 A8 2321 A9 3300 C3 3301 C3 3302 C4 3303 C4 3304 E2 3305 E2 3306 E2 3307 E2 3308 E3 3309 E3 3310 B6 3311 C6 3312 D6 3313 D7 3314 D8 3315 D8 3316 D9 3317 E6 3318 E7 3319 E8 3320 E8 3321 E9 3322 E4 3323 E4 3324 F4 3325 F4 7300-1 B7 7300-2 B7 7301-1 E7 7301-2 D7 7302 A5 7303 C5 7304 D9 7305 E9 7306 E3 7307 E4 7308 F3 7309 F4 I300 B2 I301 B2 I302 C2 I303 D2 I304 D2 I305 A4 I306 B4 I307 C5 I308 D5 I309 C2 I310 B9 I311 C9 I312 D6 I313 D6 I314 D8

I315 D9 I316 E6 I317 E9 I318 C2 I320 B2

47u 6.3V

3325

3324

10K

10K

47u

6.3V

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 29

Analog: Power Supply (PS)

1 2 3 4 5 6 7 8 9 10 11 12
F424 33VSTBY

13
1406 500mA T 9401 F425

14
12VSTBY

F421

6408 STPS3L60-C2 F422

5403 22u

7405 SI2306DS 12VE

3437 330u 2417 33VSTBY

12V
100K 47K 7408 SI2306DS 3434 3435 3K3 I429

2416

1m0

A
GND
3400 3M3 U74 3401 3M3 2415 2n2 2402 I426

A
U78 F427 STBY 7410 PDTC124EU 9403

100K

3429

3431

3432

GND

GND

220K

3436

3K3

47K

I428

I427 7406 BC847BW 220K

GND 7407

7409 BC847BW

HI = ON LOW = STANDBY
DD_ON

2437

GND I430

GND

B
1403 1405 PTF/65 100V F400 F401 1404 5ET 1400 3402 680K 2400 220n 1 2 3 2 HF2022R 5401 4 I404 1 F402 F405 220R I400 3403 I401

PDTC124EU 1n0

B
F430 1407 1000mA T 3447 1K0 3448 1K0 3449 1K0 3450 2K7 1K0 F431

GND
I402 6400 1N4006 6401 I403 1N4006 F419 3482 1K0 3483 1K0 3484 1K0 3485 3438 1K0 3K9 6 2 3439 2K2 3440 100R

GND
7411 STP16NF06FP

GND 5VSTBY 12VSTBY

3446 3441 3442 470R 3443 470R 2419 3445 1K0 7413 STP16NF06FP 3454 6 3 5 2423 3458 1n0 3K9 3455 470R 3456 470R 3457 2K2 1n0 3444 2K2

GNDHOT
6402 1N4006 6403 2403 1n0

2418

GND GND
6409 U79 SB340 6410 F428 SB340

1n0

5Vreg

3 7412-1 BC846U 7412-2 BC846U 1 4

3K9 5

GND

2405

330K

330K

330K

3406

F403

F404

3404

3405

47n

1N4006

B2P3-VH 2404
400V

GND
5404 22u 1408 T 2000mA 2421 560u 3451 3K9

C
GND 12V
3459 2K7 5V_FE 3460 I446 4401 F433

I405

5V

GNDHOT

c300

2422 U80 1n0 3452 2K2

2 3453 100R

GND 5402

7414-2 7414-1 BC846U BC846U 4 1

12VE
10K

D
2407
7401 STP3NK60ZFP

5VE

GND
1K0 5405 F437 1409 T 4A 2425 560u F439

47p

GND

I407 1401 3V3SW1 3V3SW2 3V3SW 3 12VEF 4 GND 5 12V 6 GND 7 GND 8 5V_BE 9 5VEF 10 GND 11 5N 12 F406

5400 SRW28EC9 U60 NC 5 5 1 4 12 13 17 18 14 16 11 10 12 13 17 18 14 16 11 10 F444 6413 15 9 15

F435

6411 STPS5L40 F436

5V_BE

GNDreg GND 3Vreg

GND

7415 SI2306DS

D
3V3SW

2u2

2424

to Digital Board

F413

F441

6412 STPS5L40

2406

3461

1N4003

0R47

0R68

3409

3410

6405

100R

3408

F412

12VE GND GND GND

F408

3K9

6 2

3 5

12V
F410

GND GND
2426 1n0 3462 2K2

F407

GND

5V_BE 5V_FE 7402 SI2306DS

3407

GNDHOT

GNDHOT
2408

GNDHOT

GNDHOT
7

8 6 7 2 3

3463 100R

7417-1 7417-2 BC846U BC846U 1 4

3V3SW

18K

220R 3466 120R 3467

1K5

1n0

9400

3469

I410

1m0

3V3SW

5Vreg

7416 STS9NF30L 3464 3465

12V

2427 1n0

GND
F445 5406 22u F447 1410 T 125mA 100u 2429

GND

3468 1K0

2K7

B12P-PH-K

GND
F443

300V

12VE
10K F411

U61

1u0 3411 3K3

U62

I412 2 F417 3

5NSTBY

6 7 8

5N SMPS CONTROL

SBYV27-200

2428

1m0

5N
3470 2430 100n 10K 7418 BC337-25 6417 BZX384-C6V8 3472 1K0

VCC

GNDHOT

13,9V

GNDHOT

GND GND
BAS316

12V
U84 7419 BF422 3473 1K0 U82 3474 1K0 U85 F451

F
33VSTBY

GND

F414
2

7400 TEA1507P

6414

CTRL DEM ISENSE

GND

GND
I435

3471 1K5

to Basic Engine

5V

1402 12VE GND GND 5VE 1 2 3 4

2431

2433

2434

100n

U70

2432

U64

F409 F416

5VE

B4B-EH-A

560K

5VSTBY
2K2

22u

GND GND

12VE

1M0

BAT54 COL 3416

2n2

6419

2n2

10n

F415

1V

6416 1N4935

BZX79-B33

3415

U63

6406

6415

F449

5407

6418 1N4935 U83

3475 10K

3476 10K

I440

2409

GNDHOT

3424

GND
3427 22K

GND GND
12VSTBY 12VSTBY F453 3479 47R F455 7423 BC857BW F456

GND

GND

5Vreg 3425 U65 2K2 3418 U67 7403 1K0

1411 T 125mA 9402

F459

VGNSTBY

4400 22u 50V 100n 2410 2411

7420 3426 4K7 3428 I424

I423 3477 4K7

GND1

GND 3 GNDHOT GNDHOT

U66 100n 3417 2412 4K7 TCET1108 U68

BC847BW BC847BW 10R I441 BZX79-B8V2

2
3419 470R 1 2413 100n U69 3420 10R

7422 BC547B 3480 2K2 I444 3481 2K2 100n 2436 6422 I445 BZX384-C27

GND
3421 5K6

5Vreg

2435

100n

GND
2414

100n

6420

U71

GND

7404 TL431ACZ

F452

I420 R 3

GND
BAS316 6421

I443

I442

100R

3478

7421

GND 8VSTBY

GNDHOT GNDHOT
3422 3423 4K7 56K F418 2

GND POWER_FAIL

I
GND

GND

GNDreg GNDreg GNDreg

Power Supply PS
8 9 10 11 12

3139 243 31893

2005-04-13

U60 E5 U61 F3 U62 F5 U63 G4 U64 G5 U65 H5 U66 I3 U67 H6 U68 I6 U69 I7 U70 G8 U71 H8 U74 A6 U78 A13 U79 C9 U80 D9 U82 F12 U83 G12 U84 F12 U85 F13 1400 C1 1401 D1 1402 G1 1403 B2 1404 B2 1405 B3 1406 A13 1407 B12 1408 C10 1409 D10 1410 F9 1411 H13 2400 C3 2401 D2 2402 B4 2403 C6 2404 C5 2405 C6 2406 E4 2407 D5 2408 E4 2409 G6 2410 H4 2411 H5 2412 I5 2413 H7 2414 I8 2415 B7 2416 A9 2417 A10 2418 C9 2419 C11 2420 D9 2421 D9 2422 D9 2423 D12 2424 E9 2425 E10 2426 E11 2427 E12 2428 F8 2429 F9 2430 F10 2431 G9 2432 G11 2433 G12 2434 G13 2435 H9 2436 I12 2437 B10 3400 A6 3401 A6 3402 C3 3403 B4 3404 C5 3405 C5 3406 C6 3407 F2 3408 E3 3409 E4 3410 E5 3411 F4 3412 F5 3413 F5 3414 F6 3415 G4 3416 G4 3417 I4 3418 H6 3419 H6 3420 H7 3421 H7 3422 I7 3423 I7 3424 G8 3425 H8 3426 H7 3427 G8 3428 H8 3429 A10 3430 B10 3431 A10 3432 A11 3434 A12 3435 A12 3436 A11 3437 A11 3438 B9 3439 C9 3440 C10 3441 C11 3442 C11 3443 C11 3444 C11 3445 C11 3446 C12

3447 B13 3448 B13 3449 B13 3450 B13 3451 D10 3452 D10 3453 D10 3454 D12 3455 D12 3456 D12 3457 D12 3458 D11 3459 D12 3460 D13 3461 E11 3462 E11 3463 E11 3464 E12 3465 E13 3466 E13 3467 E13 3468 E12 3469 E13 3470 F10 3471 F11 3472 F12 3473 F12 3474 F13 3475 G12 3476 G13 3477 H9 3478 H11 3479 H12 3480 H11 3481 H12 3482 B8 3483 B8 3484 B8 3485 B8 4400 H2 4401 D13 5400 D7 5401 C4 5402 D6 5403 A9 5404 C9 5405 D9 5406 F9 5407 G9 6400 B4 6401 B5 6402 C5 6403 C4 6404 D5 6405 E5 6406 G4 6407 H5 6408 A8 6409 C8 6410 C8 6411 D8 6412 E8 6413 F8 6414 F8 6415 G8 6416 G11 6417 F11 6418 G11 6419 G13 6420 H10 6421 I10 6422 I12 7400 G3 7401 D4 7402 E2 7403 H6 7404 I6 7405 A10 7406 B10 7407 B11 7408 A12 7409 A12 7410 A13 7411 B10 7412-1 C10 7412-2 C11 7413 C11 7414-1 D11 7414-2 D11 7415 D13 7416 E12 7417-1 E11 7417-2 E12 7418 F11 7419 F13 7420 H8 7421 H9 7422 H11 7423 H12 9400 E1 9401 A13 9402 H13 9403 B13 F400 B1 F401 B2 F402 B3 F403 C1 F404 C2 F405 B3 F406 E1 F407 E1 F408 E2 F409 G1 F410 E2 F411 F2 F412 E1

F413 E4 F414 F4 F415 G1 F416 G1 F417 F6 F418 I6 F419 B6 F421 A8 F422 A9 F424 A13 F425 A13 F427 A14 F428 C8 F430 B12 F431 B12 F433 C13 F435 D8 F436 E9 F437 D9 F439 D10 F441 E8 F443 F13 F444 F8 F445 F8 F447 F9 F449 G9 F451 F14 F452 I9 F453 H11 F455 H12 F456 H13 F459 H14 I400 B3 I401 B4 I402 B5 I403 B5 I404 C4 I405 C6 I407 D4 I410 E6 I412 F6 I420 I7 I423 H8 I424 H8 I426 B7 I427 A10 I428 A11 I429 A12 I430 B12 I434 F8 I435 F10 I440 G13 I441 H10 I442 H11 I443 I10 I444 H12 I445 H12 I446 D13 c300 D9

G ND

2u2 50V 3430

68u

2420

2V

820R

BYT42M

6404

820R

DRIVER HVS DRAIN

820R

3412

3413

3414

I434

BAV21

6407

BZX384-C5V6

3 4 5

1m0

470p

2401

13

14

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 30

Analog: Multi Sound Processing (MSP)

1
from PS

2
5V

4
RSA1 RSA2

6
8VSTBY

8
5VSTBY

8VSTBY

3518

10K

3511 3509 10K 3510 10K 12K 10u 25V 2513 10u 25V 2511 47u 16V 2512 100n 2514 2510 3512 22K 10n

7501 PDTC124EU
from CU

10u 25V

2500

A
8VSTBY 5V

I514 I515

I512

I513

I516

7504 BC847B 5V

STBY

7500 MSP3415G

6500

from/to CU

3502 100R

100R

I501 13 14 15 16 17 21

from/to CU

STBYQ I2S_CL

10u

11 I518

5501

SDA_5V

I2C_DA

I517

4K7

SCL_5V

I2C_CL

BAS316 3513

3501

I500 12

5V

I2S_WS I2S_DA_OUT

DVSUP

19 I519

RESETQ I2S_DA_IN1

22

2501 GND_TU 56p 2502 56p

I502 3 I503 2 ANA_IN+ ANA_IN-

DEMODULATOR

SIF1
from FV

S1...4 FM1 FM2 NICAM A NICAM B

LOUDSPEAKER R LOUDSPEAKER L

D/A D/A

DACM_R

26

LOUDSPEAKER
DACM_L 27

10u

I2SL/R

I2SL/R

2515

I2S_DA_IN2

C
2517 2518 1n0 1n0 AFER
to IOA

43

MONO_IN

IDENT

IDENT

DFP
I521 AGNDC 36 4u7 50V

AFEL
to IOA

2519

2520

D
2503 AIN1R
from IOV

I504

3503 1K0

I505 41 I507 40 I509 38 SC2_IN_R SC1_IN_L SC1_IN_R

A/D

SCART-R

HEADPHONE L
I522 SC1_OUT_R 30 I523 2523 I524 3514 220R 3515 220R I526 AOUT2R 2525 1n0 10u 25V I525 2524 10u 25V 2521 1n0 2522 1n0 I528
to IOV

2u2 50V 2504 2u2 50V 3505 2K2 3506 I510 I508

I506

3504 1K0

AIN1L
from IOV

SCART-R SCART-L

D/A D/A

2505 1u0 2506 1u0

ARDAC
from DAC_ADC

SC1_OUT_L

31

I511 37 SC2_IN_L

10n

A/D

SCART-L

HEADPHONE R

ALDAC

7502 BC817-25W 3516

VREF1

VREF2

AVSS

AVSUP

AHVSS

DVSS

XTAL_IN

XTAL_OUT

12K 3508

3507

12K

4K7

from DAC_ADC

2K2

SCART Switching Facilities

E
AKILL
from DAC_ADC

TP

NC
23 24 28 32

5V 5500 10u 2507 100n 2508 3p3 1500 2526 18M432 2509 3p3

I527 AOUT2L
to IOV

I529 1n0

7503 BC817-25W

Multi Sound Processor MSP

1 2 3 4 5 6 7 8

3139 243 31893

2005-04-13

1500 F6 2500 A2 2501 C2 2502 C2 2503 D1 2504 D1 2505 E2 2506 E2 2507 F5 2508 F6 2509 F7 2510 A6 2511 A6 2512 A6 2513 A7 2514 A7 2515 C8 2516 B8 2517 C7 2518 C7 2519 D7 2520 D7 2521 E7 2522 E7 2523 D7 2524 E7 2525 E8 2526 F8 3501 B2 3502 B1 3503 D2 3504 D2 3505 E1 3506 E1 3507 E1 3508 E1 3509 A4 3510 A4 3511 A7 3512 A7 3513 B8 3514 D8 3515 E8 3516 E9 3517 E9 3518 A8 5500 F5 5501 B8 6500 B7 7500 A3 7501 A9 7502 E9 7503 F9 7504 A8 I500 B2 I501 B2 I502 C2 I503 C2 I504 D2 I505 D2 I506 D2 I507 D2 I508 E1 I509 E2 I510 E1 I511 E2 I512 A4 I513 A4 I514 A6 I515 A6 I516 A6 I517 B7 I518 B7 I519 B7 I521 D7

I522 D7 I523 E7 I524 D8 I525 E8 I526 D8 I527 F8 I528 E9 I529 F9

18

10

33

ADR_CL

D_CTR_IO1

D_CTR_IO0

ADR_SEL

TESTEN

VREFTOP

AHVSUP

CAPL_M

34

42

ASG

2516

100n

3517

29

44

25

35

39

20

4K7

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 31

Analog: Audio Converter (DAC_ADC)

8
from PS

9
3V3SW 5V 5VSTBY 5NSTBY

12VSTBY

F713

5VSTBY 5VSTBY 3702

5VSTBY 5VSTBY 3736 5700 3V3SW 7701 PDTA124EU I701 2714 BKILL
to cinch

A
12VSTBY 3716 100u 6.3V 2715 4R7 100n I723 2716 100n GND I715 7705 BC807-25W 12VSTBY 47u 16V 2721 3V3SW 2720 2717 11 17 20 5 4u7 50V 2719 100n 2718 GND 100n 3720 3K9 3V3SW 5V 5VSTBY 5NSTBY 10u

7700 PDTA124EU I700 AKILL

to IOA,MSP

B
5NSTBY GND GND BAS316 POWER_FAIL
from PS

B
A 3721 1K0

GND I702 6700 BAS316 4700

GND

6701 F700

DAINOPT
from DIGIO

F701 F702 5VSTBY 22FMN-BTRK-A GND GND 6703 BAS316

3V3SW

SDIN SCLK LRCK 3731 MCLK 100K I722

DAINCOAX
from DIGIO

7703 CS4351 1 2 3 4 10 8 3717 10K

192 kHz DAC

SDIN SCLK LRCK MCLK RST DIF0 SDA CDIN DIF1 SCL CCLK GND 16 6 VBIAS VQ AMUTEC BMUTEC AOUTA AOUTB DEM AD0 CS

12 13 19 14 18 15 9

22n

5NSTBY

VA

VA_H VD

VL

16V 47u 2722 2723 100n A

7706 BC847BW 2724 100n 3723

3722 3V3SW 4K7 10K

DAOUT 2713

3718

10K

4u7

3719

10K

to DIGIO

C
A I716 AMUTEC I717 BMUTEC

GND 22 DAOUT 21 GND 20 DAINOPT 19

GND F703 7702 PDTC124EU 3706 22R 3708 GND I706 3707 22R 3709 22R 2702 33p 2703 33p 2704 33p 2705 3711 22R 22R GND F711 22R 3713 GND I709 3714 10K I711 2 VREF BCK 3715 GND 10K I712 47u 6.3V 3V3SW 9014 3730 1K 0 1 6 7 I724 14 VINL SFOR PWON MSSEL VSSA 15 A GND I713 VRN 4 A GND VSSD WS 12 11 33p I708 I707 LRCK 5701 SCLK F708 F709 F710 3710 22R 3712 10u 3V3SW I710 SDIN GND I705 MCLK 3V3SW GND A

18 17 DAINCOAX DKILL 16 GND 15 14 D_PCMCLK 13 GND 12 D_DATA0 D_WCLK 11 10 GND D_BCLK 9 8 GND A_PCMCLK 7 6 GND A_DAT 5 4 GND A_WCLK 3 A_BCLK 2 1 GND 1700 2706 I703 GND GND

F704 F705 F706

I718

2725 50V 10u 3725 27K

3724 680R 2726

I719 ALDAC

F707

22R

A 3728 100u 6.3V 2711 7704 UDA1361TS 2712 100n 47K 16 I720 2727 50V 10u 3727 27K GND 13 A 3726 680R 2728 1n0 I721 ARDAC

VDDA

F712

A 8 3

SYSCLK VINR

24-BIT AUDIO ADC

DATAO

VRP VDDD

ARADC
from IOA

47u 6.3V

2707 ALADC
from IOA

I704

47u 6.3V

c700 A GND

Audio Converter DAC_ADC

1 2 3 4 5 6 7 8

3139 243 31893

2005-04-13

1700 E1 2700 B1 2701 B3 2702 D3 2703 D3 2704 D3 2705 D3 2706 E1 2707 E1 2708 F4 2709 F4 2710 E5 2711 E5 2712 D7 2713 C5 2714 B6 2715 B6 2716 A7 2717 B7 2718 B7 2719 B7 2720 B8 2721 B8 2722 B8 2723 C8 2724 C9 2725 D8 2726 D9 2727 D8 2728 E9 3700 B1 3701 B1 3702 A2 3703 C2 3706 D2 3707 D2 3708 D2 3709 D2 3710 D1 3711 D2 3712 D1 3713 E2 3714 E1 3715 E1 3716 A6 3717 C5 3718 C5 3719 C7 3720 B9 3721 B8 3722 C9 3723 C9 3724 D9 3725 D9 3726 D9 3727 E9 3728 D4 3729 F4 3730 F5 3731 C5 3736 A3 3737 B4 3738 B4 4700 B2 5700 A6 5701 D5 6700 B2 6701 B1 6703 C2 7700 A2 7701 A3 7702 C2 7703 B6 7704 D6 7705 B8

from/to Digital Board

7706 C8 9014 F5 F700 C1 F701 C1 F702 C1 F703 D1 F704 D1 F705 D1 F706 D1 F707 D1 F708 D1 F709 D1 F710 D1 F711 E1 F712 E1 F713 A8 I700 A1 I701 A4 I702 B2 I703 E1 I704 E1 I705 D4 I706 D3 I707 D3 I708 D3 I709 E5 I710 D6 I711 E5 I712 F5 I713 F5 I715 B8 I716 C8 I717 C8 I718 D8 I719 D9 I720 D8 I721 D9 I722 C5 I723 A6 I724 F5 c700 F9

100K 3701

22K

22K

3737 100K

2701 22K

22K 2700

3703

GND GND GND GND

4K7

3738

3700

22n

22n

2710

100n

3729

47K 2708

100n 2709

10

1n0

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 32

Analog: Digital In / Out 1 (DIGIO 1)

2
from PS

5V

5V

A
5V

A
I900 1u0 10V 100K 2900 2901 3904 10n

I901

7900-6 74HCU04D 12

14 1 7

13

B
3901 DAINCOAX
to DAC_ADC not used

B
100K 3905

3902 10K

100R 560R 3900

for DIGITAL IN only

F900

310360100162
1900 1 2 3 4

C
DAINOPT
to DAC_ADC

F901

F902 5V

for DIGITAL IN only

D
7900-1 14 3906 DAOUT I904
from DAC_ADC

2906 7901 3 I906 2904 100n 560R 3910 7 7 7900-2 74HCU04D 14 4 3 1 7 7900-5 74HCU04D 14 10 11 1 7 7900-4 74HCU04D 14 3913 8 1K0 2907 F907 100n 25V I908 2 1 6RG 6 4 150p 2905 100n F903 1901

D
3 2
1 YKC21-3416

I902

2902 100n

I903

3908 470R

74HCU04D I905 5 1 2 1

7900-3 74HCU04D 14 6 1

750R 100R 3907

F904

3911 75R 3912 82R

F905

DIGITAL OUT

0007 F2 1900 C9 1901 D9 2900 A4 2901 A4 2902 D2 2903 E4 2904 D5 2905 D7 2906 D8 2907 F8 3900 C2 3901 B3 3902 B4 3904 A4 3905 B4 3906 D1 3907 E1 3908 D3 3909 E3 3910 E4 3911 E7 3912 E7 3913 F6 3914 E8 4812 A4 6900 F9 7900-1 D3 7900-2 E4 7900-3 D4 7900-4 F4 7900-5 E4 7900-6 B3 7901 D6 F900 C9 F901 C9 F902 C9 F903 D8 F904 D7 F905 E8 F906 F8 F907 F8 I900 A4 I901 B3 I902 D1 I903 D2 I904 E3 I905 D3 I906 D4 I907 E4 I908 D6

470R

4812

3909

I907 2903 1n0

2K2

E
5V 3914 47R

F906

6900 2 1 3 VS IN GND JFJ1000

0007 BRACKET

1 7

OPTICAL OUT F

Digital In/Out DIGIO1

1 2 3 4 5 6 7

3139 243 31893

2005-04-13

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 33

Layout: Analog-Main Part (Top View)

Analog_Topview_3355_02.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 34

Layout: Analog-Main Part (Bottom View)

Analog_Bottomview_3355_02.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 35

Front: Front Panel

2
I103

3
12VSTBY 3104 330R 7102 BC337-25 3105

4
10u 25V

5
VGNSTBY 3108 10K

6
1203 HUV-08SS65T

9
3121 10R

10

11

12

13

A
5VSTBY BAS316 6116 3100 I100 2100 100n 1K0 2101 I102 F100 220n 100u 5100 I101 3101 6K8 7100 BC847BW 3102 33R

A
F2

P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 NC 8G 7G 6G 5G 4G 3G 2G 1G

I108 470R 7101 BC847BW I105 I106 2106 50V 22u I107 3107 470R 3109 6100 BZX384-C6V8 470R 2108 47n 3110 3111 3112 10R 10R 10R

F22 F21

F11 F12

I104

3122 10R 3123 F112 10R

2107 22u 50V

F101

BC327-25 7103 2103 7104-3 74HCT14D 14 5 7 GND 5VSTBY 4104 7104-5 74HCT14D 14 11 4 7 7 GND 7 7104-2 74HCT14D 0100 WH02D-1 GND 5VSTBY 7104-6 74HCT14D 14 10 13 12 6 9 7 GND 5VSTBY 7104-4 74HCT14D 14 8 F2 1n0 3106 1K0 5VSTBY 5VSTBY

B
3124 82K 3125 3126 82K 3127 82K 82K VGNSTBY

2102 220n

C
6101 BAS316 6102 BAS316 6103 BAS316 6104 BAS316 6108 BAS316 6107 BAS316 6105 BAS316 6106 BAS316

3113 22K

D
2109 1n0

14 1 2 3 7 7104-1 74HCT14D

14

3130 2K7 3131 GND

WS0

GND

2K7 3132 7105 UPD16316GB-006-8ET 27 5VLP 1 F115 F131 1 1100 3 F130 SCK D_FM D_HOST 1101 32K768 2123 2124 22p 22p F133 RDY_FM ATN_FM HOST_RESET RC 5VSTBY 2K7 HLW14S-2C7-LF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1201 2119 100n 100n 2121 100n 2122 2120 100n

E
1208 4103 4102 EVQ11L05R 1213 EVQ11L05R 1211 1216

GND 1 F103 5102 EVQ11L05R 1215 EVQ11L05R 1214 EVQ11L05R 2 F104 6109 BAS316 6110 BAS316 6111 BAS316 2110 2n2 3117 10K 6113 BZX384-C6V8 6114 BAS316 F107 F106 BAS316 5VSTBY 6115 F105

EVQ11L05R 1207 EVQ11L05R

1217 EVQ11L05R

2127 2n2

GND 5VSTBY

3118 2111

10K 2n2

LTL816KETNN

3119

10K

F110 F111

KEY_A KEY_B KEY_C

14 15 16 17 18 19 20 21 22 23 24 25 26 29 30 31 32 33 34 35 36 37 38 39 40 45 46 47 48 RDY_FM 5 6 9

6212

2112

4100

H
1 1102 5VSTBY GND

2n2 GND 6112 5VLP 220m 5.5V 1m0 6.3V 2116 BAT54 COL 2114 10n

VDD 0 FIP 1 1 CTRL 2 DRIVER X 2 3 4 1 5 6 XT 2 7 8 RESET 9 10 11 SCK 12 FIP 13 D_HOST 14 15 SCK1 16 17 POWER_FAIL 18 19 IR 20 21 VLOAD 22 23 1 24 KEY_R 2 3 1 2 IC LED 3 4 POWER_CTL RDY ATN FM HOST_RESET

51 50 2 3 4 8 10 11 12 13 28 41 42 43 49 44 7 HOST_RESET 270K 2117 3120 KEY_A KEY_B KEY_C POWER_FAIL F134 2u2 50V 100R 3135

GND F132

3136 47K

2126

SCK D_HOST

GND

POWER_FAIL VGNSTBY 12VSTBY 100u 16V 2118

GND F116 F117 F118 F119 F120 F121 F122 F123 F124 POWER_CTLF125 F126 F127 F128

GND 5VLP 3137 5VSTBY 47K VGNSTBY 10n

RC

GND

GND

5VSTBY

3133 100R 3134 100R 4109

F114 4101

4110

GND

H
7107 TSOP4836ZC1 F129 VS OUT GND GND

3128 7106 BC847BW 560R

ATN_FM D_FM

2115

I
DC0

VSS 52 GND

2125

100n

GND GND GND GND

I
2005-04-12

GND

3139 243 31947

0100 E3 1100 E10 1101 F10 1102 H1 1201 F13 1203 A6 1207 F2 1208 E1 1211 E2 1213 F1 1214 F2 1215 F2 1216 F2 1217 F1 2100 B1 2101 B1 2102 B1 2103 B2 2104 A4 2105 A4 2106 A3 2107 B5 2108 B5 2109 D1 2110 G2 2111 G2 2112 H2 2114 I3 2115 I3 2116 I4 2117 H10 2118 G11 2119 G12 2120 G12 2121 G12 2122 G13 2123 F10 2124 F10 2125 I11 2126 F9 2127 G2 3100 B1 3101 B1 3102 A2 3103 A2 3104 A3 3105 A3 3106 C2 3107 A4 3108 A4 3109 B4 3110 B5 3111 B5 3112 B5 3113 D1 3117 G2 3118 G2 3119 H2 3120 H9 3121 A10 3122 A10 3123 B10 3124 B9 3125 B9 3126 B10 3127 B10 3128 I6 3129 G5 3130 D12 3131 D12 3132 E12 3133 H11 3134 H11 3135 F10 3136 F10 3137 G9 4100 H5

4101 I4 4102 F1 4103 E1 4104 D2 4109 H11 4110 H11 5100 B1 5102 E3 6100 A5 6101 D8 6102 D9 6103 D9 6104 D9 6105 D10 6106 D10 6107 D10 6108 D9 6109 E3 6110 F3 6111 F3 6112 H3 6113 G3 6114 G3 6115 E3 6116 B1 6212 H5 7100 C1 7101 B2 7102 A3 7103 B3 7104-1 D1 7104-2 D2 7104-3 C3 7104-4 C4 7104-5 D3 7104-6 D4 7105 E7 7106 I5 7107 H13 F100 B2 F101 B6 F103 E3 F104 E3 F105 E3 F106 F3 F107 F3 F110 H3 F111 H3 F112 B9 F114 H5 F115 E8 F116 E13 F117 E13 F118 E13 F119 E13 F120 E13 F121 F13 F122 F13 F123 F13 F124 F13 F125 F13 F126 F13 F127 F13 F128 F13 F129 H12 F130 E10 F131 E9 F132 F10 F133 F11 F134 F9 I100 B1 I101 B1 I102 B2 I103 A2 I104 A2 I105 B3 I106 B3

I107 A4 I108 A4

330R

2104

3103

47n 2105

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

1 2

150R

3129

32 31

10

11

12

13

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 36

Front: Front Panel

1
5VSTBY 2200 3200 10K 100n 2201

3
IO0
5ESD

A
6200

GND 5ESD BZX384-C12 5ESD BZX384-C12

GND

GND

GND

1 F201 Y C 3 F200 4
3201

2208

F202 1

1202 GND
GND

2204

100n

YKF51-5362
GND 5ESD 5ESD 5ESD

BZX384-C12

BZX384-C12

BZX384-C12

C
6202 F203 JPJ1127-01-0020 6 4 5 2 3 1301 1 F204 F205

100p

GND

C
1300 F207 GND GND GND 3204 GND 470R 2205 470p 3205 470R 2206 470p GND GND F208 F209 F210 F211 F212 1 2 3 4 5 6 7 8 9 B9B-PH-K Y C CVBS AL AR

6203

6204

1202 B1 1300 C3 1301 D1 1401 E1 1402 E3 2200 A1 2201 A2 2202 A2 2203 A3 2204 B1 2205 D2 2206 D2 2207 B2 2208 B2 2209 D1 2400 E2 3200 A2 3201 B1 3202 B2 3204 D2 3205 D2 3206 D1 6200 A1 6201 A2 6202 C1 6203 C2 6204 C2 F200 B1 F201 A1 F202 B1 F203 C1 F204 D1 F205 D1 F206 D1 F207 C3 F208 C3 F209 C3 F210 D3 F211 D3 F212 D3

10u 25V

2202

2203

GND

3202

6201

75R 2207

100p

75R

100n

10n

F206

GND

GND

100n

3206

75R 2209

1401 1 2 3 4 S4B-PH-K GND

1402 1 2 3 4 5401-042-101-92

2400 1n0 GND

GND

3139 243 31947

2005-04-12

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 37

Layout: Front Panel (Top View)

FrontPanel_Topview_31947_3355.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 38

Front: Standby

Layout: Standby (Top View)

1302 C2 1303 C4 2300 D2 6300 D2 6301 D3 F300 C2 F301 C2 I300 C4

DC0

1302 F300 I300

1303

1 2 S2B-EH F301 BZX384-C6V8 BZX384-C6V8

EVQ11L05R

2300

6300

6301

2n2

D
GND

E
3139 243 32017 2005-04-12

FrontPanel_Topview_hmc1_32017_3355_02.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 39

Digital: Back-End Processor

1 2 3 4 5 6 7 8 9 10 11 12 13
1101 B10 1111 E10 2101 B10 2102 B11 2105 G12 2108 F1 2109 F2 2120 B6 2121 F9 2122 F9 2123 F9 2124 F9 2125 F9 2126 F10 2127 F10 2128 F10 2129 F10 2130 F10 2131 G8 2141 G9 2142 G9 2143 G10 2144 G10 2145 G10 2146 G10 2147 G10 2151 H10 2152 I10 2153 I10 2154 I10 2155 I10 2156 I10 2157 I11 2158 I11 2161 I12 2162 I12 2171 I10 2172 I10 2173 I10 2174 I10 2175 I10 2176 I10 2181 I11 2182 I12 2183 I12 2191 I12 2199 E11 3101 B1 3102 B1 3103 B1 3104 C1 3111 D5 3112 D6 3113 D6 3114 D6 3121 B6 3122 B6 3123 B6 3124 A9 3125 B9 3131 C9 3132 C9 3133 C9 3134 C9 3135 C9 3136 C9 3137 C9 3138 C9 3139 D9 3141 E7 3142 E8 3143 E7 3144 E8 3145 E7 3146 E8 3147 E7 3148 E8 3149 E7 3150 E8 3151 E7 3152 E8 3153 E7 3154 E8 3155 E7 3156 E8 3161 A11 3162 B12 3163 B10 3164 C10 3165 C10 3166 C10 3167 C10 3168 G13 3169 H13 3171-1 G1 3171-2 G1 3171-3 G1 3171-4 G1 3172-1 G1 3172-2 G1 3172-3 G1 3172-4 G1 3173-1 G1 3173-2 G1 3173-3 H1 3173-4 H1 3174-1 H1 3174-2 H1 3174-3 H1 3174-4 H1 3175-1 H1 3175-2 H1 3175-3 H1 3175-4 H1 3176-1 H1 3176-2 H1 3176-3 H1 3176-4 H1 3177-1 I1 3177-2 I1 3177-3 I1 3177-4 I1 3178-1 I1 3178-2 I1 3178-3 I1 3178-4 I1 3181-1 G4 3181-2 G4 3181-3 H4 3181-4 H4 3182-1 G4 3182-2 H4 3182-3 G4 3182-4 H4 3183-1 G4 3183-2 G4 3183-3 H4 3183-4 G4 3184-1 G4 3184-2 G4 3184-3 G4 3184-4 G4 3185-1 H4 3185-2 I4 3185-3 I4 3185-4 H4 3186-1 H4 3186-2 I4 3186-3 H4 3186-4 H4 3187-1 I4 3187-2 I4 3187-3 I4 3187-4 H4 3188-1 I4 3188-2 I4 3188-3 I4 3188-4 I4 3191 H8 3192 F12 3193 F12 3194 F12 3195 F12 3196 F12 3197 E12 3198 E12 3199 E11 5121 F9 5131 G8 5141 G9 5151 H10 5161 H11 5162 H12 5171 I10 5181 I11 6101 C3 7101-1 D5 7101-10 I7 7101-2 A5 7101-3 B12 7101-4 A2 7101-5 F7 7101-6 D2 7101-7 A8 7101-8 F3 7101-9 A12 7105 G12 7111-1 E12 7111-2 F13 F101 B6 F102 B6 F103 B6 T101 B1 T102 B1 T103 B1 T104 B1 T105 B1 T106 B1 T111 E11 T112 E11 T113 E11 T121 A11 T122 B11

Back-end Processor
A
3V3BE 7101-4 DMN-8602

Back-end Flash (BEF)

Communication (COM)

7101-9 DMN-8602

7101-7 DMN-8602

MISC
G1 DPLUS_0 BYPASS_PLL DMINUS_0 HOST_PO_0 HMST_ALE HMST_UDS HMST_UWE HMST_DTACK H2 Y8 V14 U9 W5 U5 W4 V5 V4 3V3BE V7 U7 W6 W7 U6 3124 22R 3125 10K 3V3BE 3V3BE 1101 13M5 AT-49 T121 3161 10K E1 CKI CLKX CLK0_DAC GPIOEXT35

G3 G4 F1 H1 10K

Video Output Analog (VOA)

DAC JTAG
DAC1_OUT B7 B6 D6 A7 C6 TCK DAC2_OUT A1 A2 B4 A3 A4 B5 A5 A6

Audio (AUD)
H3 7101-2 DMN-8602 Y11 3121 SYSRST# 2120 F101 F102 F103 3V3BE AI_MCLKI GPIOEXT32 CS8 AO_MCLKI GPIOEXT33 CS9 AO FSYNC AI SCLK SCLK FSYNC AI_MCLKO A16 3123 10K W14 U13 U12 Y14 W13 V13 U11 Y13 W12 W10 Y12 V11 V9 Y10 W11 V10 3122 22R 100n 22R Y9 W15 Y7 U8 HOST_OC_0

HOST INFC

10K

10K

10K

HMST_CS0_8BIT HMST_LDS HMST_OE HMST_RST HMST_WR LWE HMST_WAIT

3101

3102

3103

T101 T102

TCK TMS TRST# TDI TDO 10K

C14 D14

0 AI_D 1 GPIO6

AUDIO
AO_D

G2

MCONFIG0

TMS DAC2_OUT_B TRST TDI DAC3_OUT DAC4_OUT

18p

T104 T105 T106

IEC958 MCLKO

10K 10K 10K 10K 10K 10K

TDO DAC4_OUT_B DAC5_OUT DAC6_OUT

A13

B13 A15 A14 B14

3104

3131 3132 3133 3134 3135 3136

D13 6101 BAV99 A12

3V3BE Y3 Y5 Y4 Y6 Y2 W3 3137 3138 3139 10K 10K 10K

3166 3167

C
Back-end Front-end Interface (IDE) Video Input Digital (VID)
7101-6 DMN-8602

0 1 2 3 4 5 6 HMST_AD 7 8 9 10 11 12 13 14 15 MA6:15 MDATA0:15

HMST_ADDRLO

0 1 2 3 4 MA1:5

SERIE-IO
SIO_SPI_MOSI 3164 3165 4K7 4K7 22R 22R Y18 Y17 W18 Y19 SCL SDA SIO SPI_MISO UART1_RX SIO_SPI_CLK SIO_SPI_CS2 CS10 W17 Y16

HMST_GPIO

0 1 2 3 4 5 PCMCIA_IOW PCMCIA_IOR 0 1 HMST_CS 2 3 4 5

V6 V12 W9 V8 W8 U10

Y15

W16 SIO_SPI_CS0 GPIOEXT24 V16 SIO_SPI_CS1 GPIOEXT25 SIO_IRRX GPIOEXT39 CS6 SIO_IRTX1 GPIOEXT40 CS7 SIO_UART2_RX GPIOEXT37 SIO_UART2_TX GPIOEXT38 SIO_UART1_TX V15

3V3BE

2101

2102

T103

C13

3163 1M0

18p

A17 0 B15 1 B16 2 B17 3

0 1 HMST_ADDRHI 2 3 4 MA22:26

T122 3162

7101-3 DMN-8602

3V3BE

U14

3V3BE 7101-1 DMN-8602 A9 A10 D7 C10 B11 C11 D11 D10 B12 C12 D12 A11 VI_CLK0

VIP_SCL VIP_SDA

10K 10K 10K 10K

W1 V2 T3 T1 R3 P4 P2 N4 N3 M4 M3 M2 N2 P1 P3 R1 R4 U1 W2

ATAPI
DMARQ INTRQ IORDY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ATAPI RESET DMAACK DIOW DIOR

U16

Y1 T2 R2 U3

VIDEO

V18

VI_VSYNC0|PEC 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 B10 C7 D8 C8 B8 D9 C9 B9

3111 3112 3113 3114

VO_CLK

A8

U17 W19

3V3BE 3141 3143 3145 3147 3149 3151 3153 3155 2K2 2K2 2K2 2K2 2K2 2K2 2K2 2K2 3142 3144 3146 3148 3150 3152 3154 3156 2K2 2K2 2K2 2K2 2K2 2K2 2K2 2K2

SIO_UART1_RTS GPIOEXT41 SIO_UART1_CTS GPIOEXT42

U15

VO_D VI_D

ATAPI_DATA 0 1 2 3 4 V3 T4 V1 U2 U4

lVGPIOEXT<0:7>

1111 B4B-PH-K 4 3 2 1 T111 T112 T113 2199 1n0 3199 100R 6 7111-1 BC847BS 1 2 3198 1K0

5VBE

E
3197 4K7

ATAPI_ADDR

3V3BE 3192 10K 3196 4K7 3 3194 10K 3193 10K 5 7111-2 BC847BS 4

1V8BE

100n

100n

100n

100n

100n

2123

2108

100n

2109

100n D16

SDRAM
SDRAM_VREF

100n

100n

100n

100n

100n

100n

100n

2141 22u 50V

DAC_DVSS1

REFVSS

XTALVSS

USB_AGND_0

3171-4 3171-3 3171-2 3171-1 3172-1 3172-2 3172-3 3172-4 3173-1 3173-2 3173-3 3173-4 3174-4 3174-3 3174-2 3174-1 3175-1 3175-2 3175-3 3175-4 3176-1 3176-2 3176-3 3176-4 3178-4 3178-3 3178-2 3178-1 3177-3 3177-2 3177-4 3177-1

4 3 2 1 1 2 3 4 1 2 3 4 4 3 2 1 1 2 3 4 1 2 3 4 4 3 2 1 3 2 4 1

5 6 7 8 8 7 6 5 8 7 6 5 5 6 7 8 8 7 6 5 8 7 6 5 5 6 7 8 6 7 5 8

47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R

M18 M19 N20 M17 L19 L18 L17 K18 K17 J19 H19 J17 J18 H18 H17 G20 G19 G18 G17 F18 F17 E19 E18 E17 A18 B18 A19 A20 B20 C19 B19 C20

WE RAS CAS CKE

N19 N17 P20 N18 L20 K20 E20 D20 M20 J20 F19 C18

22R 22R 22R 22R

6 8 7 5

3 1 2 4

3184-3 3184-1 3184-2 3184-4 J4

PHY-LINK
1394 LINK_ON 1394 PHY_CLK 1394_PHY_DATA J3 K1 PHY_CTL0 1394 PHY_CTL1

2128

2129

2124

2122

2130

2125

2127

2126

2V5S

7101-8 DMN-8602

7101-5 DMN-8602

2121 330u 16V

100n

100n

100n

100n

LREQ LPS 0 1 2 3 4 5 6 7

N1 M1 J2 L2 L4 L3 J1 K4 K3 K2 1V8BE 5131 BLM18P 1V8D 2V5BE 5141 BLM31 2V5S

FC: DM3
3V3BE 2105 100n

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

2146

2142

2143

2145

2147

2131

2144

CLK1 CLK1 0 1 2 3

22R 8 22R 7 22R 22R 22R 22R 8 8 6 5

1 3181-1 2 3181-2 1 1 3 4 3183-1 3182-1 3182-3 3181-4

SDRAM_DQS

1 2 3

(2Kx8) EEPROM
0 1 2 ADR

SDRAM CLK0 CLK0

22R 7 22R 5

2 3183-2 4 3183-4

L1

7105 M24C16-RDW6

3195 6K8

Back-end SDRAM (BES) IEEE1394 Link - Physical (LNK)

5121 BLM31 1V8C

G
WC SCL SDA 7 6 5 3169 22R 3168 22R

0 1 SDRAM_DQM 2 3 SDRAM_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17

K19 H20 F20 D18 R17 T19 P17 R19 R18 T18 T20 V20 U19 W20 U18 V19 U20 Y20 R20 P18 P19

22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R

6 7 5 6 6 8 5 8 5 5 7 5 8 7 6 6 7 8 7

3 2 4 3 3 1 4 1 4 4 2 4 1 2 3 3 2 1 2

3183-3 3182-2 3182-4 3181-3 3186-3 3186-1 3185-4 3185-1 3186-4 3187-4 3186-2 3188-4 3187-1 3188-2 3187-3 3188-3 3187-2 3188-1 3185-2 3191 1K2 1% 3V3R 3V3U 3V3A 3V3V 1V8D 3V3A 3V3P 2V5S 1V8C 5VBE D17 C16 J16 K16 L1 6 M16 L5 M5 T9 T10 E9 E10 D19 T17 V17 D15 H4 J5 K5 E11 E12 T12 T11 C1 D3 C4 E4 D2 D5 B3 B2 3V3BE 5151 BLM31 3V3P 100n 100n 100n 100n 100n 100n 2151 10u 25V 100n 100n 3V3BE 5161 BLM18P 3V3U 100n 3V3BE 5162 BLM18P 3V3R

C2

BIAS_5V00

VREF

F3 USB_AVDD_0

DAC_VDD_0

DAC_DVDD

DAC_VDD_3

XTALVDD

REFVDD

E2

2153

2155

2157

AVDD

VDDP

VDD25

SUPPLY
7101-10 DMN-8602

VDD

SDRAM_A

3V3BE 5171 BLM18P 3V3A 100n 100n 100n 100n 100n 2171 10u 25V

3V3BE 5181 BLM18P 3V3V 100n 100n 2181 220u 16V 100n 5VBE

2161

2156

2158

2162

2152

2154

22R 6

3 3185-3

21 7 3

2172

2174

2175

2183

2176

C15 C17 H8 H9 H10 H11 H12 H13 J8 J9 J10 J11 J12 J13 K8 K9 K10 K11 K12 K13 L8 L9 L10 L11 L12 L13 M8 M9 M10 M11 M12 M1 3 N8 N9 N10 N11 N12 N13

2191

2182

AGND E3 C3 D4 D1

GND

GND

GND

F4

C5

B1

F2

FC: DA0

3139 243 31875

2005-04-15

10

11

12

13

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 40

Digital: Memory
1 2 3 4 5 6 7 8 9 10 11 12 13
2201 D1 2202 D2 2203 D3 2204 D4 2205 D3 2211 B5 2212 B5 2213 B5 2214 B5 2215 A7 2216 B7 2217 B7 2218 B7 2219 B7 2220 D4 2221 D4 2231 B8 2232 B8 2233 B8 2234 B8 2235 A10 2236 B10 2237 B10 2238 B10 2239 B10 2240 D8 2241 D8 2251 A12 2252 A12 2253 B12 2254 B12 2255 B12 2256 B12 2257 B12 2258 B12 2259 C12 2260 C12 2261 C12 2262 C12 2263 C12 2264 C12 2265 D12 2266 D12 2267 D12 2268 D12 2269 D12 2270 E12 2271 E12 2272 E12 2273 E12 2274 E12 2275 E12 2276 F12 2277 F12 2278 F12 2281 F12 2282 F12 2283 G12 2284 G12 2291 G2 2292 F4 2293 H4 2294 F8 3251-1 A12 3251-2 A12 3251-3 A12 3251-4 A12 3253-1 B12 3253-2 B12 3253-3 B12 3253-4 B12 3255-1 B12 3255-2 B12 3255-3 B12 3255-4 B12 3257-1 B12 3257-2 B12 3257-3 B12 3257-4 B12 3259-1 C12 3259-2 C12 3259-3 C12 3259-4 C12 3261-1 C12 3261-2 C12 3261-3 C12 3261-4 C12 3263-1 D12 3263-2 C12 3263-3 C12 3263-4 C12 3265-1 D12 3265-2 D12 3265-3 D12 3265-4 D12 3267-1 D12 3267-2 D12 3267-3 D12 3267-4 D12 3269-1 E12 3269-2 E12 3269-3 D12 3269-4 D12 3271-1 E12 3271-2 E12 3271-3 E12 3271-4 E12 3273-1 E12 3273-2 E12 3273-3 E12 3273-4 E12 3275-1 F12 3275-2 F12 3275-3 F12 3275-4 E12 3277-1 F12 3277-2 F12 3277-3 F12 3277-4 F12 3281-1 F12 3281-2 F12 3281-3 F12 3281-4 F12 3283 G12 3284 G12 3285 G12 3286 G12 3294 H8 3295 I6 3296 H8 4291 H6 4292 H6 4293 H6 4294 I8 5201 B2 5291 F2 7201 C2 7211 C6 7231 C9 7292 F4 7293 H4 7294 H7 T201 D3 T202 D3

Memory
Back-end SDRAM (BES)

A
2V5D 2V5D 3251-4 3251-3 3251-2 3251-1 2211 22u 50V 2212 2213 100n 100n 100n 2215 2216 2217 2218 2219 100n 100n 100n 100n 100n 2231 22u 50V 2232 2233 2234 100n 100n 100n 2235 2236 2237 2238 2239 100n 100n 100n 100n 100n 3253-4 3253-3 3253-2 3253-1 3255-4 3255-3 3255-2 3255-1 3257-4 3257-3 3257-2 3257-1 3259-4 3259-3 3259-2 3259-1 3261-4 3261-3 3261-2 3261-1 3263-4 3263-3 3263-2 3263-1 3265-4 3265-3 3265-2 3265-1 3267-4 3267-3 3267-2 3267-1 3269-4 3269-3 3269-2 3269-1 3271-4 3271-3 3271-2 3271-1 3273-4 3273-3 3273-2 3273-1 3275-4 3275-3 3275-2 3275-1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 47R 4 3 2 1 5 6 7 8 47R 47R 47R 47R

VTT 2251 2252 100n 100n

2V5D

2253 2254

100n 100n

2255 2256

100n 100n

B
2V5BE 5201 BLM31 2V5D

2214

18

18

33

15

61

15

55

33

55

61

2257 2258

100n 100n

2V5D

C
7201 LP2995 VDDQ 5 VSENSE 3 2V5D 100n

29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 20 47 49 46 45 44 24 23 22 21

VDD 0 1 2 3 4 5 A 6 7 8 9 10 11 12 AP 0 BA 1 L DM U VREF CK CK CKE CS RAS CAS WE VSS 6 34 48 66

DDR SDRAM 16Mx16

VDDQ

NC

14 17 19 25 43 50 53 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65

PVIN

7211 D

VTT 6 100n 2201 22u 50V AVIN VREF GND NC

T201

VTT

4 100n

T202 100n 2203 330u 16V

100n

100n

2202

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

29 30 31 32 35 36 37 38 39 40 28 41 42 2V5D 100n 26 27 20 47 49 46 45 44 24 23 22 21

VDD 0 1 2 3 4 5 A 6 7 8 9 10 11 12 AP 0 BA 1 L DM U VREF CK CK CKE CS RAS CAS WE VSS 66 48 6

DDR SDRAM 16Mx16

VDDQ

NC

14 17 19 25 43 50 53 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65

2259 2260

100n 100n

7231 D

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

2261 2262

100n 100n

2263 2264

100n 100n

2265 2266

100n 100n

2220

2240

2267 2268

100n 100n

2205

2204

2221

DQS

L U

16 51

2241

DQS

L U

16 51

2269 2270

100n 100n

VSSQ 52 12 58 34 64

VSSQ 52 58 64 12

2271 2272

100n 100n

E
2273 2274 100n 100n

2275 2276

100n 100n

Back-end Flash (BEF)

F
3V3BE 5291 BLM18P 3V3F 2291 10u 25V

3V3F 2292 7292 74LVC573ADB 1 EN 11 C1 2 3 4 5 6 7 8 9 1D 20 100n

BA{BA(6:21)}

3277-4 3277-3 3277-2 3277-1 3281-4 3281-3 3281-2 3281-1 3283 3284 3285 3286

2277 2278

100n 100n

2281 2282

100n 100n

3V3F 2294 37 100n

2283 2284

100n 100n

19 18 17 16 15 14 13 12

VDD

3V3F 2293 7293 74LVC573ADB 1 EN 11 C1 2 3 4 5 6 7 8 9 1D 20 100n

19 18 17 16 15 14 13 12

4291 4292 4293 SYSRST# 3295 10K 3V3F

25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0 1 2 3 4 5 6 7 D 8 0 9 A 10 2M-1 / 1M-1 11 12 7294 13 M29W160ET70 14 15 A-1

[FLASH] 2Mx8/1Mx16

29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45

10

FC: DM2

H
3294 4K7 4K7 13 14 10 3V3F SYSRST# 3296

3V3F

15 12 11 28 26 47

NC RB RP WE OE CE BYTE 27

4294

10

VSS 46

I
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Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 41

Digital: IEEE 1394 Physical Layer

1 2 3 4 5 6 7 8 9 10 11 12 13
1351 D5 2301 D6 2302 D6 2303 D6 2304 D6 2305 D7 2306 D7 2307 D7 2321 G5 2341 G9 2343 G9 2351 D5 2352 E5 2361 E5 3301 E5 3302 F5 3303 G8 3304 G8 3305 E8 3306 F7 3307 F7 3308 F7 3310-1 E9 3310-2 E9 3310-3 E9 3310-4 E9 3311-1 E9 3311-2 E9 3311-3 E9 3311-4 F9 3312 E9 3313 E9 3314 D9 3315 E9 3321 F5 3322 G5 3331 F5 3332 F5 3341 F9 3342 F9 3343 F9 3344 F9 3345 G9 3351 E5 3360 E5 3361 E5 3362 E5 4361 E5 5301 C6 7301 D6 T301 E7 T302 E7 T303 E7 T304 E7 T305 E7 T306 E7 T307 E7 T308 F7 T309 E7 T310 F5 T311 F7 T312 E7 T313 E7 T314 E7 T315 F5 T316 F5 T351 E5 T352 E5

IEEE1394 Physical Layer

A A

IEEE1394 Link - Physical (LNK)

C
3V3BE 5301 BLM18P 3V3I 2301 10u 25V 2302 100n 100n 100n 2305 2306 2307 100n 100n 100n

D
2351 33p 3351 1M0 1351 24M576 AT-49

2303 2304

D
3314 4K7 4K7 3V3I

7301 TSB41AB1PHP T351 T352 42 43 38 39 22 1K0 1K0 1K0 1K0 T310 23 24 20 13 19 XI

25 35

21 44 45

AVDD

DVDD

PLLVDD

40

SYSCLK LREQ

1 T309 48 T312 2 T313 3 T314 4 5 6 7 8 9 10 11 30 29 28 27 T301 T302 T303 T304 T305 T306 T307 T308

3305

22R

LNK_CLK

3315

2352

33p 2361

XO 0 1 FILTER

100n

CTL

0 1 0 1 2 3 4 5 6 7

LNK_CTL0 LNK_CTL1

3312 3313 3310-4 3310-3 3310-2 3310-1 3311-4 3311-3 3311-2 3311-1 4 3 2 1 4 3 2 1

4K7 4K7 5 6 7 8 5 6 7 8 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7

3V3I 3V3I 3360 3361 3362 3301

4361

TESTM SE SM CPS LPS ISO 0 1 R

1-PORT CABLE TRANCEIVER ARBITER

D

LNK_DATA(0) LNK_DATA(1) LNK_DATA(2) LNK_DATA(3) LNK_DATA(4) LNK_DATA(5) LNK_DATA(6) LNK_DATA(7)

E
IEEE1394 Physical - Transport (PHY)

3V3I

3V3I

3302 3331 3332

10K

TPA+ TPATPB+ TPB0 PC 1 2 PLLGND GND_HS C LKON

3341 56R 1%

3342 56R 1%

31 T316 3321 100R 100n 4K7 T315 12 37

TPBIAS PD RESET AGND 26 32 36 DGND 14 46 47

16 17 18

3306 3307 3308

680R 680R 680R

15 T311 3V3I 3345 5K1 1% 3303 3304 10K 10K

41

2321

3322

49

2341 1u0

2343 220p

3343 56R 1%

3344 56R 1%

5K6 1% 33 750R 1% 34

FC: ME0

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3139 785 3093x

7.

EN 42

Digital: Video Input Processor

1 2 3 4 5 6 7 8 9 10 11 12 13
1461 C6 2401 C2 2402 C2 2403 C2 2404 C2 2411 D2 2412 D2 2413 D2 2414 D2 2415 D2 2421 E2 2422 E2 2423 E2 2424 E2 2425 E2 2426 E3 2427 E3 2431 E2 2432 F2 2433 F2 2434 F2 2435 F2 2453 D5 2461 C6 2462 D6 2471 E6 2472 E7 2473 E6 2474 E6 2475 E7 2476 E6 2477 E6 2478 E7 2479 E6 2480 E7 3400 D10 3401 C10 3407 D6 3408 D6 3452 D5 3453 D5 3454 E10 3455 D5 3461 C7 3471 F4 3472 F4 3473 F4 3474 F5 3475 F5 3476 F5 3477 F5 3478 F5 3479 F5 3480 F5 3481 E11 3482 E11 3484 F11 3486 F11 3488-1 F11 3488-2 F11 3488-3 F11 3488-4 F11 3492-1 E11 3492-2 F11 3492-3 F11 3492-4 F11 4471 E6 4472 E6 4473 E5 4474 E6 4475 E6 4476 E5 4477 E6 4478 E6 4479 E5 4480 E6 4481 E11 4486 E11 5401 C2 5411 D2 5421 D2 5431 E2 7401 C7 F401 D10 F402 D10 T400 E10 T401 F10 T402 F10 T403 F10 T404 F10 T405 F10 T406 F10 T407 F10 T408 F10 T409 F10 T411 E10 T412 E10 T461 C7 T462 D7

Video Input Processor

A A

B
1V8D2 3V3D2 1V8A2 3V3A2 1V8A2

3V3BE 5401 BLM18P 3V3D2 100n 100n 100n 2401 10u 25V 78 CH1_A18VDD 11 CH2_A18VDD 14 CH3_A18VDD 25 CH4_A18VDD 4 CH1_A33VDD 5 CH2_A33VDD 20 CH3_A33VDD 21 CH4_A33VDD

A18VDD_REF

DVDD

IOVDD

PLL_A18VDD

33p

2461

T461

7401 TVP5146PFP

2402

2403

2404

C
0 1 2 3 C 4 5 6 RED C_7 GREEN C_8 BLUE C_9 FSO AVID FID 70 69 66 65 64 63 60 59 58 57 36 71 35 72 73 4486 F402 3400 F401 2K2 3401 2K2

38 48 61

12

3V3BE 5411 BLM18P 100n 100n 100n 100n 33p 3V3D2 SYSRST# 3V3A2 VID_RST# 3452 100R 100R 10K 3455 3453 VIP_SCL VIP_SDA 3407 3408 2462

3461 1M0

1461

74 75

XTAL1 XTAL2 PWDN RESETB

T462

2411 10u 25V

33 34

2412

D
1V8BE

2413

2414

2415

31 41 55 67

76

D
Video Input Digital (VID)

22R 22R

28 29

2453 5421 BLM18P 1V8A2 100n 100n 100n 100n 100n 100n 2421 10u 25V

100n

SCL SDA FSS

Video Input Analog (VIA)

4471 4473 4474 4476 4477 4479 4478 600R 270R 4475 600R 600R 4472 680R 600R

2471 2473 2474 2476 2477 2479 4480 270R

100n 2472 100n 100n 2475 100n 100n 2478 100n 2480 100n 100n 100n 100n

2422

2423

2424

2426

2427

2425

80 1 2 7 8 9 16 17 18 23

VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A

HS CS VS VBLK GPIO<0:14> GLCO I2CA INTREQ DATACLK 0 1 2 3 4 5 6 7 8 9

37 30 40 54 53 52 51 50 47 46 45 44 43

2K2

3454 T412 T411 T400 T401 T402 T403 T404 T405 T406 T407 T408 T409

3481 4481 3482 3492-1 3492-2 3492-3 3492-4 3488-1 3488-2 3488-3 3488-4 3486 3484 1 2 3 4 1 2 3 4

10K

1V8BE 5431 BLM18P 1V8D2 100n 100n 100n 2431 10u 25V 100n

3V3D2

22R 8 7 6 5 8 7 6 5 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R

2433

2432

2434

2435

1%

1%

1%

1%

1%

1%

1%

1%

1%

1%

Y 79 CH1_A18GND 10 CH2_A18GND 15 CH3_A18GND 24 CH4_A18GND 3 CH1_A33GND 6 CH2_A33GND 19 CH3_A33GND 22 CH4_A33GND A18GND_REF PLL_A18GND

3472 75R

3474 75R

3477 75R

3473 75R

3471 75R

3476 75R

3478 75R

3479 75R

3475 75R

3480 75R

DGND 27 32 42 56 68

IOGND 39 49 62

13

26

77

81

GND_HS

AGND

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3139 785 3093x

7.

EN 43

Digital: Interfaces
1 2 3 4 5 6 7 8 9 10 11 12 13
1501 C1 1502 H9 1512 H12 1521 A9 1522 A9 1536 A13 1551 D12 1571 F1 2501 I7 2502 I7 2503 I6 2505 B4 2506 B4 2507 B5 2508 B5 2511 D2 2512 E2 2513 E2 2515 B2 2516 B2 2517 B2 2518 C2 2519 C2 2520 C2 2521 D2 2522 D2 2523 D2 2525 D6 2526 D7 2527 D4 2528 D5 2529 C5 2541 C11 2542 C12 2543 C12 2544 C12 2545 C12 2546 C12 2552 F9 2553 F9 2556 F10 2557 F10 2560 F10 2561 F10 2562 F10 2563 F10 2564 F10 2565 F11 2566 F11 2567 F11 2570 A9 2571 A9 2572 A9 2573 B9 2574 B9 2575 B9 2576 B9 2577 B9 2578 B9 2579 B9 2580 C9 2581 C9 2582 C9 2583 H2 2584 C9 2585 C9 2586 C9 2595 F5 2596 F5 3501 I6 3502 H6 3503 I8 3504 I8 3505 I8 3506 I8 3521 C6 3522 D6 3523 C6 3524 D5 3525 D5 3526 D6 3528 D5 3537 A11 3538 A11 3539 A11 3540 A11 3541 B11 3542 B11 3543 B11 3544 B11 3545 B11 3546 B11 3552 D9 3553 E9 3556 E9 3557 E9 3560 E9 3561 E9 3562 E9 3563 E9 3564 E9 3565 E9 3566 F9 3567 F9 3568 F11 3571 F2 3572 F2 3573-1 F2 3573-2 F2 3573-3 F2 3573-4 F2 3574-1 F2 3574-2 F2 3574-3 G2 3574-4 G2 3575-1 G2 3575-2 G2 3575-3 G2 3575-4 G2 3576-1 G2 3576-2 G2 3576-3 G2 3576-4 G2 3577 G2 3578 G2 3579-1 H2 3579-2 H2 3579-3 H2 3579-4 H2 3580 H2 3581 H2 3582 H2 3583 H2 3584-1 H2 3584-2 H2 3584-3 I2 3584-4 I2 3695 F6 4523 D6 4581 H2 5511 D2 5518 B2 5521 C2 5525 C6 6501 C4 6502 C4 6505 C6 6506 C7 6521 D6 6595 F6 7501 H6 7515 A2 7521 C3 7522 D5 7595 F5 T501 C1 T502 C1 T503 C1 T504 C1 T505 C1 T506 C1 T507 C1 T508 D1 T509 D1 T510 D1 T511 D1 T515 A2 T516 C7 T517 F6 T518 A8 T519 A8 T520 A8 T521 A8 T522 B8 T523 B8 T524 B8 T525 B8 T526 B8 T527 B8 T528 B8 T529 C8 T530 C8 T531 C8 T532 C8 T533 C8 T534 C8 T535 C8 T536 A13 T537 A13 T538 A13 T539 A13 T540 A13 T541 B13 T542 B13 T543 B13 T544 B13 T545 B13 T546 B13 T547 C13 T551 D12 T552 D12 T553 E12 T554 E12 T555 E12 T556 E12 T557 E12 T558 E12 T559 E12 T560 E12 T561 E12 T562 E12 T563 E12 T564 E12 T565 E12 T566 F12 T567 F12 T568 F12 T569 F12 T571 F1 T572 F1 T573 F1 T574 F1 T575 F1 T576 F1 T577 F1 T578 F1 T579 G1 T580 G1 T581 G1 T582 G1 T583 G1 T584 G1 T585 G1 T586 G1 T587 G1 T588 G1 T589 G1 T590 H1 T591 H1 T592 H1 T593 H1 T594 H1 T595 H1 T596 H1 T597 H1 T598 H1 T599 I1 T600 I1 T601 I1 T605 H8 T606 I8 T607 I8 T608 I8 T611 H11 T612 H11 T613 H11 T614 H11 T615 H11 T616 I11

Interfaces
Audio IO Video Output Analog (VOA)

A
7515 LD29150DT25R 100n 100n 100n 100n 1 100n IN OUT COM 2 3 2515 10u 25V T515 2V5BE 100n

1521 HLW30S-2C7 T518 T519 T520 T521 T522 T523 T524 T525 T526 T527 T528 T529 T530 T531 T532 T533 T534 T535 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

1522 HLW24S-2C7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2584 2585 2586 22p 22p 22p

Audio (AUD)

Video IO

1536 HLW22S-2C7 3537 3538 3539 3540 22R 22R 22R 60R 22R 22R 22R 60R 22R T536 T537 T538 T539 T540 T541 T542 T543 T544 T545 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

2507

2506

2508

2505

22p 3541 22p 22p 22p 22p 22p 22p 3546 22p 22p 22p 22p 22p 22p 22R 22p 22p 22p 22p 22p 22p T546 T547 3542 3543 3544 3545

2516

2517

CHASSIS1

CHASSIS2

CHASSIS3

CHASSIS4

Video Input Analog (VIA)

B
5518 BLM31 100n 2518 220u 16V 100n 3V3BE

6505 BAT760

BAT760 6501

BAT760 6502

6506 BAT760

2542

2544

2545

2541

2519

2520

Power supply

22n 8 5521 BLM31 100n 100n 2521 330u 16V 7521 L5973D 3 2 VCC INH FB SYNC COMP GND GND_HS 7 9 220p

3521 240R 1%

1501 B12P-PH-K 1 2 3 4 5 6 7 8 9 10 11 12 T501 T502 T503 T504 T505 T506 T507 T508 T509 T510 T511

3523 5K6 1% 2529 6

2543

2546

VREF

T516 5525 TSL0809 1V8BE

OUT

1 5 SS24 7522 BC847B 22n 3524 1K0

2525 330u 16V

2522

2523

4523

3528 4K7 1%2528

6521

2526

100n

5V

5511 BLM31 5VBE 100n 100n

3522 12K 1%

3525

3526

2527

1K0

1K0

D
2511 220u 16V

D
Communication
1551 HLW20S-2C7

Communication (COM)

2512

2513

3552 3553

22R 22R

3556 3557

22R 22R HOSTRST#

T551 T552 T553 T554 T555 T556 T557 T558 T559 T560 T561 T562 T563 T564 T565 T566 T567 T568 T569 22p 4K7

E
3V3BE 4K7

3560 3561 3562 3563 3564 3565 3566 3567

22R 22R 22R 22R 22R 22R 22R 22R

5VBE

Back-end Front-end Interface (IDE)

22p

22p

22p

22p

22p

22p

22p

22p

22p

22p

100n

2552

2561

2553

2562

2564

2565

2556

2560

2557

2563

2566

2567

3573-1 3573-2 3573-3 3573-4 3574-1 3574-2 3574-3 3574-4 3575-1 3575-2 3575-3 3575-4 3576-1 3576-2 3576-3 3576-4 3577 3578 3579-1 3579-2 3579-3 3579-4 3580 3581 4581 3582 3583 2583 3584-1 3584-2 3584-3 3584-4

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5

33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 4K7 33R

HOSTRST# 2595 4 3 2596 22p 6595 BAS316

3568

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

T571 T572 T573 T574 T575 T576 T577 T578 T579 T580 T581 T582 T583 T584 T585 T586 T587 T588

5VBE

OUTP CD NC GND

22p

1571 1-440094-2

3571 3572

10K 33R

INP

3695

ATAPI

7595 NCP303LSN30 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

T517

SYSRST#

F
FC: DIA

FC: DP2

G
Communication (COM)

T589 T590 T591 T592 T593 T594 T595 T596 T597 T598 T599 T600 T601

IEEE1394 Physical - Transport (PHY)

1 2 3 4

8 7 6 5

5VBE

33R 33R 33R 33R 33R 4K7

5V

3502

10K

7501 TPS2041D

IEEE1394
1512 BM06B-SRSS-TBT T611 T612 T613 T614 T615 T616 8 7 1 2 3 4 5 6

33R 680R 22p 1 2 3 4 8 7 6 5 33R 33R 33R 33R 5V 100n

4 2 3

EN_ 1 IN 2 GND

1 OUT 2 3 OC_

6 7 8 2501 220u 16V 5

USB
1502 B4B-PH-K 3503 3504 3505 3506 22R 22R 15K 15K T605 T606 T607 T608 1 2 3 4 100n 2502

2503

FC: DI4

I
5V 3501 10K

FC: ME0 FC: MU0

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3139 785 3093x

7.

EN 44

Layout: Digital-Main Part (Top View)

Digital_Topview_3355_02.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 45

Layout: Digital-Main Part (Bottom View)

Digital_Bottomview_3355_02.pdf 2005-07-15

Circuit Diagrams and PWB Layouts

3139 785 3093x

7.

EN 46

Notes:

Circuit- and IC description

3139 785 3093x

8.

EN 47

8.
8.1.
8.1.1.

Circuit- and IC description

Front Board (Panel Display + Key)
General This board consists of the following parts: Slave P Frontend (Audio & Video) VFD Heater voltage Generator

8.2.
8.2.1.

Analog Board
General The pc board consist of the following parts: Fan Control (OPTION) Power Supply Unit Tuner Frontend Audio ADC/DAC Fan Control The Laser on the OPU of the drive is very sensitive to temperature. A fan control circuit [7802 & 7803] is built into the board as a provision. The fan is ON when the set is in active mode, and OFF when the tray opens. When the set is in Standby mode, the fan is switched off. The control of the fan is coming from the Digital Board. Power Supply Unit This power supply functions on a circuitry combination of a SMPS control IC [7400], switching FET [7401] and transformer [5400] as a switched-mode power supply (SMPS). Feedback control is provided by the IC 7404, which compares the 5V-output voltage via voltage dividers [3421, 3422 & 3423] with an internal 2.5V reference voltage. The output voltage is fed to an optocoupler [7403] that provide the insulation between the primary and secondary parts as a current value into pin 3 of the IC 7400. The following are the various supply lines provided: 3V3SW to CU, DAC_ADC, Digital Board 5V to IOA, IOV, CU, CINCH, MSP, DIGIO and FV 5N to MSP (provision only) and Digital Board (provision only) 5VE to Basic Engine 5V_BE to Digital Board 5NSTBY to IOA, CINCH and DAC_ADC 5VSTBY to IOA, IOV, FV, MSP, DAC_ADC, Front Board 8VSTBY to MSP 12V to Digital Board 12VSTBY to CU, IOV, DAC_ADC, Front Board 12VE to Basic Engine and Digital Board (provision only) 33VSTBY to FV VGNSTBY to Front Board Standby modes: In Standby mode, the STBY control line is low, switching off the 3V3SW, 5V, 5N (provision), 5VE, 12V and 12VE supply and thus reducing the power consumption.

8.1.2.

Slave P (IC 7105: UPD16316GB) The core element of the Front Display + Keyboard is the slave P. It runs on a 5V supply and is responsible for the following functions: Interface with the Domino chip on the Digital Board Evaluation of the keyboard matrix within Front board Decoding the remote control commands from the infra-red receiver Activation and control of the display Timer Wake-up activation It runs on two clock frequencies namely: 5MHz for normal operation 32.768KHz for the real time clock

8.2.2.

8.2.3.

8.1.3.

Interface to the Domino chip It communicates with the Domino Host on the Digital board via a 6-wire synchronous serial interface. The Host is always the master to generate the communication clock to the slave P irrespective of the direction of data transfer.

8.1.4.

Evaluation of the keyboard matrix A key matrix is used on the Front board. The slave P does the key scanning with FIP9 - FIP24 (pin 23-26 and 29-40) as output and KEY_A - KEY_C (pin 41-43) as input. Each key is assigned a key code based on the output and input ports, and the slave P will do the evaluation by getting the key codes.

8.1.5.

IR receiver and signal evaluation The IR receiver on the Front Board contains a selectively controlled amplier as well as a photodiode. The photo-diode changes the received infrared transmission to electrical pulses, which are then amplied and demodulated. On the output of the IR receiver, a pulse sequence with TTL-level, which corresponds to the envelope curve of the received IR remote control command, can be measured. This pulse sequence is fed into the slave P for further processing via pin 13.

8.1.6.

Vacuum Fluorescent Display [1203: HUV-08SS65T] The VFD is fully controlled and driven by the slave P.

8.1.7.

VFD Heater Voltage Generator The oscillator circuit provided by [5100, 2101, 2102 & 7100] provides the necessary sine wave signal for transistors [7101, 7102 & 7103] to generate the 50% duty-cycle 48KHz AC square-wave signal for the lament of the VFD.

8.1.8.

Timer Wake-up activation During the Standby mode, the slave P provides a wakeup call (POWER_CTL-line switches to high) to the Domino Host on the Digital Board. It will then starts up and asks for the wake-up reason.

EN 48
8.2.4.

8.

3139 785 3093x

Circuit- and IC Description

Tuner Frontend [1100 : TMQZ2] It has a RF IN for antenna connection and RF OUT which provides a RF loop through for connection to the TV. The Frontend ( Tuner & IF-demodulator ) is controlled by I2C (SCL_5V- and SDA_5V-) lines coming from the Domino Host on the Digital board. Complete video processing is done in this unit and the video output (CVBS) is taken out from the [VID_OUT] pin via a transistor as CVBS_TV-line to the Video I/O circuitry. The audio-IF component SIF1 is taken out from the [SIFOUT] pin for the demodulation by the Multi-sound processor (MSP). Audio demodulator The sound demodulation is done by the MSP3415 [7500], which is also fully controlled via I2C bus by the Domino Host. The audio signals are available at pin 26 and pin 27 and fed as AFER- & AFEL- line to the audio I/O for further processing.

8.2.5.

Analog Audio In / Out Overview

Scart2
6 3 1 2

Scart1

Audio routing

AudInL

AudInL

AudInR

AudOutL

AudOutL AudInR Dig.Audio Out ALDAC ARDAC AudOutR

AudOutR

OUT1R OUT1L OUT2L OUT2R

MUTE

AKILL BKILL

AKILL

DKILL

POWER_FAIL

AKILL 1
AIN2R
MSB/LSB LL

HEF4052
POS.7303
H

AKILL

AKILL

4 3 3 0dB
OUT1R

LH

POS.7703

CS4351

2
ARDAC

HL L

D_DATA

VOR

15

ARDAC

5 12
LL

HH

DAC AIN2L

from dig. board

VOL

18

ALDAC

11
H HL L

LH

19

14

13

OUT1L

15
ALDAC

0dB
DAOUT

BMUTE

14 Logic
MSB

HH LSB

AMUTE

from digital board

10

AMUTE from Domino Host (digital board) MUTE AL AR REAR OUT (CVBS/YC)

Circuit- and IC description

AINFR

AIN_SEL0 AIN_SEL1

FRONT IN (CVBS/YC)

AINFL

Tuner
SIF1

POS.7500

MSP3415G

AIN1L AIN2L

2 1 5 3
AINFL AFEL

MSB/LSB LL

HEF4052
POS.7302
LH

BKILL

MUTE BMUTE
H

Source select

Figure 8-1 Analog Audio In / Out Overview

2
Demodulator 3 4 5 1
AIN1R AOUT2R
SC1_OUT_L HL L HH

SIF1

0dB

ALDAC

37
SC1_OUT_R

3139 785 3093x

ARDAC

30 31 26
AOUT2L AFER

15
AIN2R AINFR

LL

38 40 41
Q.Peak Det

POS.7704

UDA1361TS

14 11

LH H HL L

ALADC

AIN1L AIN1R

13
DACM_R DACM_L

0dB
ARADC AFER

1 ADC

A_DATA
HH

27 I2C Control

AFEL

12

Logic
MSB LSB

to dig. board

8.

10

12

13

9
RSA1

from Domino Host SCL_5V (Digital Board) SDA_5V

RSA2

DVDR3355_Eur_Audio IO dd wk527

EN 49

EN 50

8.

3139 785 3093x

Circuit- and IC Description

The sound processing is always done in stereo (that means separate left- and right- channel) and the complete switching is realized by using HEF4052 which is a dual four-to-one multiplexer and MSP3415G which is a multi-sound processor. a) Scart 1 Output path The multiplexer [7303] selects either signals from the Scart 2 Input (AIN2L/AIN2R) or the Audio DAC (ALDAC/ARDAC) as the output source for Scart 1 (AOUT1L/AOUT1R). b) Scart 2 Output path The MSP [7500] selects either signals from the Scart 1 Input (AIN1L/AIN1R), the Audio DAC (ALDAC/ARDAC) or the Tuner Frontend as the output source for Scart 2 (AOUT2L/ AOUT2R). c) Digital audio-out path In addition, a digital output (DAOUT) coming from the Digital board is passed through a 6-fold inverter [7900] for performance reasons (noise reduction, jitter, ) and transformer (level correction, ground isolation,) to the digital out cinch socket at the rear. d) Record path The record-selector [7302] selects either signals from the Scart 1 Input (AIN1L/AIN1R), Scart 2 Input (AIN2L/AIN2R), Front Cinch (AINFL/AINFR) or the MSP (AFEL/AFER) and routes to the audio ADC (ALADC/ARADC) for record purposes. The switch is controlled via RSA1 and RSA2 signals coming from the MSP. 8.2.6. Audio ADC/DAC The conversion of analog audio signals from the recordselector [7302] outputs (ALADC/ARADC) is done via UDA1361TS [7704]. This IC can process input signals up to 2Vrms by using external resistors in series to the input pins. All required clock signals are generated on the digital board and only the audio data (A_DAT-line) are routed to Digital board for further processing. The transformation of digital audio back into analog domain is done by CS4351 [7703]. All necessary clock signals are coming from the digital board and digital audio data (D_DATA0-line) are converted into analog signals (pin 15 and 18). The output signals from the audio DAC part (ALDAC/ ARDAC) are directly routed to the rear cinch sockets. To avoid plops and any other audible noise on the output muting circuits are implemented for each channel. Muting for the various other output lines are done via AKILL & BKILL-lines which is a combination of the D_KILL from the Digital board and POWER_FAIL from power supply and AMUTE & BMUTE (digital silence mute) from DAC-part.

8.2.7.

8SC2 to CU to Digital Board

Analog Video In / Out Overview

8SC2_1

8SC2_2

VideoIn G FastBlk R/C_Out SlowBlk

VideoIn

R/C_In

Bin/out

FastBlk

SlowBlk

VideoOut

VideoOut

Video Aspect Ratio detection 12V 6V 0V Video Aspect Ratio detection & AV switching

Bout/Cin

Video-routing

0V 2.2V 5V

DGO2

Scart FS In/Out loop through

DigOUT1 (pin 42)

Pos 7210

D_CVBS

Pos 7606

NJM2267M

CVBS

FBIN to CU
CVBS_RE CVBSIN1

CVBS_TV

D_Y Y

YCVBSIN2 YCVBSOUT1 D_CVBS

D_Y CVBSOUT2

CRout

DENC
RCIN

to VIP

D_CVBS

D_Y
D_C

D_C

CVBS_REAR
GIN ROUT RCIN

D_VR

D_YG A_UB A_YG

BIN GOUT

Circuit- and IC description

From digital board

D_UB

A_VR CVBS_TV
BOUT

CVBS_FIN
D_VR FBOUT D_UB

DGO1

DGO2

CVBS D_Y D_CVBS A_UB A_YG A_VR

CVBS_FIN

DGO4

FrontIN

Figure 8-2 Analog Video In / Out Overview

D_YG FBIN

Y_FIN C_FIN

3139 785 3093x

CVBS_TV

From CU

To digital board

8.

Y/C

Y_FIN

EN 51

C_FIN
DVDR3355_Eur_Video IO dd wk527

EN 52

8.

3139 785 3093x

Circuit- and IC Description 8.3. Digital Board

The Digital Board is based on the highly integrated LSI Domino BGA chip (Ball Grid Array), DMN-8602. This IC has an on-chip ATAPI controller and integrates an analog video encorder, and provides build-in support for non-simultaneous progressive and interlaced video output. A 1394 link layer function is also integrated so a simple external physical layer device is required. The DMN-8602 also has a set of integrated USB Physical Layer Interface. The board encodes and multiplexes analogue video and digital uncompressed audio (I2S) into an MPEG2 stream. This MPEG2 stream is formatted for recording by the DVD+RW engine. In the playback, the board will decode the MPEG2 video into analogue video. In addition, a DV stream can be received via IEEE 1394 (i-Link), and transformed to MPEG2 format.

A matrix switch STV6618 [7210] controlled by the Domino Host via I2C-bus is used for Video I/O switching. All used outputs excluding pin 21 (Y/CVBS-REC) have a 6dBamplication and a 75 ohms-driver-stage inside. This IC also includes several digital outputs, which are used for switching purposes on the Analog board. This matrix switch routes the selected inputs to the correct output lines for TV viewing and further processing in the Digital board. The record selector inside the switch selects between the inputs from Tuner Frontend (CVBS_TV), CVBS Scart1 (CVBSIN1), CVBS Scart2 (CVBSIN2) or D_CVBS from the DENC (on Digital board). The output signal CVBS_RE together with the other signals CVBS_FIN, Y_FIN & C_FIN from the Front and RCB from Scart2 are routed directly to the VIP (on Digital board) for further processing. The signals D_C and D_Y are fed through [7606] (6dB amplication) and D_C via transistors [7213 & 7212] as driver to the S-Video output socket. Likewise the signal D_CVBS is fed through [7606] (6dB amplication) to the rear CVBS cinch socket.

8.3.1.

Record Mode

TO/FROM FRONTEND PART ATAPI

7401 7101 VIP TVP5146 ITU656 DOMINO DMN-8602 1FH VIDEO (2) OUT CLOCK 13.5MHz 7211/7231 DDR SDRAM 16M X 16Bit DIG. AUDIO OUT I2S A UDIO OUT

I2C

I2S A UDIO IN

For DV-in version only

7304 1394 TSB41AB1

7294 FLASH 16M Bit

1FH VIDEO IN(1)

3V3 1512 1394 CONNECTOR

5V

12V
(1) analogue CVBS / YC and RGB/YUV (2) analogue CVBS, YC, RGB/YUV

FROM POWER SUPPLY

Figure 8-3 Domino block

Circuit- and IC description

Video Part The analogue video input signals CVBS, YC and RGB are routed via the board to connector 1521 and sent to Video Input Processor, TVP5146P [7401]. The digital video input signals from the DV-in on the Front board are routed from connector 1521 via the IEEE 1394 PHY IC [7301] to the Domino chip [7101]. 8.3.2. The Video Input Processor encodes the analogue video to digital video stream (CCIR656 format). The output stream, named VID_D (9:0), is then routed to the Domino chip. This IC encodes and decodes the digital video stream into / from MPEG2 format. Audio Part I2S audio is sent from the Analog board to the Domino chip via connector 1536. The Domino chip compresses the I2S audio data into an MPEG1-L2 / AC3 audio stream. Front-end I S The Domino chip interfaces directly to the basic Engine via 8.3.4. Clock Distribution
2

3139 785 3093x

8.

EN 53

ATAPI connector 1571. It buffers the data streams that are coming from (or going to) the Basic Engine. In the Domino chip, the video MPEG2 stream and the audio AC3 stream are sent to the basic Engine for recording through ATAPI bus. Playback mode During playback, the data from the Basic Engine is going directly to the Domino chip via ATAPI interface. The Domino chip has the following outputs: Analogue video CVBS, YC and RGB outputs on connector 1521 I2S audio (PCM format) on connector 1536 SPDIF audio (digital audio output) on connector 1536 Progressive Scan output connector 1522 (Not for European version) Basic Engine Interface The Digital board is equipped with an IDE bus (ATAPI) for connecting to the Basic Engine.

8.3.3.

FRONTEND INTERFACE 14.31818MHz

7401 VIP TVP5146 7101 7211 150 MHz DOMINO DMN-8602 7301 1934 PHY SDRAM

7231 SDRAM

24.576 MHz

13.5 MHz
Figure 8-4 DIMINO_CLOCK

The Domino chip has a complex system, which is needed to support the processes running at different frequencies such as video decoding, audio decoding or peripheral I/O devices etc. To ensure a synchronous initialization of all the registers and state machines, all the PLLs are switched to their default frequency 27MHz. Then when the booting control unit is correctly initialized and once it has captured all the booting parameters, it sets the PLLs to its functional frequencies. Thanks to a clock blocking mechanism, the frequency switching is glitch free.

System clocks: DMN-8602 (7101, pin E1 and F1): 13.5 MHz provided by the xtal 1101 DMN-8602 1394-LINK (7101, pin L1): 49.152MHz provided by 1394-PHY TVP5146 (7401, pin 74 and 75): 14.31818MHz provided by xtal 1461 SDRAM (7211 and 7231, pin 45 and 46): 150MHz provided by the DMN-8602 TSB41AB1PHP IEEE 1394 PHY IC (7301, pin 42 and 43): 24.576MHz provided by xtal 1351

EN 54
8.3.5.

8.

3139 785 3093x

Circuit- and IC Description

Power Supply The Digital board is not powered in standby mode. The control signal STBY on the analog board will enable the PSU and power the digital board. STBY = Low: the digital board is in powered down standby mode STBY = High: the power supply to the digital board is enabled. The 3V3, +5V and +12V come from the PSU, while the following voltages are generated in the digital board: 1.8V core voltage is generated on the board by a 2A switching step down voltage regulator [7521] 2.5V supply for the SDRAM is generated by an ultra fast low dropout linear regulator [7515] 1.25V DDR termination supply is generated by regulator [7201]

8.3.6.

Memory FLASH IC7294: this memory contains the boot parameters and application rmware

8.3.7.

Reset

5V Supply

HOSTRST

FRONT MICROPROCESSOR

SYSRST# DMN-8602

IDE_RST#

Basic Engine VAD8041 Delay t3

POWER ON RESET & LOW VOLTAGE DETECTION NCP303LSN30 IC7595

VID_RST#

VIP (TVP5146) Delay t2

LNK_RST#

PDI1394P25BD Delay t2

FLASH MEMORY RSTn

Figure 8-5 DOMINO_RESET Reset concept Digital board The rest circuitry [7595] takes cares that the different devices on the digital board are boot-up in the correct order. At power on the reset circuitry provides the following resets (delay 1): SYS_RST# to the Domino chip [7101] and Flash Memory [7294] The Domino chip then generates other reset signals (delay 2) via its GPIOs: VID_RST# to reset the VIP [7401] LINK_RST# to reset the IEEE1394 DV PHY IC [7301] IDE_RST# to reset Basic Engine 8.3.8. I/O Connector Audio IO Connector (item 136) The Audio In/Out (AIO) connector is used to interchange digital audio signals between the Analog and Digital board Video IO Connector (item 1521) The Video In/Out (VIO) Connector is used to interchange analogue video signals between the Analog and Digital board

Circuit- and IC description 8.4

8.4.1

3139 785 3093x

8.

EN 55

IC Description
Analog Board IC7421 - TEA1507 - SMPS Control IC

BLOCK DIAGRAM
dth

VCC

SUPPLY MANAGEMENT internal UVLO start supply

START-UP CURRENT SOURCE clamp VALLEY

DRAIN HVS n.c.

GND

S1

M-level VOLTAGE CONTROLLED OSCILLATOR 4 LOGIC 100 mV OVERVOLTAGE PROTECTION DEM

FREQUENCY CONTROL

OVERTEMPERATURE PROTECTION 3 1

LOGIC

DRIVER Iss

DRIVER

CTRL

POWER-ON RESET

LEB S Q blank soft start S2

0.5 V

2.5 V burst detect

UVLO

Q 5 OCP Isense

TEA1507

MAXIMUM ON-TIME PROTECTION

short winding

0.75 V OVERPOWER PROTECTION

MGU230

Figure 8-6

PIN DESCRIPTION AND CONFIGURATION

SYMBOL PIN VCC GND CTRL DEM Isense DRIVER HVS DRAIN 1 2 3 4 5 6 7 8 ground control input input from auxiliary winding for demagnetization timing, OVP and OPP programmable current sense input gate driver output high voltage safety spacer, not connected drain of external MOS switch, input for start-up current and valley sensing Fig.3 Pin configuration. DESCRIPTION supply voltage
handbook, halfpage

VCC 1 GND 2

8 DRAIN 7 HVS

TEA1507
CTRL 3 DEM 4
MGU231

6 DRIVER 5 Isense

EN 56

8.

3139 785 3093x

Circuit- and IC Description

IC7500 - MSP34X5G - Multistand Sound Processor Family

BLOCK DIAGRAM

23 N.C.

24 N.C.

28 N.C.

32 N.C.

33

19

34

AHVSUP

AVSUP

ANA_IN+

CAPL_M

DVSUP

MSP34x5G

ANA_IN-

ADC

DeModulator

Preprocessing

Loudspeaker sound proeessing

DACM_L

27

DAC
DACM_R

26

17

I2S_DA_IN1

21 39 40 41

I2S_DA_IN2

Preprocessing Source select

Loudspeaker sound proeessing

I2S_DA_OUT

16

ASG SC1_IN_L SC1_IN_R

37 38

SC2_IN_L SC2_IN_R

SCART DSP input select

SC1_OUT_L

31

ADC

Prescale

DAC SCART Output select

SC1_OUT_R

30

43

MONO_IN

10 ADR_SEL 12 13 I2C_CL I2C_DA XTAL_OUT AGNDC AHVSS I2S_WS XTAL_IN ADR_CL I2S_CL VREF1 VREF2 DVSS AVSS

D_CTR_I/O-0

9 8

I2C Control

ADR BUS

I2S Control

X'tal Oscillator
STANDBYQ VREFTOP RESETQ TESTEN

D_CTR_I/O-1

18

14

15

44

35

36

20

29

25

42

22

11

Figure 8-7

TP 7

Circuit- and IC description PIN CONFIGURATION

NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP DACM_L DACM_R VREF2 NC NC

3139 785 3093x

8.

EN 57

33 32 31 30 29 28 27 26 25 24 23 CAPL_M AHVSS AGNDC SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS 34 35 36 37 38 39 40 41 42 43 44 1 AVSUP ANA_IN1+ ANA_IN TESTEN XTAL_IN XTAL_OUT TP 2 3 4 5 6 7 8 9 10 11 STANDBYQ ADR_SEL D_CTR_I/O0 D_CTR_I/O1 22 21 20 19 18 RESETQ I2S_DA_IN2 DVSS DVSUP ADR_CL I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL

MSP 34x5G

17 16 15 14 13 12

PMQFP44 package
Figure 8-8

IC7703 - CS4351 - 192KHz Stereo DAC with 2vrms line-out

BLOCK DIAGRAM
1.8 V to 3.3V 3.3 V 9 V to 12 V

Hardware or I 2C/SPI Control Data Register/Hardware Configuration Reset Interpolation Filter with Volume Control Level Translator Multibit
Modulator

DAC

Amp + Filter

2 Vrms Line Level Left Channel Output

Serial Audio Input

PCM Serial Interface Interpolation Filter with Volume Control Multibit

Modulator

DAC

Amp + Filter

2 Vrms Line Level Right Channel Output

Auto Speed Mode Detect Internal Voltage Reference

External Mute Control

Left and Right Mute Controls

Figure 8-9

EN 58

8.

3139 785 3093x

Circuit- and IC Description

PIN DESCRIPTION AND CONFIGURATION

SDIN SCLK LRCK MCLK VD GND DIF1(SCL/CCLK) DIF0(SDA/CDIN) DEM(AD0/CS) RST

Pin Name
SDIN SCLK LRCK MCLK VD GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VL AMUTEC AOUTA VA_H GND AOUTB BMUTEC VQ VBIAS VA

# 1 2 3 4 5 6 16 10 11 12 13 17 20 14 19 15 18

Pin Description
Serial Audio Data Input (Input) - Input for twos complement serial audio data. Serial Clock (Input) - Serial clock for the serial audio interface. Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section. Ground (Input) - Ground reference. Reset (Input) - Powers down device and resets all internal resisters to their default settings when enabled. Low Voltage Analog Power (Input) - Positive power supply for the analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. High Voltage Analog Power (Input) - Positive power supply for the analog section. Serial Audio Interface Power (Input) - Positive power for the serial audio interface Mute Control (Output) - Control signal for optional mute circuit.

RST VA VBIAS VQ VA_H VL BMUTEC AMUTEC AOUTB AOUTA Control Port Definitions SCL/CCLK SDA/CDIN AD0/CS Stand-Alone Definitions DIF0 DIF1 DEM

Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteristics table.

7 8 9

Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data (Input/Output) - Input/Output for I2C data. Input for SPI data. Address Bit 0 / Chip Select (Input) - Chip address bit in I2C Mode. Control Port enable in SPI mode.

8 7 9

Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock, and Serial Audio Data. De-emphasis (Input) - Selects the standard 15s/50s digital de-emphasis filter response for 44.1 kHz sample rates

Circuit- and IC description

IC7704 - UDA1361TS - 96KHz Sampling 24-bit stereo audio ADC

3139 785 3093x

8.

EN 59

BLOCK DIAGRAM
VDDA 16 VSSA 15 VRP 5 VRN 4 Vref 2

dth

SYSCLK 8 9 VDDD VSSD

UDA1361TS
1 ADC

10

VINL

14 DECIMATION FILTER VINR 3 ADC CLOCK CONTROL 7

MSSEL PWON

DATAO BCK WS

13 11 12 DIGITAL INTERFACE DC-CANCELLATION FILTER 6 SFOR

MGT451

Figure 8-10

PIN DESCRIPTION AND CONFIGURATION

SYMBOL VINL Vref VINR VRN VRP SFOR PWON SYSCLK VDDD VSSD BCK WS DATAO MSSEL VSSA VDDA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION left channel input reference voltage right channel input negative reference voltage positive reference voltage data format selection input power control input system clock 256, 384, 512 or 768fs digital supply voltage digital ground bit clock input/output word select input/output data output master/slave select analog ground analog supply voltage
handbook, halfpage

VINL 1 Vref 2 VINR 3 VRN 4

16 VDDA 15 VSSA 14 MSSEL 13 DATAO

UDA1361TS
VRP 5 SFOR 6 PWON 7 SYSCLK 8
MGT452

12 WS 11 BCK 10 VSSD 9 VDDD

EN 60

8.

3139 785 3093x

Circuit- and IC Description

8.4.2

Digital Board IC7301 - TSB41AB1 - IEEE 1394a-2000 one port cable Transceiver/Arbiter

BLOCK DIAGRAM

CPS LPS ISO CNA

Link Interface I/O

Received Data Decoder/Retimer

SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PC0 PC1 PC2 C/LKON

TPA+ TPA

Cable Port Arbitration and Control State Machine Logic TPB+ TPB

R0 R1 TPBIAS

Bias Voltage and Current Generator

PD RESET CNA output is only available in the 64-pin PAP package

Transmit Data Encoder

Crystal Oscillator, PLL System, and Clock Generator

XI XO FILTER0 FILTER1

Figure 8-11

Circuit- and IC description PIN CONFIGURATION

3139 785 3093x

8.

EN 61

PHP package terminal diagram

PHP PACKAGE (TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

XI PLLGND PLLVDD FILTER1 FILTER0 RESET

LREQ DGND DGND DVDD DVDD XO

SYSCLK CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

36 35 34 33 32 31 30 29 28 27 26 25

TSB41AB1

AGND AVDD R1 R0 AGND TPBIAS TPA+ TPA TPB+ TPB AGND AVDD

LPS DGND C/LKON PC0 PC1 PC2 ISO CPS DV DD TESTM SE SM

Figure 8-12

EN 62

8.

3139 785 3093x

Circuit- and IC Description

PIN DESCRIPTION
TERMINAL NAME AGND AVDD PHP NO. 26, 32, 36 25, 35 TYPE Supply Supply I/O DESCRIPTION Analog circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. Analog circuit power terminals. A combination of high frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DVDD inside the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. Bus manager contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-k resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this terminal should be programmed low, and that the contender status be set via the C register bit. If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status, then a 1-k series resistor should be placed on the LKON line between the PHY and LLC to prevent bus contention. Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high-impedance. The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when: a) the PHY receives a link-on PHY packet addressed to this node, or b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-time-out interrupt), CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. Once activated, the link-on output continues active until the LLC becomes active (both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus reset occurs unless the link-on output would otherwise be active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). NOTE: If an interrupt condition exists which would otherwise cause the link-on output to be activated if the LLC were inactive, the link-on output is activated when the LLC subsequently becomes inactive. Cable-not-active output. This terminal is asserted high when there is no incoming bias voltage. Cable power status input. This terminal is normally connected to cable power through a 400-k resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. This terminal should be tied directly to DVDD supply if application does not require it to be used. Control I/Os. These bidirectional signals control communication between the TSB41AB1 and the LLC. Bus holders are built into these terminals. Data I/Os. These are bidirectional data signals between the TSB41AB1 and the LLC. Bus holders are built into these terminals.

C/LKON

15

CMOS

I/O

CNA CPS

N/A 20

CMOS CMOS

O I

CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7

2 3 4 5 6 7 8 9 10 11

CMOS CMOS

I/O I/O

Circuit- and IC description

3139 785 3093x

8.

EN 63

TERMINAL NAME DGND DVDD PHP NO. 14, 46, 47 21, 44, 45 TYPE Supply Supply I/O DESCRIPTION Digital circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. Digital circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD inside the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter required for stable operation of the internal frequency multiplier PLL running from the crystal oscillator. A 0.1 F 10% capacitor is the only external component required to complete this filter. Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO terminal should be tied high to disable the differentiation logic. For additional information refer to TI application note Galvanic Isolation of the IEEE 1394-1995 Serial Bus, SLLA011. Link power status input. This terminal monitors the active/power status of the link layer controller and controls the state of the PHY-LLC interface. This terminal should be connected through a 10-k resistor either to the VDD supplying the LLC, or to a pulsed output which is active when the LLC is powered (see Figure 9). A pulsed signal should be used when an isolation barrier exists between the LLC and PHY. (See Figure 10.) The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 s (128 SYSCLK cycles), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 s). The LPS input must be high for at least 21 ns to guarantee that a high is observed by the PHY . When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LLC request input. The LLC uses this input to initiate a service request to the TSB41AB1. Bus holder is built into this terminal. Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. Refer to Table 9 for encoding. Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)

FILTER0 FILTER1

38 39

CMOS

I/O

ISO

19

CMOS

LPS

13

CMOS

LREQ PC0 PC1 PC2 PD

48 16 17 18 12

CMOS CMOS

I I

CMOS

EN 64

8.

3139 785 3093x

Circuit- and IC Description

TERMINAL NAME PLLGND PLLVDD PHP NO. 41 40 TYPE Supply Supply I/O DESCRIPTION PLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise isolation. It should be tied at a low-impedance point on the circuit board. Current setting resistor terminals. These terminals are connected through an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1.0% is required to meet the IEEE Std 1394-1995 output voltage limits. Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal may be tied to GND through a 1-k pulldown resistor or it may be tied to GND directly. Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to VDD. Twisted-pair cable A differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. Twisted-pair cable B differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Information section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is powered on.

R0 R1

33 34

Bias

RESET

37

CMOS

SE

23

CMOS

SM SYSCLK TESTM TPA+ TPA TPB+ TPB TPBIAS

24 1 22 30 29 28 27 31

CMOS CMOS CMOS Cable Cable Cable Cable Cable

I O I I/O I/O I/O I/O I/O

XI XO

42 43

Crystal

Circuit- and IC description

IC7401 - TVP5146PFP - 4x10bit DigitalVideo Decoder with microvision

3139 785 3093x

8.

EN 65

BLOCK DIAGRAM

Copy Protection Detector Analog Front End VI_1_A VI_1_B VI_1_C VI_2_A CVBS/ Y/G VI_2_B VI_2_C VI_3_A CVBS/ Pr/R/C VI_3_B VI_3_C ADC3 ADC2 M U X

CVBS/Y/G

VBI Data Slicer

CVBS/ Pb/B/C

Composite and S-Video Processor ADC1 CVBS/Y C Y/C Separation 5-line Adaptive Comb Y C Luma Processing Chroma Processing Output Formatter Component Processor Color Space Conversion YCbCr

YCbCr Y[9:0] C[9:0] FSS

Y/G Pb/B Pr/R

Gain/Offset

CVBS/Y VI_4_A

ADC4

GPIO Sampling Clock Timing Processor with Sync Detector

Host Interface

XTAL1

XTAL2

VS/VBLK

AVID

GLCO

DG

DR

DB

FSO

SCL
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42

DATACLK

RESETB

Figure 8-13

PIN CONFIGURATION
PFP PACKAGE (TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD

VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID/GPIO C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD

HS/CS

PWDN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

C_6/GPIO/RED C_7/GPIO/GREEN C_8/GPIO/BLUE C_9/GPIO/FSO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD

CH4_A33VDD CH4_A33GND VI_4_A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS/GPIO AVID/GPIO GLCO/I2CA IOVDD IOGND DATACLK

Figure 8-14

SDA

FID

EN 66

8.

3139 785 3093x

Circuit- and IC Description

PIN DESCRIPTION
TERMINAL NAME Analog Video VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A Clock Signals DATACLK XTAL1 XTAL2 Digital Video 57, 58, 59, 60, 63, 64, 65, 66, 69, 70 58 59 60 57 43, 44, 45, 46, 47, 50, 51, 52, 53, 54 Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Unused outputs can be left unconnected. Also, these terminals can be programmable general-purpose I/O. For the 8-bit mode, the two LSBs are ignored. I I I I Digital BLUE input from overlay device Digital GREEN input from overlay device Digital RED input from overlay device Fast-switch overlay between digital RGB and any video Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB. For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected. 40 74 75 O I O Line-locked data output clock. External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock signal or a 14.31818-MHz crystal oscillator. External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator. 80 1 2 7 8 9 16 17 18 23 I VI_1_x: Analog video input for CVBS/Pb/B/C VI_2_x: Analog video input for CVBS/Y/G VI_3_x: Analog video input for CVBS/Pr/R/C VI_4_A: Analog video input for CVBS/Y Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof) can be supported. The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 F. The possible input configurations are listed in the input select register at I2C subaddress 00h (see Section 2.11.1). NUMBER I/O DESCRIPTION

C[9:0]/ GPIO[9:0]

D_BLUE D_GREEN D_RED FSO

Y[9:0]

Miscellaneous Signals FSS/GPIO 35 I/O Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB) and the composite video input. Programmable general-purpose I/O GLCO/I2CA INTREQ PWDN RESETB 37 30 33 34 I/O O I I Genlock control output (GLCO). Two Genlock data formats are available: TI format and real time control (RTC) format. During reset, this terminal is an input used to program the I2C address LSB. Interrupt request Power down input: 1 = Power down 0 = Normal mode Reset input, active low

Circuit- and IC description

3139 785 3093x

8.

EN 67

TERMINAL NAME Host Interface SCL SDA Power Supplies AGND A18GND_REF A18VDD_REF CH1_A18GND CH2_A18GND CH3_A18GND CH4_A18GND CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD CH1_A33GND CH2_A33GND CH3_A33GND CH4_A33GND CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD DGND DVDD IOGND IOVDD PLL_A18GND PLL_A18VDD Sync Signals HS/CS/GPIO VS/VBLK/GPIO FID/GPIO AVID/GPIO 72 73 71 36 I/O I/O I/O I/O Horizontal sync output or digital composite sync output Programmable general-purpose I/O Vertical sync output (for modes with dedicated VSYNC) or VBLK output Programmable general-purpose I/O Odd/even field indicator output. This terminal needs a pulldown resistor. Programmable general-purpose I/O Active video indicator output Programmable general-purpose I/O 26 13 12 79 10 15 24 78 11 14 25 3 6 19 22 4 5 20 21 27, 32, 42, 56, 68 31, 41, 55, 67 39, 49, 62 38, 48, 61 77 76 I I I Analog ground. Connect to analog ground. Analog 1.8-V return Analog power for reference 1.8 V 28 29 I I/O I2C clock input I2C data bus NUMBER I/O DESCRIPTION

Analog 1.8-V return

Analog power. Connect to 1.8 V.

Analog 3.3-V return

Analog power. Connect to 3.3 V.

I I I I I I

Digital return Digital power. Connect to 1.8 V. Digital power return Digital power. Connect to 3.3 V or less for reduced noise. Analog power return Analog power. Connect to 1.8 V.

EN 68

8.

3139 785 3093x

Circuit- and IC Description

IC7501 - TPS2041 - Power Distribution Switches

BLOCK DIAGRAM

Power Switch IN Charge Pump Current Limit OC UVLO Thermal Sense CS OUT

EN

Driver

GND Current Sense

Figure 8-15

PIN CONFIGURATION

TPS2041 D OR P PACKAGE (TOP VIEW)

GND IN IN EN

1 2 3 4

8 7 6 5

OUT OUT OUT OC

Figure 8-16

Circuit- and IC description PIN DESCRIPTION

TERMINAL NO. NAME EN EN GND IN OC OUT 4 1 2, 3 5 6, 7, 8 D OR P TPS2041 TPS2051 4 1 2, 3 5 6, 7, 8 I I I I O O I/O

3139 785 3093x

8.

EN 69

DESCRIPTION

Enable input. Logic low turns on power switch. Enable input. Logic high turns on power switch. Ground Input voltage Over current. Logic output active low Power-switch output

IC7521 - L5972D - 2A Switch Step Down Switching Regulator

PIN DESCRIPTION AND CONFIGURATION

PIN CONNECTION

OUT GND GND COMP

1 2 3 4
D02IN1367

8 7 6 5

VCC GND GND FB

PIN DESCRIPTION
N 1 2,3,6,7 4 5 8 Pin OUT GND COMP FB VCC Regulator Output. Ground. E/A output for frequency compensation. Feedback input. Connecting directly to this pin results in an output voltage of 1.23V. An external resistive divider is required for higher output voltages. Unregulated DC input voltage. Function

EN 70

8.

3139 785 3093x

Circuit- and IC Description

IC7595 - NCP303 - Voltage Detector Series with Programmable Delay

BLOCK DIAGRAM
NCP303LSNxxT1 Open Drain Output Configuration 2 Input 1 Reset Output

RD

Vref

Gnd

CD

Figure 8-17

PIN DESCRIPTION AND CONFIGURATION

PIN CONNECTIONS AND MARKING DIAGRAM

Reset Output Input Ground 1 xxxYW 2 3 5 CD

4 N.C.

xxx = 302 or 303 Y = Year W = Work Week (Top View)

Figure 8-18

Exploded View & Spare Parts List

3139 785 3093x

9.

EN 71

P003

Figure 9-1

P001

P002

3139 249 2798 2005-03-02

Exploded View of the Set

EN 72

9.

3139 785 3093x

Exploded View & Spare Parts List

Spare Parts List 0002 0164 0168 0196 0228 0288 0333 0333 0336 0336 0342 0345 0901 0901 0901 0901 0901 0901 0910 0910 0910 0920 1001 1001 1001 1001 1001 1001 1001 1001 1001 1003 1003 1003 1004 1004 1005 1005 8002 8003 8004 8007 8008 8010 8011 3139 247 11131 3103 601 20231 3103 601 20212 3139 241 22761 3139 241 22791 4822 532 60948 2422 549 00607 2422 549 00611 4822 321 11499 2422 070 98236 2422 076 00532 4822 320 50377 3143 027 62231 3143 027 62261 3143 027 62311 3143 027 62331 3143 027 62681 3143 027 62701 3143 027 61951 3143 027 62351 3143 027 62411 3143 027 62251 3139 248 86731 3139 248 84651 3139 248 86721 3139 248 86691 3139 248 86061 3139 248 86681 3139 248 86711 3139 248 85941 3139 248 86701 3139 248 84591 3139 248 86561 3139 248 86291 3139 248 84751 3139 248 86551 3139 248 84631 3139 248 86571 3139 110 35631 3139 241 01081 3139 241 00241 3139 241 00591 3139 241 01011 3139 241 00921 2422 076 00676 MODULE DRIVE D4.3 SPRING GROUND SPRING I-LINK COVER TOP DVDR3305 PLATE REAR EU DVDR3305 BUSH REMOTE CONTR DVDR3365/EU B REMOTE CONTR DVDR3355/DVDR3305 MAINSCORD /02, /19, /51 only MAINSCORD UK 5A 1M8 VH BK B /05 only CBLE SCART 1M5 SCART 21P BK B CONNECT. CABLE PAL FRONT ASSY DVDR3365 /02, /19, /51 only FRONT ASSY DVDR3365 /05 only FRONT ASSY DVDR3355 /02, /19, /51 only FRONT ASSY DVDR3355 /05 only FRONT ASSY DVDR3305 /02, /19, /51 only FRONT ASSY DVDR3355 /05 only COVER TRAY ASSY DVDR3365 COVER TRAY ASSY DVDR3355 COVER TRAY ASSY DVDR3305 FRAME ASSY DIGITAL BOARD DVDR3365 /05 only DIGITAL BOARD DVDR3365 /02, /19 only DIGITAL BOARD DVDR3365 /51 only DIGITAL BOARD DVDR3305 /05 only DIGITAL BOARD DVDR3305 /02, /19 only DIGITAL BOARD DVDR3305 /51 only DIGITAL BOARD DVDR3355 /05 only DIGITAL BOARD DVDR3355 /02, /19 only DIGITAL BOARD DVDR3355 /51 only FRONT BOARD DVDR3365 FRONT BOARD DVDR3305 FRONT BOARD DVDR3355 STB BOARD DVDR 3355/DVDR3365 STB BOARD DVDR 3305 ANALOG BOARD DVDR3355/DVDR3365 ANALOG BOARD DVDR3305 FFC FOIL 22P/180/22P BD 1MMP FFC FOIL 20P/140/20P BD 1MMP FFC FOIL 30P/140/30P BD 1MMP CBLE HR 04P/220/04P LOADER SUP FFC FOIL 14P/180/14P BD 1MMP CBLE IDE 40P/280/40P IDE UL CBLE IEEE1394 DVDR3355/DVDR3365

Revision List
10. REVISION LIST
Version 1.0 * Original Release Version 1.1 * Add missing Exploded View drawing

3139 785 3093x

10.

EN 73