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ECE448 Lecture15 External SRAM

The document discusses a lecture about external SRAM. It covers the basic block diagram and timing of SRAM, including read and write cycles. It also discusses the role and design of memory controllers for accessing external SRAM from an FPGA or ASIC, showing state machine charts for different controller designs.

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121 views18 pages

ECE448 Lecture15 External SRAM

The document discusses a lecture about external SRAM. It covers the basic block diagram and timing of SRAM, including read and write cycles. It also discusses the role and design of memory controllers for accessing external SRAM from an FPGA or ASIC, showing state machine charts for different controller designs.

Uploaded by

Aziz Pro
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Lecture 15

External SRAM

ECE 448 FPGA and ASIC Design with VHDL

Required reading
P. Chu, FPGA Prototyping by VHDL Examples

Chapter 10, External SRAM

ECE 448 FPGA and ASIC Design with VHDL

Block diagram of a typical SRAM

ECE 448 FPGA and ASIC Design with VHDL

SRAM Functional Table

ECE 448 FPGA and ASIC Design with VHDL

SRAM Simplified Functional Table

ECE 448 FPGA and ASIC Design with VHDL

Timing diagram of an address-controlled read cycle

ECE 448 FPGA and ASIC Design with VHDL

Timing diagram of an output_enable-controlled read cycle

ECE 448 FPGA and ASIC Design with VHDL

SRAM Timing Parameters (in ns)

ECE 448 FPGA and ASIC Design with VHDL

Timing diagram of write cycle

ECE 448 FPGA and ASIC Design with VHDL

SRAM Timing Parameters (in ns)

ECE 448 FPGA and ASIC Design with VHDL

10

Role of a memory controller

ECE 448 FPGA and ASIC Design with VHDL

11

Block diagram of a memory controller

ECE 448 FPGA and ASIC Design with VHDL

12

ASM chart of a safe SRAM controller

ECE 448 FPGA and ASIC Design with VHDL

13

ASM chart of a testing circuit

ECE 448 FPGA and ASIC Design with VHDL

14

ASM chart of an alternative SRAM controller: design I

ECE 448 FPGA and ASIC Design with VHDL

15

ASM chart of an alternative SRAM controller: design II

ECE 448 FPGA and ASIC Design with VHDL

16

ASM chart of an alternative SRAM controller: design III

ECE 448 FPGA and ASIC Design with VHDL

17

Generating a half cycle with DDR

ECE 448 FPGA and ASIC Design with VHDL

18

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