Memory Access

Steps in Address Mapping

Memory Access Modes

COMP375 Computer Architecture and O d Organization i ti

Programmer selects a variable name. Compiler allocates space and selects a relative address. Linker combines object files and updates references to relative address to be p g program addresses. Operating system allocates memory for the program and copies it into RAM.

Relocatable Address Adjustment

Relocatable Object Files
0 0 50 100 150 100 0 50 0 100 101 151 152 0

Adjusting Addresses
When the linker combines object files to create an executable, it goes th t t bl through th h the program and adjusts every address. When a program is executed, it is loaded into memory. The hardware adjusts each program relative address to a hardware address.

Executable
0 0

150

302

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Program Memory Types

Global variables
Data segment

Program Memory Organization

Program instructions Global data

Local variables and parameters

Stack

Dynamic variables
Heap

Constants
Data segment or instruction segment

Stack Heap
Intel method

Instructions
Instruction segment

Effective Address
The effective address (or logical address ) p g or virtual address) is the program relative address. The hardware maps the effective address to the physical address. Different programs in different physical addresses may h dd have the same effective h ff i address. Effective addresses can be the result of address calculations.

Where is the data?

The operands for an instruction can be in RAM, RAM a register or i th i t ti i t in the instruction. The instruction specifies where the operand is located. There are several ways the operands address can be specified specified. Different addressing modes have been created for different program situations.

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Addressing modes
immediate register i t memory direct register indirect register indirect with offset memory indirect register + offset memory indirect displacement

Immediate
The data is part of the instruction. Immediate data items are read-only. There is usually a size limit.
Instruction address

data register

data
memory

Register
The data is in a CPU register. The instruction might indicate which register

Memory Direct
The data is in memory. The instruction contains the address of the memory location.
Instruction address

Instruction

address

data register

data
memory

data register

data
memory

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Register Indirect
The address of the data is in a CPU register. i t Useful if the address is calculated.
Instruction address

Register Indirect with Offset

The address of the data is the sum of the instruction ff t fi ld d i t ti offset field and a register value. i t l Useful when addressing an array.
Instruction address

data register

data
memory

data register

data
memory

Memory Indirect
A memory location contains the address of the d t th data. Useful for pointers.
Instruction address

Register Offset & Memory Indirect

The sum of the instruction offset field and a register value gives the location of the address in memory. Useful when addressing ref parameters.
Instruction address

data register

data
memory

data register

data
memory

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Displacement
The address of the data is the sum of the instruction offset field and the program counter. Used for short jumps
Instruction address

Stack Addressing
The same as Register Indirect with Offset using the stack pointer register Useful when addressing local variables or parameters.
Instruction address

Program Counter

instruction
memory

stack pointer register

data
memory

Function Calls
Add

What are the Instructions?

Opcodes Subtract 1 Multiply 2 Divide 3 Load 4 Store 5 JumpEql 6 Jump 7 0

To call a function or method, the program counter is pushed on th stack and th t i h d the t k d then the program counter is loaded with the address of the function. This puts the address of the instruction after the function call on the stack. To return the return address is popped from the stack and loaded into the program counter.

Instruction Formats opcode 3 register 4 opcode 3

1 2 3 4 5 6 7 8 9 1 0

index register 4
unused

memory address 21 reg 1 4 reg 2 4

1 4 1 5 1 6 1 7 1 8

LoadandStore

reg 3 4
1 9 2 0 2 1

Add,Sub,MultandDivide
2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2

1
1 1 1 2 1 3

1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

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Notes on the Example Architecture

This is an example of a Load/Store architecture. O l th l d and store hit t Only the load d t instructions access memory. Why is there a one bit unused field in the arithmetic instructions? Why is the opcode always the left most bits? The format of the jump instructions was not shown. What might be a good format?

Instruction Cycle
Fetch the instruction from the memory address i th P dd in the Program C Counter register t i t Increment the Program Counter Decode the type of instruction Fetch the operands Execute the instruction Store the results

Basic Processor Components

Program Counter contains the address of the next instruction to execute. f th t i t ti t t Arithmetic Logic Unit logic to perform arithmetic and logical functions User registers hold data Memory Address Register contains the address to be copied to or from RAM Memory Buffer Register contains data copied to or from RAM.

Instruction Fetch
R1 ProgramCounter InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryRead MemoryBufferReg

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Instruction Fetch
R1 ProgramCounter InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryBufferReg ReadResult

Increment Program Counter

R1 ProgramCounter InstructionRegister ALU +1 MemoryAddressReg MemoryBufferReg R2 ... R16

Increment Program Counter

R1 ProgramCounter InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryBufferReg

Decode Instruction
R1 ProgramCounter InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryBufferReg

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Operand Fetch
R1 ProgramCounter InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryRead MemoryBufferReg ProgramCounter

Operand Fetch
R1 InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryBufferReg ReadResult

Execution
R1 ProgramCounter InstructionRegister ALU R2 ... R16 MemoryAddressReg MemoryBufferReg MemoryAddressReg ProgramCounter

Result Store
R1 InstructionRegister ALU R2 ... R16 MemoryBufferReg

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Jump Instruction
Consider an arithmetic instruction followed by jump i t ti b aj instruction. The arithmetic instruction sets bits in the status register

Execution Stage of Instruction 1

Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg

Result Save Stage of Instruction 1

Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg

Instruction 2 Fetch
Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryRead MemoryBufferReg

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Instruction 2 Fetch
Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg ReadResult

Increment Program Counter

Status Register ProgramCounter InstructionRegister ALU +1 MemoryAddressReg MemoryBufferReg R1 R2 ... R16

Increment Program Counter

Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg

Decode Instruction
Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg

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Execution of Instruction 2
Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg

Saving Result of Instruction 2

Status Register ProgramCounter InstructionRegister ALU R1 R2 ... R16 MemoryAddressReg MemoryBufferReg

Goals for Instruction Set

The purpose of the machine language is to run th applications. the li ti Compilers should be able to translate high level languages into machine language. Run fast

RISC vs. CISC

Complex Instruction Set Computers
many instructions some instructions can perform complex operations. each instruction may take several cycles

Reduced Instruction Set Computers

fewer instructions many RISC machines run 1 instruction / cycle

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CISC Theory
The machine language should be designed t b as close as possible t th d i d to be l ibl to the application requirements. Machine instructions should support high level language constructs.

RISC Theory
Many complex instructions are rarely executed. M t programs use only a t d Most l small set of instructions. The few important instructions should run as fast as possible. If you have to do something complex, use complex several fast simple instructions. Registers are much faster than RAM.

PDP-8 Instruction Set

The PDP-8 was a popular mini computer y made by DEC in the 1970s. The 12 bit fixed length instructions had a 3 bit op code, an address field and two addressing mode bits. There were 7 instructions with the normal format. One op code was for zero operand instructions. The remaining bits of the instruction specified what to do.

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