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U I - Lecture 4 Basic Principle of Low Power Design

The document discusses the basic principles of low power design in CMOS circuits. It explains that the main sources of power dissipation are charging and discharging capacitance, short circuit current, diode leakage current, and subthreshold channel leakage. The key techniques to reduce power consumption are to reduce switching voltage, capacitance, switching frequency, and leakage/static current. It also introduces various figures of merit used to evaluate the power efficiency of chips, such as μW/MIPS, μW/SPEC, and energy delay product.

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3K views

U I - Lecture 4 Basic Principle of Low Power Design

The document discusses the basic principles of low power design in CMOS circuits. It explains that the main sources of power dissipation are charging and discharging capacitance, short circuit current, diode leakage current, and subthreshold channel leakage. The key techniques to reduce power consumption are to reduce switching voltage, capacitance, switching frequency, and leakage/static current. It also introduces various figures of merit used to evaluate the power efficiency of chips, such as μW/MIPS, μW/SPEC, and energy delay product.

Uploaded by

bganeshsai
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
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UNIT - I POWER DISSIPATION IN CMOS

Presented By S.Kirubaveni Assistant Professor, ECE Dept

Presentation Outline
Lecture 2: Physics of Power Dissipation in CMOS FET devices Lecture 3: Sources of Power Consumption Lecture 4: Basic Principle of Low Power Design Lecture 5: Hierarchy of Limits of Power

Objectives
To learn the basic principles of Low Power Design
Reduce Reduce Reduce Reduce Switching Voltage Capacitance Switching Frequency Leakage & Static Current

To understand the Low Power Figure of Merits.

Basic Principles of Low Power Design


The fundamental modes of power dissipations in CMOS VLSI circuits are given by the equations. By examining the equations, several basic principles of low power design techniques can be uncovered. Charging & Discharging Capacitance Short Circuit Current Diode Leakage Current Subthreshold Channel Leakage

Reduce Switching Voltage


The dynamic power of digital chips is generally the largest portion of power dissipation. The P =CV2 equation consists of three terms: Voltage, Capacitance and Frequency. Due to the quadratic effect of the voltage term, reducing the switching voltage can achieve dramatic savings. The easiest method to achieve this is to reduce the operating voltage of the CMOS circuit. Other methods seek to reduce voltage swing by using well-known circuit techniques such as charge sharing, transistor threshold voltage, etc.

Reduce Switching Voltage


There are many trade-offs to be considered in voltage reduction. Performance is lost because MOS transistors become slower at lower operating voltages. The main reason is that the threshold voltages of the transistors do not scale accordingly with the operating voltage to avoid excessive leakage current. Noise immunity is also a concern at low voltage swing. Special level converters are required to interface low swing signals to the full-swing ones.

Reduce Capacitance
Reducing parasitic capacitance in digital design has always been a good way to improve performance as well as power. However, a blind reduction of capacitance may not achieve the desired result in power dissipation. The real goal is to reduce the product of capacitance and its switching frequency. Signals with high switching frequency should be routed with minimum parasitic capacitance to conserve power. Conversely, nodes with large parasitic capacitance should not be allowed to switch at high frequency.

Reduce Switching Frequency


For the sake of power dissipation, the techniques for reducing switching frequency have the same effect as reducing capacitance. Again, frequency reduction is best applied to signals with large capacitance. The techniques are often applied to logic level design and above. Those applied at a higher abstraction level generally have greater impact. Reduction of switching frequency also has the side effect of improving the reliability of a chip as some failure mechanism is related to the switching frequency.

Reduce Switching Frequency


One effective method of reducing switching frequency is to eliminate logic switching that is not necessary for computation. Other methods involve alternate logic implementation since there are many ways to design a logic network to perform an identical function. The use of different coding methods,

number representation systems, counting sequences and data representations can directly alter the
switching frequency of a design.

Reduce Leakage & Static Current


Leakage current, whether reverse biased junction or subthreshold current, is generally not very useful in digital design. However, designers often have very little control over the leakage current of the digital circuit. Fortunately, the leakage power dissipation of a CMOS digital circuit is several orders of magnitude smaller than the dynamic power. The leakage power problem mainly appears in very low frequency circuits or ones with "sleep modes" where dynamic activities are suppressed.

Reduce Leakage & Static Current


Most leakage reduction techniques are applied at low-level design abstraction such as process, device and circuit design. Memory chips that have very high device density are most susceptible to high leakage power. Static current can be reduced by transistor sizing, layout techniques and careful circuit design. Circuit modules that consume static current should be turned off if not used. Sometimes, static current depends on the logic state of its output and we can consider reversing the signal polarity to minimize the probability of static current flow.

Low Power Figure of Merits


Power Consumption in Watts
Watt is the absolute measure of power consumed by a chip or a system Used in total power specification Useful for packaging considerations, system power supply & cooling requirements

Peak Power
The maximum power consumption of a chip at any time Useful for power ground wiring design, signal noise margin & reliability analysis.

Low Power Figure of Merits


Power Efficiency of a Chip
A chip operates at a higher frequency can perform faster computation and hence consume more power. Watt is no longer useful. Power is the rate at which energy is consumed over time. Energy in Joules becomes important W/MHz in numbers A low energy number is desirable because it requires less power to perform computation at the same frequency.

Low Power Figure of Merits


Power Efficiency of a Chip
Different processors require different number of clock cycles for the same operation so W/MHz in numbers is not suitable. W/MIPS or A/MIPS with unit WattSecond per Instruction is introduced. MIPS is a measure of the performance level of a processor. This FOM is only useful when comparing power efficiency of two processors with similar instruction sets.

Low Power Figure of Merits


Power Efficiency of a Chip
When comparing two processor chips with different instruction sets or architecture W/MIPS or A/MIPS is still not suitable Example: CISC Vs RISC Vs VLIW Processors

W/SPEC is introduced
SPEC is a measure of computation speed derived from executing some standard benchmarks software programs written in machine independent high level programming language

Low Power Figure of Merits


Power Efficiency of a Chip
W/MIPS and W/SPEC
Measure energy consumption of a typical instruction or operation regardless of the processors performance rating. Encompass the merits of chip fabrication technology as well as architecture and circuit design techniques.

Other Measures
Energy Delay Product Used to assess the merits of a logic style.

Conclusion
The following basic principles of Low Power Design are discussed
Reduce Reduce Reduce Reduce Switching Voltage Capacitance Switching Frequency Leakage & Static Current

The Low Power Figure of Merits are introduced.

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