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ECE 223 Boolean Algebra

This document provides an overview of Boolean algebra and logic gates covered in ECE 223 Digital Circuits and Systems. It introduces binary logic, basic logic gates (AND, OR, NOT), truth tables, Boolean algebra postulates and theorems. It also discusses logic functions, minterms and maxterms, standard forms, other logic gates (NAND, NOR, XOR, XNOR), and positive and negative logic. Finally, it briefly discusses the evolution of integrated circuits and different digital logic families.

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0% found this document useful (0 votes)
57 views

ECE 223 Boolean Algebra

This document provides an overview of Boolean algebra and logic gates covered in ECE 223 Digital Circuits and Systems. It introduces binary logic, basic logic gates (AND, OR, NOT), truth tables, Boolean algebra postulates and theorems. It also discusses logic functions, minterms and maxterms, standard forms, other logic gates (NAND, NOR, XOR, XNOR), and positive and negative logic. Finally, it briefly discusses the evolution of integrated circuits and different digital logic families.

Uploaded by

plmko1
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 223 Digital Circuits and Systems

Boolean Algebra & Logic Gates


M. Sachdev,
Dept. of Electrical & Computer Engineering University of Waterloo

Binary (Boolean) Logic


Deals with binary variables and binary logic functions
Has two discrete values
0 1 False, Open True, Close

Three basic logical operations


AND (.); OR (+); NOT ()

Logic Gates & Truth Tables


AND
AND A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A 0 0 1 1

OR
OR B 0 1 0 1 A+B 0 1 1 1 A 0 1

NOT
NOT A 1 0

AND; OR gates may have any # of inputs


AND 1 if all inputs are 1; 0 other wise OR 1 if any input is 1; 0 other wise
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Boolean Algebra
Branch of Algebra used for describing and designing two valued state variables
Introduced by George Boole in 19th centaury Shannon used it to design switching circuits (1938)

Boolean Algebra Postulates


An algebraic structure defined by a set of elements, B, together with two binary operators + and . that satisfy the following postulates:
1.

Postulate 1:
Closure with respect to both (.) and ( +)

2.

Postulate 2:
An identity element with respect to +, designated by 0. An identity element with respect to . designated by 1
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Boolean Algebra - Postulates


3. 4. 5.

Postulate 3:
Commutative with respect to + and .

Postulate 4:
Distributive over . and +

Postulate 5:
For each element a of B, there exist an element a such that (a) a + a = 1 and (b) a.a = 0

6.

Postulate 6:
There exists at least two elements a, b in B, such that a b

Boolean Algebra - Postulates


Postulates are facts that can be taken as true; they do not require proof
We can show logic gates satisfy all the postulates

AND A 0 0 1 1 B 0 1 0 1 A.B 0 0 0 1 A 0 0 1 1

OR B 0 1 0 1 A+B 0 1 1 1 A 0 1

NOT A 1 0

Boolean Algebra - Theorems


Theorems help us out in manipulating Boolean expressions
They must be proven from the postulates and/or other already proven theorems

Exercise Prove theorems from postulates/other proven theorems

Boolean Functions
x y F1

Are represented as
Algebraic expressions; F1 = x + yz Truth Table

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

F1 0 1 0 0 1 1 1 1
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Synthesis
Realization of schematic from the expression/truth table

Analysis
Vice-versa

Synthesis F1
x y z F1

Assume true as well as complement inputs are available Cost


A 2-input AND gate A 2-input OR gate 4 inputs

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

F1 0 1 0 0 1 1 1 1
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Canonical and Standard Forms


Minterms
A minterm is an AND term in which every literal (variable) of its complement in a function occurs once For n variable 2n minterms Each minterm has a value of 1 for exactly one combination of values of n variables (e.g., n = 3)

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Minterms
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Corresponding minterm xyz xyz xyz xyz xyz xyz xyz xyz Designation m0 m1 m2 m3 m4 m5 m6 m7

One method of Writing Boolean function is the canonical minterm (sum of products or SOP) form
F = xyz +xyz + xyz = m1 + m5 + m6 = (1,5,6)
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Minterms examples
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F2 (Given) 1 1 1 1 0 1 0 0 m5 Designation m0 m1 m2 m3

F2 = (0,1,2,3,5) = xyz + xyz + xyz + xyz + xyz


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Minterms examples
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F2 (Given) 1 1 1 1 0 1 0 0 m5 Designation m0 m1 m2 m3

(F2)

= (all minterms not in F2) = (4,6,7)

= xyz + xyz + xyz


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Maxterms
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Corresponding maxterm x +y +z x +y +z x +y +z x +y +z x +y +z x +y +z x +y +z x +y +z Designation M0 M1 M2 M3 M4 M5 M6 M7

A maxterm is an OR term in which every literal (variable) or its complement in a function occurs once
Each maxterm has a value 0 for one combination of values of n variables
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Minterms & Maxterms


Conversion between minterms & maxterms
m0 = xyz = (x+y+z) = (M0) In general, mi = (Mi)

An alternative method of writing a Boolean function is the canonical maxterm (product of sums or POS) form The canonical product of sums can be written directly from the truth table

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Maxterms
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F3 (Given) 0 1 0 0 0 1 1 0 M7 M2 M3 M4 Designation M0

F3 (F3)

= (x+y+z)(x+y+z)(x+y+z)(x+y+z)(x+y+z)
= (0,2,3,4,7)

= (all maxterm not in F3)


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Standard Forms
In canonical forms, each minterm (or maxterm) must contain all variables (or its complements)
The algebraic expressions can further be simplified

Example
F4 (x,y,z) = xy +yz (sum of products, standard form) F5 (x,y,z) = (x+y)(y+z) (product of sums, standard form)

Conversion
Standard form can be converted into canonical form using identity elements

F4 = xy + yz = xy.1 +1.yz = xy(z+z) + (x+x)yz = xyz + xyz + xyz + xyz = m7 +m6 +m5 +m1 How about the conversion from canonical forms to standard forms? Exercise convert F5 into maxterms
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Non-Standard Forms
A Boolean function may be written in non-standard form
F6 (x,y,z) = (xy + z)(xz + yz) = xy(xz + yz) + z(xz + yz) = xyz + xyyz + xz +yz = xyz + xz + yz = xz + yz (standard form)

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Other Logic Gates NAND Gate


So far, we discussed AND, OR, NOT gates
2-input NAND (NOT-AND operation) Can have any # of inputs NAND gate is not associative
Associative property to be discussed later x
x 0 0 1 1 y 0 1 0 1 z 1 1 1 0

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Other Logic Gates NOR Gate


2-input NOR (NOT-OR operation)
Can have any # of inputs NOR gate is not associative
Associative property to be discussed later

x
x 0 0 1 1 y 0 1 0 1 z 1 0 0 0

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Other Logic Gates XOR Gate


2-input XOR
Output is 1 if any input is one and the other input is 0 Can have any # of inputs

x
x 0 0 1 1 y 0 1 0 1 z 0 1 1 0

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Other Logic Gates XNOR Gate


2-input XNOR
Performs the NOT-XOR operation
Output is 1 if both inputs are 1; or both inputs are 0

Can have any # of inputs

x
x 0 0 1 1 y 0 1 0 1 z 1 0 0 1

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Extension to Multiple Inputs


So far, we restricted ourselves to 1 or 2-input gates
A logic gate (except inverter) can have any number of inputs

AND, OR logic operations have two properties


x +y = y +x (x +y)+ z = x + (y +z) = x +y +z (commutative) (associative)

NAND and NOR operations are commutative, but not associative


(xy)z x(yz) (xy)z x(yz) = NOR operation = NAND operation

How about XOR

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Positive & Negative Logic


Positive Logic
0 = False 1 = True (Low Voltage) (High Voltage) (High Voltage) (Low Voltage)
x L L H H y L H L H z L L L H

Negative Logic
0 = True 1 = False

Implement truth table with positive & negative logic


Positive logic Negative logic AND gate ?

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Integrated Circuit - Evolution


Transistor was invented in 1947/48 Integrated Circuits were invented in 1959/60
101 Since then, larger # of transistors/chip are integrated Small Scale Integration 102-3 Medium Scale Integration 3-6 10 Large Scale Integration 106-9 Very Large Scale Integration

Digital Logic Families (technologies)


TTL ECL MOS CMOS Transistor-Transistor Logic Emitter Coupled Logic Metal Oxide Semiconductor Complementary Metal Oxide Semiconductor

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Book Sections Boolean Algebra & Logic Gates


Material is covered in Sections 2.1 2.8

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