INTEGRATED CIRCUITS

DATA SHEET
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The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

74HC/HCT74 Dual D-type flip-flop with set and reset; positive-edge trigger
Product specication Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

FEATURES Output capability: standard ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns

74HC/HCT74

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL VCC2 fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC 1.5 V maximum clock frequency input capacitance power dissipation capacitance per ip-op notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 15 16 76 3.5 24 15 18 18 59 3.5 29 ns ns ns MHz pF pF HCT UNIT

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

ORDERING INFORMATION TYPE NUMBER 74HC(T)74N 74HC(T)74D 74HCT74DB 74HCT74PW PACKAGE NAME DIP14 SO14 SSOP14 TSSOP14 DESCRIPTION plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm

74HC/HCT74

VERSION SOT27-1 SOT108-1 SOT337-1

plastic shrink small outline package; 14 leads; body width 5.3 mm

plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

PIN DESCRIPTION PIN NO. 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1RD, 2RD 1D, 2D 1CP, 2CP 1SD, 2SD 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION asynchronous reset-direct input (active LOW) data inputs clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true ip-op outputs complement ip-op outputs ground (0 V) positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

FUNCTION TABLE INPUTS SD L H L RD H L L CP X X X

74HC/HCT74

OUTPUTS D X X X Q H L H Q L H H

INPUTS SD H H Note RD H H CP D L H

OUTPUTS Qn+1 L H Qn+1 H L

1. H = HIGH voltage level L = LOW voltage level X = dont care = LOW-to-HIGH CP transition Qn+1 = state after the next LOW-to-HIGH CP transition Fig.4 Functional diagram.

Fig.5 Logic diagram (one flip-flop).

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay nCP to nQ, nQ +25 40 to +85 40 to +125 min. max. 265 53 45 300 60 51 300 60 51 110 22 19 120 24 20 120 24 20 45 9 8 90 18 15 3 3 3 4.0 20 24 MHz ns ns ns ns ns ns ns ns ns UNIT

74HC/HCT74

TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6

typ. max. min. max 47 17 14 50 18 14 52 19 15 19 7 6 175 35 30 200 40 34 200 40 34 75 15 13 100 20 17 100 20 17 40 8 7 75 15 13 3 3 3 4.8 24 28 5 220 44 37 250 50 43 250 50 43 95 19 16

tPHL/ tPLH

propagation delay nSD to nQ, nQ propagation delay nRD to nQ, nQ output transition time

tPHL/ tPLH

tTHL/ tTLH

tW

clock pulse width HIGH or LOW

80 16 14 80 16 14 30 6 5 60 12 10 3 3 3 6.0 30 35

19 7 6 19 7 6 3 1 1 6 2 2 6 2 2 23 69 82

tW

set or reset pulse width LOW

trem

removal time set or reset

tsu

set-up time nD to nCP

th

hold time nCP to nD

fmax

maximum clock pulse frequency

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: flip-flops Note to HCT types

74HC/HCT74

The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT nD nRD nSD nCP

UNIT LOAD COEFFICIENT 0.70 0.70 0.80 0.80

AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tW trem tsu th fmax propagation delay nCP to nQ, nQ propagation delay nSD to nQ, nQ propagation delay nRD to nQ, nQ output transition time clock pulse width HIGH or LOW set or reset pulse width LOW removal time set or reset set-up time nD to nCP hold time nCP to nD maximum clock pulse frequency 18 16 6 12 3 27 +25 typ. 18 23 24 7 9 9 1 5 3 54 40 to +85 40 to +125 UNIT VCC WAVEFORMS (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.6 TEST CONDITIONS

max. min. max. min. max. 35 40 40 15 23 20 8 15 3 22 44 50 50 19 27 24 9 18 3 18 53 60 60 22 ns ns ns ns ns ns ns ns ns MHz

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

AC WAVEFORMS

74HC/HCT74

The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.6

Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.

handbook, full pagewidth

nCP INPUT

VM(1)

trem VM(1)

nSD INPUT

tW

trem

tW VM(1)

nRD INPUT

tPLH

tPHL

nQ OUTPUT

VM(1)

tPHL

tPLH

(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

nQ OUTPUT

VM(1)
MGL350

Fig.7

Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time.

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil)

74HC/HCT74

SOT27-1

D seating plane

ME

A2

A1

c Z e b1 b 14 8 MH w M (e 1)

pin 1 index E

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001AA EIAJ EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-03-11

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

74HC/HCT74

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

A X

c y HE v M A

Z 14 8

Q A2 A1 pin 1 index Lp 1 e bp 7 w M L detail X (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012

inches 0.069

0.010 0.057 0.004 0.049

0.019 0.0100 0.35 0.014 0.0075 0.34

0.244 0.039 0.041 0.228 0.016

8 0o

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06S JEDEC MS-012AB EIAJ EUROPEAN PROJECTION

ISSUE DATE 95-01-23 97-05-22

1998 Feb 23

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

74HC/HCT74

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

A X

c y HE v M A

Z 14 8

Q A2 pin 1 index Lp L 1 bp 7 w M detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 0o
o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150AB EIAJ EUROPEAN PROJECTION

ISSUE DATE 95-02-04 96-01-18

1998 Feb 23

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Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

74HC/HCT74

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

c y HE v M A

14

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

7
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
o

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04

1998 Feb 23

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Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. 1998 Feb 23 12

74HC/HCT74
Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.

Philips Semiconductors

Product specication

Dual D-type ip-op with set and reset; positive-edge trigger

DEFINITIONS Data sheet status Objective specication Preliminary specication Product specication Limiting values

74HC/HCT74

This data sheet contains target or goal specications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains nal product specications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specication. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1998 Feb 23

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