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Progess Report

VHDL is a hardware description language that can be used to model a digital system. The system can be as simple as a logic gate or as complex as a complete electronic system. To describe entity, VHDL provides five different types of constructs, called design units.

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Md Rizwan Ahmad
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21 views

Progess Report

VHDL is a hardware description language that can be used to model a digital system. The system can be as simple as a logic gate or as complex as a complete electronic system. To describe entity, VHDL provides five different types of constructs, called design units.

Uploaded by

Md Rizwan Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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WORK CONCLUDED

VHDL:VHDL is an acronym for very high-speed integrated circuit hardware description language. It is a general-purpose hardware description language that is specifically designed to describe the organization and function of digital hardware system, circuit boards & components at many level of abstraction ranging from simple gate to complete digital electronics systems. BASIC TERMONOLOGY:VHDL is a hardware description language that can be used to model a digital system. The system can be as simple as a logic gate or as complex as a complete electronic system .A hardware abstraction of this digital system is called an ENTITY. To describe entity, VHDL provides five different types of constructs, called design units, they are:1. Entity Declaration 2. Architecture declaration 3. Configuration declaration 4. Package declaration 5. Package body DESIGN DESCRIPTION METHODS-:
a. b. c. d. STRUCTURAL STYLE OF MODELLING DATA FLOW STYLE OF MODELLING BEHAVIORAL STYLE OF MODELLING MIXED STYLE OF MODELLING

MIXED STYLE OF MODELLING: It is possible to mix the three modeling style that we have shown so far in a signal architecture body. That is, within an architecture body, we could component instantiation statement (that represents structure). Concurrent signal assignment statement (that represent flow), and process statements (that represents behavior). Here is an example of a mixed style model for the 1-BIT FULL ADDER: Entity FULL ADDER is port ( A, B, CIN : in bit; SUM, CAROUT : out bit); generic (del :time = 10ns); end FULL ADDER; architecture FA MIXWD of FULL ADDER is component XOR2

port(P1,P2 : in bit :PZ : out bit); end component ; signal S 1: bit; begin x1 : XOR2 port map (A, B,S1): - -structure process (A,B,CIN) -- behavior variable T1, T2, T3:BIT ; begin T1 = A and B T2 : = B and CIN; T3 : = A and CIN ; CAROUT < = T1 or T2 OR T3 end process; SUM < = S1 xor CIN; end FA MIXED;

PROGRESS REPORT
OF

FINAL YEAR PROJECT


ON

DESIGN OF ALU OF THE 8086 MICROPROCESSOR USING VHDL.


ELECTRONICS & COMMUNICATION ENGINEERING (EC-1)
By

KUNDAN KUMAR (Roll no.-0800114038) MD RIZWAN AHMAD (Roll no.-0800114048) DENIS KUMAR (Roll no.-0800114025) ADIL MASOOD(Roll no.-0800114007)

Under the guidance of

Ms Tarana Afrin Chandel


(ASST. PROFESSOR)

DEPT. OF ELECTRONICS & COMMUNICATION ENGINEERING

INTEGRAL UNIVERSITY
KURSI ROAD, LUCKNOW (U.P.) (Odd Semester, session: 2011-2012)

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