Introduction to

CMOS VLSI
Design
Lecture 3:
CMOS Transistor Theory
David Harris
Harvey Mudd College
Spring 2004
3: CMOS Transistor Theory Slide 2 CMOS VLSI Design
Outline
q Introduction
q MOS Capacitor
q nMOS I-V Characteristics
q pMOS I-V Characteristics
q Gate and Diffusion Capacitance
q Pass Transistors
q RC Delay Models
3: CMOS Transistor Theory Slide 3 CMOS VLSI Design
Introduction
q So far, we have treated transistors as ideal switches
q An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
q Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
q Also explore what a degraded level really means
3: CMOS Transistor Theory Slide 4 CMOS VLSI Design
MOS Capacitor
q Gate and body form MOS capacitor
q Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
(b)
+
-
0 < V
g
< V
t
depletion region
(c)
+
-
V
g
> V
t
depletion region
inversion region
3: CMOS Transistor Theory Slide 5 CMOS VLSI Design
Terminal Voltages
q Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
q Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
0
q nMOS body is grounded. First assume source is 0 too.
q Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
3: CMOS Transistor Theory Slide 6 CMOS VLSI Design
nMOS Cutoff
q No channel
q I
ds
= 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
3: CMOS Transistor Theory Slide 7 CMOS VLSI Design
nMOS Linear
q Channel forms
q Current flows from d to s
e
-
from s to d
q I
ds
increases with V
ds
q Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
3: CMOS Transistor Theory Slide 8 CMOS VLSI Design
nMOS Saturation
q Channel pinches off
q I
ds
independent of V
ds
q We say current saturates
q Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
3: CMOS Transistor Theory Slide 9 CMOS VLSI Design
I-V Characteristics
q In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
3: CMOS Transistor Theory Slide 10 CMOS VLSI Design
Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
q Q
channel
=
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
3: CMOS Transistor Theory Slide 11 CMOS VLSI Design
Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
q Q
channel
= CV
q C =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
3: CMOS Transistor Theory Slide 12 CMOS VLSI Design
Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
q Q
channel
= CV
q C = C
g
=
ox
WL/t
ox
= C
ox
WL
q V =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
3: CMOS Transistor Theory Slide 13 CMOS VLSI Design
Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
q Q
channel
= CV
q C = C
g
=
ox
WL/t
ox
= C
ox
WL
q V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
3: CMOS Transistor Theory Slide 14 CMOS VLSI Design
Carrier velocity
q Charge is carried by e-
q Carrier velocity v proportional to lateral E-field
between source and drain
q v =
3: CMOS Transistor Theory Slide 15 CMOS VLSI Design
Carrier velocity
q Charge is carried by e-
q Carrier velocity v proportional to lateral E-field
between source and drain
q v = E called mobility
q E =
3: CMOS Transistor Theory Slide 16 CMOS VLSI Design
Carrier velocity
q Charge is carried by e-
q Carrier velocity v proportional to lateral E-field
between source and drain
q v = E called mobility
q E = V
ds
/L
q Time for carrier to cross channel:
t =
3: CMOS Transistor Theory Slide 17 CMOS VLSI Design
Carrier velocity
q Charge is carried by e-
q Carrier velocity v proportional to lateral E-field
between source and drain
q v = E called mobility
q E = V
ds
/L
q Time for carrier to cross channel:
t = L / v
3: CMOS Transistor Theory Slide 18 CMOS VLSI Design
nMOS Linear I-V
q Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I
3: CMOS Transistor Theory Slide 19 CMOS VLSI Design
nMOS Linear I-V
q Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ds
Q
I
t

3: CMOS Transistor Theory Slide 20 CMOS VLSI Design

_


,
_


,
ox
=
W
C
L

3: CMOS Transistor Theory Slide 21 CMOS VLSI Design
nMOS Saturation I-V
q If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
q Now drain voltage no longer increases current
ds
I
3: CMOS Transistor Theory Slide 22 CMOS VLSI Design
nMOS Saturation I-V
q If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
q Now drain voltage no longer increases current
2
dsat
ds gs t dsat
V
I V V V
_


,
3: CMOS Transistor Theory Slide 23 CMOS VLSI Design
nMOS Saturation I-V
q If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
q Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V

_


,

3: CMOS Transistor Theory Slide 24 CMOS VLSI Design
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

_
<
'
,

>

q Shockley 1
st
order transistor models
3: CMOS Transistor Theory Slide 25 CMOS VLSI Design
Example
q We will be using a 0.6 m process for your project
From AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
q Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L

_
_

,
,
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
3: CMOS Transistor Theory Slide 26 CMOS VLSI Design
pMOS I-V
q All dopings and voltages are inverted for pMOS
q Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V*s in AMI 0.6 m process
q Thus pMOS must be wider to provide same current
In this class, assume
n
/
p
= 2
*** plot I-V here
3: CMOS Transistor Theory Slide 27 CMOS VLSI Design
Capacitance
q Any two conductors separated by an insulator have
capacitance
q Gate to channel capacitor is very important
Creates channel charge necessary for operation
q Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
3: CMOS Transistor Theory Slide 28 CMOS VLSI Design
Gate Capacitance
q Approximate channel as connected to source
q C
gs
=
ox
WL/t
ox
= C
ox
WL = C
permicron
W
q C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9
0
)
polysilicon
gate
3: CMOS Transistor Theory Slide 29 CMOS VLSI Design
Diffusion Capacitance
q C
sb
, C
db
q Undesirable, called parasitic capacitance
q Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g
for contacted diff
C
g
for uncontacted
Varies with process
3: CMOS Transistor Theory Slide 30 CMOS VLSI Design
Pass Transistors
q We have assumed source is grounded
q What if source > 0?
e.g. pass transistor passing V
DD
V
DD
V
DD
3: CMOS Transistor Theory Slide 31 CMOS VLSI Design
Pass Transistors
q We have assumed source is grounded
q What if source > 0?
e.g. pass transistor passing V
DD
q V
g
= V
DD
If V
s
> V
DD
-V
t
, V
gs
< V
t
Hence transistor would turn itself off
q nMOS pass transistors pull no higher than V
DD
-V
tn
Called a degraded 1
Approach degraded value slowly (low I
ds
)
q pMOS pass transistors pull no lower than V
tp
V
DD
V
DD
3: CMOS Transistor Theory Slide 32 CMOS VLSI Design
Pass Transistor Ckts
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
3: CMOS Transistor Theory Slide 33 CMOS VLSI Design
Pass Transistor Ckts
V
DD
V
DD
V
s
= V
DD
-V
tn
V
SS
V
s
= |V
tp
|
V
DD
V
DD
-V
tn
V
DD
-V
tn
V
DD
-V
tn
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
-V
tn
V
DD
-2V
tn
3: CMOS Transistor Theory Slide 34 CMOS VLSI Design
Effective Resistance
q Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
q Simplification: treat transistor as resistor
Replace I
ds
(V
ds
, V
gs
) with effective resistance R
I
ds
= V
ds
/R
R averaged across switching of digital gate
q Too inaccurate to predict current at any given time
But good enough to predict RC delay
3: CMOS Transistor Theory Slide 35 CMOS VLSI Design
RC Delay Model
q Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
q Capacitance proportional to width
q Resistance inversely proportional to width
k g
s
d
g
s
d
kC
kC
kC
R/k
k g
s
d
g
s
d
kC
kC
kC
2R/k
3: CMOS Transistor Theory Slide 36 CMOS VLSI Design
RC Values
q Capacitance
C = C
g
= C
s
= C
d
= 2 fF/m of gate width
Values similar across many processes
q Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
q Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
3: CMOS Transistor Theory Slide 37 CMOS VLSI Design
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
2
1
A
Y
2
1
3: CMOS Transistor Theory Slide 38 CMOS VLSI Design
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
Y
2
1
3: CMOS Transistor Theory Slide 39 CMOS VLSI Design
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
3: CMOS Transistor Theory Slide 40 CMOS VLSI Design
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
d = 6RC