ASIC DESIGN FLOW
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
ASICS
What are ASICS?
Any IC other than a general purpose IC which contain the functionality of thousands of gates is usually called an ASIC(Application Specific Integrated Circuit). ASICs are designed to fit a certain application.
An ASIC is a digital or mixed-signal circuit designed to meet specifications set by a specific project.
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
ASIC Project
ASIC design team (Project leader, designers for different tasks) Information share with closely related projects/design teams (software, analog HW design, system design) - Documentation! ASIC project is a part of bigger project - Scheduling is important! Design flow must be defined and approved
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
ASIC Design Flow
SYSTEM REQUIREMENTS
SPECIFICATION
SPECIFICATION
LOGIC DESIGN
MODELLING
LOGIC DESIGN
SYNTHESIS
VERIFICATION
TEST GENERATION
PHYSICAL
SIGN-OFF / Mapping
MANUFAC / Place & Route
/ Configuration data
PROTOTYPE
SYSTEM TESTING PROTO VERIFICATION
SYSTEM TESTING
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
ASIC Specification
The goal is to specify the functional requirements for the design and define the external interfaces to the related designs.
SYSTEM REQUIREMENTS
SPECIFICATION System Req. Specification System Func. Specification ASIC Project Plan Tools Re qu i r e me n S t pe c i f i c a t i
e . g. W r d o
REQ. SPEC REVI EW Re qu i r e me n t Spe c i f i c at i Da t a Sp i Sh e c t f i c a t i
e . g. W d or
DATA SHEET REVI EW Da t a S he e t l 1
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
MODELLING
ASIC Modeling
The goal is to build a simulatable (behavioral) VHDL model corresponding to the specification. The function of the model is verified by using a VHDL test bench Architecture design Model validation ok -> Logic design
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Logic design
The goal is to write a synthezisable VHDL description of the design Design rules (Naming, vendor independence, Use only IEEE standard types, comments, ). Reusing Synchronous design !! Design partitioning (into RTL blocks)
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Naming rules
Use meaningful names for signals, ports, functions and parameters. For example, do not use ra for a RAM address bus. Instead, use ram_addr or RamAddr (capital letters can also be used). If your design uses several parameters, use short but descriptive names. Use the name clk for the clock signal. If there is more than one clock in the design, use clk as the prefix for all clock signals (for example clk4m, clk8m). Use the same name throughout the hierarchy for all clock signals that are driven from the same source. For active low signals, end the signal name with an underscore followed by a lowercase character x. Use the name reset for reset signals. For active low resets use the name reset_x. For multibit buses, use (y downto x) ordering of bits.
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Naming rules
Use the same name or similar names for ports and signals, throughout the hierarchy, that are connected. (for example, a => a; or a => a_int;) Use the name enab for an enable signal. If there is more than one enable in the design, use enab as the prefix for all enable signals. Testbench is named 'name_of_the_block'_TB.
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Guidelines for clocks and resets
The preferred clocking structure is a single global clock and positive edge-triggered flip-flops as the only sequential devices.
FF
FF
clk
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Guidelines for clocks and resets
Digital ASICs must be designed to be synchronous when possible. This must be considered, when VHDL for synthesis is written. The main benefits of synchronous design are:
Timing problems are avoided. Only the propagation of signals to the next register during one clock cycle must be verified. Most of the problems with hazards are avoided. The X-states and glitches in gated and multiplexed clocks are avoided. It is easier to test a synchronous circuit than an asynchronous one. Static timing analysis is possible.
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Guidelines for clocks and resets
partition the design so that all the logic in a single module uses a single clock and a single reset. Isolating clock and reset generation logic in a separate module allows the other modules to use the standard timing analysis and scan insertion techniques. It also makes it easier to develop specific test strategies for the clock/reset generation logic.
clk1 master clock clk2
submodule 1 submodule 2 submodule 3
Clock Generation
clk3
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Guidelines for clocks and resets
Avoid gated clocks Clock gating circuits tend to be technology specific and timing dependent. Improper timing of a gated clock can generate a false clock or glitch, causing a flip-flop to clock in the wrong data. Also, the skew of different local clocks can cause hold time violations. Gated clocks also cause limited testability because the logic clocked by a gated clock cannot be made part of a scan chain.
FF
FF
clk
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Guidelines for clocks and resets
If your design requires gated clocks, use preferably vendor provided gated flip-flop elements using master clock.
data enable master clock reset
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Guidelines for clocks and resets
Avoid internally generated resets Make sure your registers are controlled only by a single reset signal. Avoid internally generated, conditional resets if possible. Generally, all the registers in the macro should be reset at the same time. This approach makes analysis and design much simpler and easier. If conditional reset is required, create a separate signal for the reset signal, and isolate this in a separate module. This approach results in more readable code and improves synthesis results.
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Design partitioning
Good partitioning in the design provides several advantages including:
Easy handling of design requires sensible hierarchy Better synthesis results Faster synthesis compile runtimes Ability to use simpler synthesis strategies to meet timing Reusability
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Design partitioning
Locate related combinational logic in a single module and single process if possible The synthesis tool has more flexibility in optimising a design when related combinational logic is located in the same module. This is because synthesis tools cannot move logic across hierarchical boundaries during compile operation.
A B C
clk
FF A
COMB A
COMB B
COMB C
clk
FF C
Bad
clk
FF A
COMB A&B&C
clk
FF C
Better
clk
FF A
COMB A&B&C
clk
FF C
Best
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
RTL block design
P RTLi t i t Bl k
RTL Bl o c k D i
VHDL Sch.,DFD
Ar c hi t e c t u r e Pl hi i A a n/ De s c r i p t M d l
Te x t di
Target technology
Sy nt he s i z a b l e Bl oc k RTL D i
VHDL
RTL VHDL Syn t h e s i s Ch k
Tar ge t h da t a l b
VHDL TB
De s i g n C il
Schematics
S c h e mat i c i RTL Bl o c k F ti V ifi ti
simulation results
VHDL Te s t Be n c h M nt or e VSS Si l
S t i mu l R i e s po ns e
VHDL,DFD
RTL Doc k Bl ume n t a t i o Te x t di Bl o c k Re v i e w
Add e d c o mme n t s
RTL Block
Re l e a s e d RTL bl k
RTL M e l od I nt e g r a t i
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Synthesis
LOGIC DESIGN
SYNTHESIS
VHDL
RTL VHDL M ode l
e . g. Te x t di
Generic technology
Pr t h i S e pa r a t i
VHDL Sch.,DFD
RTL VHDL M ode l opt i mi z e d f or h i M dul e o Syn t he s i
Schematics
Ge n e r i c h dat a l b
De s i gn Compi l e r Te s t Comp i l e r Mp a Li b pi ng
Sc h e mat i c bas e d on ge ne r i c i h l
Schematics
Sc h e mat i c bas e d on t ar ge t i h l
Target technology
ASI C t e s t s yn t he s i s , t t bi l i t
Schematics
Tar ge t h dat a l b Opt l M d i mi z a t i
Sc h e mat i c add e d t e s t s t r u c t ur e i
Schematics
Sc h e mat i c opt i mi z e d i f or t ar ge t h l Ti mi ng A l i Ti mi ng R
VERIFICATION
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Gate level verification
CHIP VERIFICATION ASI C/ FPGA RTL d i i
Synthesis
Opt i mi z e d db
Static timing analysis Sy nops y s De s i gn or FPGA c e qui e r or ompi l v al e nt l Sy nt he s i s Li br ar
Qui c k c he c k Ti mi ng
Netlist creator
Ne t l i s
Formal verification and
ASI C/ FPGA gat e Li b Te s t be nc h, be h. mode l Aut omat i c / manua c l ons t r ai n Functional errors St i mul i Re d pons e s s Functional simulation
static timing analyses
M appi ng i nf or mat i
VHDL/ gat e l e v e l i l
Mapping (FPGA)
Floorplanning
Fl oor pl anni n i nf or mat i
ASI C/ FPGA v e ndor t d ool s i
Place&route (FPGA)
FPGA i mpl e me nt at i
ASI C/ FPGA Ce l l Li b
Static timing analysis Ti mi ng
Te s t be nc h, be h. mode l
St i mul i Re d pons e s s
Timing simulation Dat a She e t d
VHDL/ gat e l e v e l l t i
Timing errors
TO TEST GENERATION
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Test generation
CHIP VERIFICATION
Chip gate level schematic with test structures
TEST GENERATION Pr e l i m. t e s t pa t t e r n ti
Test Patterns
(ASIC only)
ASCI I Pr e l i mi na r y
M nu a l t e s t a pa t t e r n ti
Test Pattern
ASCI I M ua l : RAM . . an
Test Compiler Plus
Au t o ma t i c p t at t er n i
Test Pattern
ASCI I Aut omat i c
Test pattern responses
Te s t Si mull a t i o n ti
ASCI I Te s t da t a : s t i mu l i +
VeriFault
Fa u l t G di Ve r i f i e d Ch i p h i
Layout
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Layout and sign off
TEST GENERATI ON
Lay o ut
Schema Netlist
De s i gn , t e s t d a t a
(ASIC)
Pr e l a yo ut i l ti
simulation results
Ve n d or s De s i gn Ki
S t i mul R i e s p on s e
Pl a c e & Rou t e
Target technology Design
GDS I I
Tar ge t h dat a l b Po s t l a y ou t i l ti
simulation results
S t i mul R i e s p on s e
Ba c k a nn ot a t e t o S St a t i c Ti mi ng A l i
Back annotation
Ti mi ng f i l e t o d i
De s i gn DRC, i LVS i if t Ve n d or l fil
Re p o r t fil
Si g n o f f M u f a c t . a g r e e me nt an
M ANUFACTURI NG PROTO TESTI NG
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
Prototype testing
Final verification is done with E/S (engineering samples). Physical measurements:
Parametric DC tests Parametric AC tests Functional tests Power consumption Thermal tests
Release to system tests Final documentation and project completion Chips manufacturing
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
FPGA prototyping
FPGA, Field Programmable Gate Array VHDL coding for FPGAs (design partitioning, limited maximum clock speed, limited amount of interfaces) Building prototyping board Prototyping in laboratory environment
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
FPGA prototyping
Advantages:
VHDL is tested with real clock speed, in real environment Prototyping environment offers "early ASIC" for other projects More secure to sign off
Disadvantages
Requires a lot of time and resources Expensive
TKK Laitteistokuvauskielinen digitaalisuunnitelu Syksy-1999
MPl 5.10.1999
