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SCH Cpu

This circuit diagram shows a microcontroller development board with a PIC16F877 microcontroller. It includes components for power regulation and reset, an oscillator, serial communication, and input/output including a parallel port. The microcontroller is connected to buffers, decoders, and other logic chips to interface with an LCD module and expand its I/O capabilities.

Uploaded by

Williams Giorgio Sicsu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
120 views

SCH Cpu

This circuit diagram shows a microcontroller development board with a PIC16F877 microcontroller. It includes components for power regulation and reset, an oscillator, serial communication, and input/output including a parallel port. The microcontroller is connected to buffers, decoders, and other logic chips to interface with an LCD module and expand its I/O capabilities.

Uploaded by

Williams Giorgio Sicsu
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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1

10

5Vcc
5Vcc
R1
10K

Q2
BC548

R2
4K7
U1A
7407

D5 LPT
5-VPP-6

13Vcc

R4
4K7

R3
10K

Q1
BC557

D1
1N4148

R5
2K7

R6

C1
10uF

/Q-PROG
2K7

SW1
Reset uProc

D2
1N4148

D3
1N4148

5Vcc
5Vcc

CLK
Q

RB6-I6
RB7-I7

/Q-PROG

13
14

R7
2K7

MCLR/VPP

OSC1/CLKIN
OSC2/CLKOUT
MCLR/VPP
GND
GND

C
22pF
Y1
20MHZ
C8

8
9
10

RD0-S0
RD1-S1
RD2-S2
RD3-S3
RD4-S4
RD5-S5
RD6-S6
RD7-S7

16

RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7

RX

TX

11
10

T1IN
T2IN

RX

12
9

R1OUT
R2OUT

1
10uF
C3
10uF

T1OUT
T2OUT

14
7

R1IN
R2IN

13
8

VCC

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

19
20
21
22
27
28
29
30

LCD CLK
OUTPUT CLK

1
6
2
7
3
8
4
9
5

C2
C1+

3
4

C1C2+

C2-

C6
MAX232

V+

V-

P1
10uF
C4
10uF

12
31

C7

11
32

RBO/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7

TX

U3

33
34
35
36
37
38
39
40

RB0-I0.0
RB1-I0.1
RB2-I0.2
RB3-I0.3
RB4-I0.4
RB5-I0.5

Q-RUN

U4A
4013
3

C5
1uF x 25V

CONNECTOR DB9

AD/PWM2
AD/PWM1

GND

SW2
Prog/Run

15
16
17
18
23
24
25
26

15

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

5Vcc

RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/TOCKI
RA5/AN4/SS

2
3
4
5
6
7

RA0-AN0
RA1-AN1
RA2-AN2
RA3-AN3

VDD
VDD

U2
PIC16F877

22pF

Q-RUN

/Q-PROG
5Vcc
5Vcc

IN Buffer
LPT
2-DAT-8

R9
4K7

U1B
7407

U5A

R8
4K7

U5B
U1C
7407
6

5Vcc

Out RB7
Out RB6

5Vcc
74LS126

R10
10K

74LS126

U1D
7407

13

10

IN Buffer
LPT
3-CLK-7

R11
4K7

U5C

12

U1E
7407
11

11

74LS126

74LS126
R14
4K7
U1F
7407
12

IN Buffer LPT

10

R13
10K

5Vcc

R12
4K7

U5D

E
13
Size

CAGE Code

A3
Monday, February 20, 2006

<Cage Code>

R ev

DWG NO
<Doc>

Scale

<RevCode>
Sheet
4

of

10

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