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Stick Diagram Basics

The document discusses CMOS mask layouts and design rules. It provides examples of nMOS and CMOS inverter mask layouts as well as higher level logic gates. The layers used in mask layouts are color coded. Design rules like lambda determine minimum feature sizes. Translating between mask layouts and logic diagrams involves simplifying the layout and drawing nMOS and pMOS stick diagrams to determine the circuit.

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sanju012
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© Attribution Non-Commercial (BY-NC)
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880 views

Stick Diagram Basics

The document discusses CMOS mask layouts and design rules. It provides examples of nMOS and CMOS inverter mask layouts as well as higher level logic gates. The layers used in mask layouts are color coded. Design rules like lambda determine minimum feature sizes. Translating between mask layouts and logic diagrams involves simplifying the layout and drawing nMOS and pMOS stick diagrams to determine the circuit.

Uploaded by

sanju012
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 26

11-1

Mask Layout (Print this presentation in colour if possible, otherwise highlight colours)

Circuit coloured mask layer layout


Coloured stick diagram mask representation Lambda and layout design rules Mask layout of nMOS and CMOS inverters Mask layout of CMOS circuits (examples) Reading & understanding mask layout (exercises)

CMOS Mask layout & Stick Diagram Mask Notation

11-2

nMOS transistor mask representation gate drain


polysilicon

source

metal

Contact holes diffusion (active region)

CMOS Mask layout & Stick Diagram Mask Notation

11-3

Mask layout & coloured stick diagram notation


Silicon layers are typically colour coded as follows :

diffusion (device well, local interconnect) polysilicon (gate electrode, interconnect) metal (contact, interconnect) contact windows depletion implant P well (CMOS devices)
This colour representation is used during mask layer definition Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward Several examples follow :

CMOS Mask layout & Stick Diagram Mask Notation

11-4

Layer contact mask layout representation


A transistor is formed when device well is crossed by polysilicon. Device well oxide : thin gate oxide
Metal contacting polysilicon
diffusion polysilicon metal contact windows depletion implant P well

Metal contacting diffusion

Metal crossing polysilicon (no contact, electrically isolated with thick oxide and so can carry separate voltages) Metal contacting diffusion (no contact, electricall isolated with thick oxide)
CMOS Mask layout & Stick Diagram Mask Notation

11-5

Transistor mask layout representation


A transistor is formed when device well is crossed by polysilicon. Device well oxide : thin gate oxide Enhancement mode transistor (Vth 0.2Vdd )

Depletion mode transistor (extra well implant to provide Vth -0.6Vdd )


diffusion polysilicon metal contact windows depletion implant P well

CMOS Mask layout & Stick Diagram Mask Notation

11-6

CMOS Inverter Mask Layout (using Microwind)

diffusion polysilicon metal contact windows depletion implant P well

Use file>colors>white background


CMOS Mask layout & Stick Diagram Mask Notation

11-7

CMOS Inverter Mask Layout

diffusion polysilicon metal contact windows depletion implant P well

CMOS Mask layout & Stick Diagram Mask Notation

11-8

CMOS AN2 (2 i/p AND gate) Mask Layout

diffusion polysilicon metal contact windows depletion implant P well

CMOS Mask layout & Stick Diagram Mask Notation

11-9

Layout Design rules & Lambda ()


Lambda () : distance by which a geometrical feature or any one layer may stay from any other geometrical feature on the same layer or any other layer. All processing factors are included plus a safety margin. used to prevent IC manufacturing problems due to mask misalignment or exposure & development variations on every feature, which otherwise could lead to : over-diffusion over-etching inadvertent transistor creation etc is the minimum dimension which can be accurately re-produced on the silicon wafer for a particular technology.

CMOS Mask layout & Stick Diagram Mask Notation

11-10

Layout Design rules & Lambda ()


Minimum photolithographic dimension (width, not separation) is 2. Hence, the minimum channel length dimension is 2. Where a 0.25m gate length is quoted, is 0.125 microns (m). Minimum distance rules between device layers, e.g., polysilicon metal metal metal diffusion diffusion and minimum layer overlaps are used during layout Layout design rule checker (DRC) automatically verifies that no design rules have been broken

Note however, the use of Lambda is not optimal but supports design reuse

CMOS Mask layout & Stick Diagram Mask Notation

11-11

Layout Design rules & Lambda ()


Lambda based design: half of technology since 1985. As technology changes with smaller dimensions, a simple change in the value of can be used to produce a new mask set.

4 6

6
Hcmos6 technology : =0.2m Hcmos8 technology : =0.1m

All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2. Minimum metal to metal spacing = 3
CMOS Mask layout & Stick Diagram Mask Notation

11-12

Basic design rules

2mA Minimize spared diffusion Use minimum poly width (2)

1 contact = 1mA Multiply contacts

CMOS Mask layout & Stick Diagram Mask Notation

11-13

Basic design rules

Width of pMOS should be twice the width of nMOS

Same N and P alters symmetry

L min Wpmos=2 Wnmos

CMOS Mask layout & Stick Diagram Mask Notation

11-14

nMOS transistor mask representation (See stick diagram next slide) for comparison

gate drain

polysilicon

source

metal

Contact holes diffusion (active region)

CMOS Mask layout & Stick Diagram Mask Notation

11-15

nMOS transistor coloured stick diagram representation


polysilicon

metal

Contact holes
diffusion polysilicon metal contact windows depletion implant P well

diffusion (active region)

CMOS Mask layout & Stick Diagram Mask Notation

11-16

For reference : an nMOS Inverter coloured stick diagram


diffusion polysilicon metal contact windows depletion implant P well

* Note the depletion mode device

Vdd = 5V

Vgspu= 0 (always) Vin

Tpu Vthpu -3V Vout

(Tpu always on since Vgs=0)

Tpd Vthpd +1V (enhancement mode device, off at 0V)

CMOS Mask layout & Stick Diagram Mask Notation

11-17

CMOS Inverter Mask Layout

CMOS Mask layout & Stick Diagram Mask Notation

11-18

CMOS Inverter Mask Layout

Simplify by deleting connections provided for interconnecting cell (additional pads and output metal rails)

CMOS Mask layout & Stick Diagram Mask Notation

11-19

CMOS Inverter coloured stick diagram

diffusion polysilicon metal contact windows depletion implant P well

CMOS Mask layout & Stick Diagram Mask Notation

11-20

Stick diagram -> CMOS transistor circuit

Vdd = 5V pMOS Vin nMOS Vout Vin

Vdd = 5V

Vout

In practice, first draw stick diagram for nMOS section and analyse (pMOS is dual of nMOS section)
CMOS Mask layout & Stick Diagram Mask Notation

11-21

Static CMOS NAND gate

CMOS Mask layout & Stick Diagram Mask Notation

11-22

Static CMOS NOR gate

CMOS Mask layout & Stick Diagram Mask Notation

11-23

Static CMOS Design Example Layout

CMOS Mask layout & Stick Diagram Mask Notation

11-24

Layout 2 (Different layout style to previous but same function being implemented)

CMOS Mask layout & Stick Diagram Mask Notation

11-25

Steps in translating from layout to logic circuit


1. Try to simplify mask layout diagram by removal of extended metal and polysilicon lines 2. First draw coloured stick diagram for nMOS section and analyse All nMOS transistor nodes which connect to GND terminal are SOURCE nodes

3. Since the pMOS section is the dual of the nMOS section, draw the pMOS stick diagram and confirm the outcome of step 2. All pMOS transistor nodes which connect to Vdd terminal are pMOS SOURCE nodes

CMOS Mask layout & Stick Diagram Mask Notation

Exercise : Draw coloured stick diagram and logic circuit for this CMOS mask layout

11-26

CMOS Mask layout & Stick Diagram Mask Notation

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