/----------------------------------------------------2 // Design Name : syn_fifo 3 // File Name : syn_fifo.

v 4 // Function : Synchronous (single clock) FIFO 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------7 module syn_fifo ( 8 clk , // Clock input 9 rst , // Active high reset 10 wr_cs , // Write chip select 11 rd_cs , // Read chipe select 12 data_in , // Data input 13 rd_en , // Read enable 14 wr_en , // Write Enable 15 data_out , // Data Output 16 empty , // FIFO empty 17 full // FIFO full 18 ); 19 20 // FIFO constants 21 parameter DATA_WIDTH = 8; 22 parameter ADDR_WIDTH = 8; 23 parameter RAM_DEPTH = (1 << ADDR_WIDTH); 24 // Port Declarations 25 input clk ; 26 input rst ; 27 input wr_cs ; 28 input rd_cs ; 29 input rd_en ; 30 input wr_en ; 31 input [DATA_WIDTH-1:0] data_in ; 32 output full ; 33 output empty ; 34 output [DATA_WIDTH-1:0] data_out ; 35 36 //-----------Internal variables------------------37 reg [ADDR_WIDTH-1:0] wr_pointer; 38 reg [ADDR_WIDTH-1:0] rd_pointer; 39 reg [ADDR_WIDTH :0] status_cnt; 40 reg [DATA_WIDTH-1:0] data_out ; 41 wire [DATA_WIDTH-1:0] data_ram ; 42 43 //-----------Variable assignments--------------44 assign full = (status_cnt == (RAM_DEPTH-1)); 45 assign empty = (status_cnt == 0); 46 47 //-----------Code Start--------------------------48 always @ (posedge clk or posedge rst) 49 begin : WRITE_POINTER 50 if (rst) begin 51 wr_pointer <= 0; 52 end else if (wr_cs && wr_en ) begin 53 wr_pointer <= wr_pointer + 1; 54 end 55 end 56 57 always @ (posedge clk or posedge rst) 58 begin : READ_POINTER 59 if (rst) begin 60 rd_pointer <= 0;

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103

end else if (rd_cs && rd_en ) begin rd_pointer <= rd_pointer + 1; end end always @ (posedge clk or posedge rst) begin : READ_DATA if (rst) begin data_out <= 0; end else if (rd_cs && rd_en ) begin data_out <= data_ram; end end always @ (posedge clk or posedge rst) begin : STATUS_COUNTER if (rst) begin status_cnt <= 0; // Read but no write. end else if ((rd_cs && rd_en) && ! (wr_cs && wr_en) && (status_cnt ! = 0)) begin status_cnt <= status_cnt - 1; // Write but no read. end else if ((wr_cs && wr_en) && ! (rd_cs && rd_en) && (status_cnt ! = RAM_DEPTH)) begin status_cnt <= status_cnt + 1; end end ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM ( .address_0 (wr_pointer) , // address_0 input .data_0 (data_in) , // data_0 bi-directional .cs_0 (wr_cs) , // chip select .we_0 (wr_en) , // write enable .oe_0 (1'b0) , // output enable .address_1 (rd_pointer) , // address_q input .data_1 (data_ram) , // data_1 bi-directional .cs_1 (rd_cs) , // chip select .we_1 (1'b0) , // Read enable .oe_1 (rd_en) // output enable ); endmodule

timescale 1ns/1ps 13 14 module aFifo 15 #(parameter DATA_WIDTH = 8, 16 ADDRESS_WIDTH = 4, 17 FIFO_DEPTH = (1 << ADDRESS_WIDTH)) 18 //Reading port 19 (output reg [DATA_WIDTH-1:0] Data_out, 20 output reg Empty_out,

21 input wire ReadEn_in, 22 input wire RClk, 23 //Writing port. 24 input wire [DATA_WIDTH-1:0] Data_in, 25 output reg Full_out, 26 input wire WriteEn_in, 27 input wire WClk, 28 29 input wire Clear_in); 30 31 // 32 reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0]; 33 wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead; 34 wire EqualAddresses; 35 wire NextWriteAddressEn, NextReadAddress En; 36 wire Set_Status, Rst_Status; 37 reg Status; 38 wire PresetFull, PresetEmpty; 39 40 // 41 //Data ports logic: 42 //(Uses a dual-port RAM). 43 //'Data_out' logic: 44 always @ (posedge RClk) 45 if (ReadEn_in & ! Empty_out) 46 Data_out <= Mem[pNextWordToRead]; 47 48 //'Data_in' logic: 49 always @ (posedge WClk) 50 if (WriteEn_in & ! Full_out) 51 Mem[pNextWordToWrite] <= Data_in; 52 53 //Fifo addresses support logic: 54 //'Next Addresses' enable logic: 55 assign NextWriteAddressEn = WriteEn_in & ~Full_out; 56 assign NextReadAddressEn = ReadEn_in & ~Empty_out; 57 58 //Addreses (Gray counters) logic: 59 GrayCounter GrayCounter_pWr 60 (.GrayCount_out(pNextWordToWrite), 61 62 .Enable_in(NextWriteAddressEn), 63 .Clear_in(Clear_in), 64 65 .Clk(WClk) 66 ); 67 68 GrayCounter GrayCounter_pRd 69 (.GrayCount_out(pNextWordToRead), 70 .Enable_in(NextReadAddressEn), 71 .Clear_in(Clear_in), 72 .Clk(RClk) 73 ); 74 75 76 //'EqualAddresses' logic: 77 assign EqualAddresses = (pNextWordToWrite == pNextWordToRead); 78 79 //'Quadrant selectors' logic: 80 assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRe ad[ADDRESS_WIDTH-1]) & 81 (pNextWordToWrite[ADDRESS_W

IDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]); 82 83 assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRe ad[ADDRESS_WIDTH-1]) & 84 (pNextWordToWrite[ADDRESS_W IDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]); 85 86 //'Status' latch logic: 87 always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous C lear & Preset. 88 if (Rst_Status Clear_in) 89 Status = 0; //Going 'Empty'. 90 else if (Set_Status) 91 Status = 1; //Going 'Full'. 92 93 //'Full_out' logic for the writing port: 94 assign PresetFull = Status & EqualAddresses; //'Full' Fifo. 95 96 always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchrono us Preset. 97 if (PresetFull) 98 Full_out <= 1; 99 else 100 Full_out <= 0; 101 102 //'Empty_out' logic for the reading port: 103 assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo. 104 105 always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchro nous Preset. 106 if (PresetEmpty) 107 Empty_out <= 1; 108 else 109 Empty_out <= 0; 110 111 endmodule You could download file aFifo.v here

1 //========================================== 2 // Function : Code Gray counter. 3 // Coder : Alex Claros F. 4 // Date : 15/May/2005. 5 //======================================= 6 7 `timescale 1ns/1ps 8 9 module GrayCounter 10 #(parameter COUNTER_WIDTH = 4) 11 12 (output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output. 13 14 input wire Enable_in, //Count enable. 15 input wire Clear_in, //Count reset. 16

17 input wire Clk); 18 19 // 20 reg [COUNTER_WIDTH-1:0] BinaryCount; 21 22 // 23 24 always @ (posedge Clk) 25 if (Clear_in) begin 26 BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begin s @ '1' with 27 GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_i n'. 28 end 29 else if (Enable_in) begin 30 BinaryCount <= BinaryCount + 1; 31 GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1], 32 BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[C OUNTER_WIDTH-1:1]}; 33 end 34 35 endmodule