aSic p r o T o T yp i n g S i m p li fi e d

Technical paper
contents
introduction ....................... 1 design flow for aSic prototyping with fpgas ...... 2 design flow with allegro fpga System planner ......... 3 design requirements .......... 5 designing with allegro fpga System planner ......... 6 conclusion ....................... 11

IntroductIon
With the cost of aSic design being what it is, you can hardly afford to have any mistakes in your aSic/aSSp. The need for good verification is hence paramount. hardware-based verification platforms have been used ever since the advent of aSic design. more recently, fpga-based systems have started to address this need. however, off-the-shelf fpga-based systems are not ideal for a variety of reasons: 1. cost. if you require one prototype board with a limited number of fpgas, you may be able to justify the cost. however, in a real project, you always require multiple systems for different groups to use. The cost of off-the-shelf fpga boards becomes prohibitively high 2. feasibility. you would like to prototype your entire Soc, or at least prototype the newer/critical portions of it. Such a prototype is difficult to create using off-the-shelf boards. mapping your design into off-the-shelf boards can be quite a challenge, especially if your design has wide busses. mapping a complex design onto off-the-shelf boards can reduce the frequency of operation significantly 3. performance. you would like to prototype your system and test it out at or near the required frequency of operation. With off-the-shelf boards, your frequency is limited off-the-shelf boards provide an expensive, partial solution that doesnt enable you to prototype your design and test it fully. growing Soc complexity, an increasing amount of embedded software, and the high cost of emulation systems have driven the need for custom prototyping. however, there is significant complexity of designing boards with multiple fpgas. cadence allegro fpga System planner was designed to overcome the challenges with multifpga board design. it is designed to be used in combination with commercial tools available for rTl partitioning, fpga design, and board design. allegro fpga System planner has been used in

several aSic prototyping designs successfully. it has been found to double or triple the productivity and cut the overall schedule in half. in this application note, we will walk you through a complete fpga board for aSic prototyping.

desIgn Flow For AsIc PrototyPIng wIth FPgAs

figure 1 shows a typical flow for prototyping aSics using fpgas.

Estimate the number of FPGAs required

Define a high-level board architecture with FPGAs

Define FPGA connectivity and select I/Os for FPGAs manually

Analyze results and modify board architecture

Partition ASIC RTL using the board

Figure 1: Typical design flow for ASIC protoyping using FPGAs

The process starts by identifying the number of fpgas required for prototyping. This can be done in several ways: 1. Start with an estimate of the fpgas. This can be a rough estimate, for example, based on the number of functional blocks that you are integrating to create the Soc. it may be a good idea to separate each functional block into an fpga or a set of fpgas 2. alternately, you can use a synthesis tool to synthesize the aSic rTl to calculate the equivalent fpga resources required once you identify the fpgas required, you will need to estimate the number of connections that are required between the different fpgas. again, if you use the approach of prototyping each functional block of your Soc in an fpga, the connections between different functional blocks will be the connections between the fpgas on the board. you will then need to create a board Verilog netlist defining all the fpgas and the connections between the different fpgas. Using all of this information, you can start the process of aSic partitioning into fpgas. To partition the aSic/Soc rTl, you will need to use a synthesis tool. of course, you can partition the rTl manually as well. you may need to add or delete fpgas and connections between fpgas to enable satisfactory partitioning.

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The key difficulty in the process described above is in creating the multi-fpga pcB, and iterating between the board architecture and rTl partitioning tool to design a board that works for your aSic/Soc.

desIgn Flow wIth Allegro FPgA system PlAnner

allegro fpga System planner enables you to simplify this whole process of multi-fpga board design significantly. figure 2 shows a flow for aSic partitioning using fpga System planner.

Estimate the number of FPGAs required

Increase/Decrease the number of FPGAs

Place the FPGAs on 7Circuits canvas

Use the board Verilog file and partition the RTL

Read the port list into 7Circuits to synthesize the I/Os for the FPGAs

Modify port list

All I/Os placed?

Done

Figure 2: ASIC partitioning flow using FPGA System Planner

allegro fpga System planner automates several steps in the process. Below is the process that you can use for aSic prototyping with fpga System planner in the flow: 1. estimate the fpgas required for partitioning your rTl. While estimating the number of fpgas, keep the following factors in mind: The aSic gate count that you want to implement in the prototype, translated into equivalent fpga lUTs. a rough estimate of the fpga lUTs required for implementing aSic gates is as follows: i. 4 input lUT = 10 aSic gates ii. 6 input lUT = 15 aSic gates memory requirement. Separate out the required memory into fpga internal memory vs. external memory. also, separate the requirement into external and internal Sram, Sdram, and flash identify the resources that can be implemented in fpga hard ip, such as dSp blocks. note that while functions such as dSps can be implemented using lUTs, it can become very expensive with the number of lUTs required

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 if you are using processors, such as an arm processor, in the design, you may want to consider an off-the-shelf part that can implement this function, and integrate that with the fpgas ensure you have sufficient i/os for interconnecting the fpgas. The fpga i/os or board traces connecting these i/os represent the wires in the top level of your partitioned rTl 2. next, place the fpgas on the allegro fpga System planner canvas, which will allow you to make some architectural tradeoffs. generate a top-level Verilog board file with the fpgas. you can now drive the partitioning tools: roughly figure out the size of the board you will require identify a placement that will make sense for the board 3. now, use an aSic partitioning tool to ensure that the rTl can be partitioned within the selected number of fpgas. Some factors to consider here: its a good idea to keep your fpga utilization low, say in the range of 50-70%. you may want to keep it lower if you expect your rTl functionality to grow if you plan to use on-chip debug tools, such as Xilinx chipScope or altera SignalTap, remember to reduce your Sram and logic utilization correspondingly another reason to keep the utilization low is to use your fpga board for the next generation of your product 4. next, use the top level of the partitioned rTl to define the connections required among the different fpgas 5. allegro fpga System planner can now synthesize the design to translate the nets in the toplevel rTl and create i/os for the fpgas while considering all the aspects for the design: The physical placement of fpgas on the board The fpga i/o drc requirements The logical requirement for the busses between the fgpas 6. once you complete the i/o synthesis in allegro fpga System planner, you can generate the Verilog board connectivity file. you may need to iterate with the i/o definitions to ensure that all the i/os can be placed on the different fpgas 7. Use this connectivity file once again in the rTl partitioning tool. The rTl partitioning tool can now map the wires in the top level to ports/traces on the board 8. in some cases, it may be required to iterate a bit to get to successful results. analyze results of the partitioning tools and make the required changes to the fpga board architecture. you may also want to increase the bus widths to increase the available connectivity 9. iterate between the steps defined in (2) through (8) to ensure you design a board that can be fully utilized for your prototyping requirement 10. once you have a board partition that meets the requirements, you can proceed to the next steps in board design. allegro fpga System planner enables you to quickly: create all the required power supply connections automatically. This is done in a few mouse clicks, and it ensures that your design is going to have correct power supplies connected generate all the configuration connections required for the fpgas to be programmed automatically generate schematics for the most popular board design tools add the required decoupling capacitors and terminations Take your design into layout. (allegro fpga System planner can read back the layout files from allegro pcB tools to re-optimize any nets to make the layout easier) in the next few sections, we will go through a real prototype design example using allegro fpga System planner.

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desIgn requIrements
consider an Soc designed for a next-generation mobile phone. Typical functional blocks for such an Soc are shown in figure 3.

DRAM

Audio SpeechQuality Processor

RF & ADC/DAC

Baseband Modem

Memory Interface Processor

Central Processor

Storage Processor

WiFi/Lan Processor

Multi-media Processor

Miscellaneous I/O Processor

Figure 3: Functional blocks of a mobile phone SoC

for the sake of simplicity, we will illustrate a design with the baseband processor and the central processor. let us assume that you have determined the following requirements for each of the functional blocks: 1. control plane busses a 32-bit bus between the central processing unit and all the other blocks 2. Baseband modem Six of the largest available fpgas connections among the fpgas should be the maximum possible, since it is hard to determine how the partitioning is going to work. you would like the board to have the maximum possible connections, so that the partitioning tools can easily do the partitioning an 8-bit data bus and a small control bus between the baseband modem functional block and the audio processor a connector to interface between rf and baseband 3. central processor assume four large fpgas again, the maximum possible connections among the four fpgas control plane bus to all the other functional blocks

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desIgnIng wIth Allegro FPgA system PlAnner

now, lets map the high-level design architecture we described in the previous section into fpgas. The steps are as follows: 1. open allegro fpga System planner and place your favorite large fpgas on the canvas 2. place the fpgas on the board and create a Verilog file with the fpga definitions. you would use this file in the partitioning tool 3. after partitioning and identifying the busses required among different fpgas, define them concisely in allegro fpga System planner 4. run the allegro fpga System planner i/o synthesis engine to generate connectivity 5. output the board Verilog file, individual fpga Verilog files, and constraint files 6. Verify that design requirements are met by using this Verilog file in the partitioning tool 7. modify the design to meet the partitioning requirements

Allegro FPgA system PlAnner

allegro fpga System planner is a tool designed to simplify multi-fpga board design. it generates outputs that enable you to iterate with your partitioning tool.

IdentIFyIng And PlAcIng the FPgAs on the boArd

allegro fpga System planner has a pre-defined library of all the popular fpgas that are typically used for prototyping, including Xilinx and altera fpgas. a screenshot of allegro fpga System planner with the six fpgas for baseband and four fpgas for the cpU is shown in figure 4. Below is the key design criteria we used:

Figure 4: Allegro FPGA System Planner with 10 FPGAs placed on the board

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1. create a 12x12 board in allegro fpga System planner 2. place 10 of the largest Xilinx Virtex-5 fpgas on the board 5VlX330ff1760 devices, 6 for the baseband modem and 4 for the central processor create the modem function with the fpgas labeled U1 to U6 create the central processor function with fpgas labeled U7 to U10 3. add the following connectors to enable input/output to the system a Z-doK+ connector labeled as U11 Two fmc connectors labeled as U12 and U13 (these will enable you to cascade with other fpga boards or functional modules such as rf/dac/adc) a memory part, ddr2 Sodimm connector, Xp32

deFInIng the connectIons between FPgAs

as previously mentioned, we want to maximize the connections between groups of fpgas intended for each function. We also want to create a bus between the central processing function and the rest of the fpgas. allegro fpga System planner enables you to define the connections at a high level. for example, you only need to define the different types of busses and the different fpgas with which they communicate. a protocol (a built-in feature of allegro fpga System planner) is used to create busses. a protocol can be used to create point-to-point busses or point-to-multi-point busses. an example is shown in figure 5. in this example, we have created a 512-bit bus between the six fpgas forming the modem function. We also create two additional busses: one between U1, U2, and U3, and the other between the other three fpgas. These busses are 256 bits wide. We then create a small control bus (32-bit, lVdS) between all the six fpgas. lets also define a 32-bit bus between the Z-doK connector and U1. note that the generic data busses are defined with the i/o standard lVcmoS12.

Figure 5: Defining a bus between different FPGAs forming the modem function

a screenshot of the high-level architecture defined so far is shown in figure 6. This abstract view can be used to define the architecture.

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Figure 6: Abstract view of the FPGAs with the different busses defined so far

runnIng synthesIs
Since allegro fpga System planner understands all the fpga i/o drc rules, it is able to synthesize the i/o connections based on the high-level definitions. While running synthesis, allegro fpga System planner will consider the logical rule definitions, the physical placement of the fpgas on the board, and all of the fpga i/o drcs. allegro fpga System planner has several synthesis algorithms to help you get the outputs most desirable for your requirements. it is important to consider all of the required factors to pin out the fpgas correctly: 1. logical rules. in simple words, following these rules enable the logic to function correctly. an example of a logical rule is as follows: the relationship between clock and data lines in a sourcesynchronous bus as applied to the fpga requirement. in a Xilinx Virtex-5 architecture, you will require that the clock line goes to a pin of type cc or clock capable pin. The corresponding data pins should go to pins within the same clock region in the Virtex-5 architecture 2. physical rules. These are rules to enable better board design. physical rules are derived automatically by allegro fpga System planner based on the layout of the different fpgas on the allegro canvas. With this understanding, allegro fpga System planner picks pins that simplify the layout rats-nest 3. fpga i/o drcs. These are rules that the fpga vendors dictate. allegro fpga System planner fully understands these rules for all of the key fpga architectures after synthesis, allegro fpga System planner displays the rats-nest of the connections (see figure 7).

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Figure 7: Rats-nest after synthesizing protocols between the modem FPGAs

allegro fpga System planner also generates a detailed report with the i/o utilization. This report can be used to increase or decrease the different bus widths. reports can be generated for each fpga or for the entire design (see figure 8).

Figure 8: A report of the design so far

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generAtIng outPuts For rtl PArtItIonIng tools

one key output that the rTl partitioning tools require is the board Verilog file. This file is directly generated by allegro fpga System planner. you can use this file in the partitioning tool to map the wires into fpga ports (and board traces).

VerIFyIng the PArtItIonIng requIrements And IterAtIng oVer the boArd ArchItecture
you can now use the Verilog board file created in allegro fpga System planner as the input to your fpga partitioning tool. Use the aSic/Soc rTl to run through the partitioning tool along with the board Verilog. Based on this, identify if the board that was just designed will be able to satisfy your requirements. you can easily modify the number of busses between the different fpgas, the width of the busses, or anything else to satisfy the rTl partitioning requirements. you can iterate between allegro fpga System planner and rTl partitioning tools until you are satisfied with a good balance of board and partitioned rTl. once you are satisfied with all aspects of the board architecture, you can also verify the fpga drcs with fpga tools such as Xilinx iSe pinahead and altera Quartus. allegro fpga System planner provides a direct interface to verify fpga pin outs with either Xilinx or altera tools.

comPletIng the boArd desIgn

once you are satisfied with the board architecture, allegro fpga System planner can be used to complete the rest of your design: 1. connect the configuration interfaces to configure the fpgas automatically 2. connect the fpga power pins to appropriate voltage rails automatically 3. generate schematics for popular schematic entry tools automatically 4. add any required terminations, clock/debug connectors, etc., either in allegro fpga System planner or in your schematic tool all the mundane and error-prone tasks are completed by allegro fpga System planner to ensure a successful outcome. The next steps are as follows: 1. perform power mapping in allegro fpga System planner to wire up all the power pins automatically, and bring them up to different rails. you can connect regulators of your choice to the different rails 2. add a Systemace part and flash for configuring the fpgas. allegro fpga System planner connects the devices automatically 3. define and add the required terminations

schemAtIcs And lAyout

now you can generate the schematics for your design. allegro fpga System planner can automatically generate the schematics for different tools, and it can also generate a cSV file format with all the connectivity information, if you want to use a schematic tool that allegro fpga System planner doesnt support. There are a few things you would need to do in the schematics to take you to board layout. for example, you would need to add all the voltage regulators.

consIderAtIons For successFul PrototyPIng

When designing your fpga board, you should also consider the following: 1. Watch the fpga lUT utilization and fpga i/o utilization carefully. Keeping a low utilization will enable you to use the same board for a longer time

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2. ensure there is sufficient ram left in the fpgas for debug. Tools such as Xilinx chipScope utilize a high amount of ram; you will not be able to use these tools if your fpga ram utilization is high 3. consider connecting each of the fpgas to a debug connector. This allows you to bring out important signals and observe them using an oscilloscope 4. consider using high-speed lVdS connections when possible. rTl partitioning tools can automatically use these high-speed busses to multiplex the traces available on the board. Such highspeed busses effectively multiply the available busses on the board 5. consider a small bus between the fpgas and use it for complex triggering between the fpgas. This can prove to be a very helpful debug aid

conclusIon
allegro fpga System planner provides a simplified approach to aSic prototyping. The current solutions available for aSic prototyping using fpgas either require you to spend an inordinate amount of time creating a custom board, or to buy off-the-shelf fpga boards. The off-the-shelf boards available today cannot satisfy the requirements for complex Socs because they try to fit one size for all. Secondly, these solutions are prohibitively expensive and so do not scale very well. allegro fpga System planner provides a simple approach that scales well with the current requirements for aSic prototyping. it has already been used in several large-scale aSic prototype design projects successfully.

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2010 cadence design systems, Inc. All rights reserved. cadence, the cadence logo, Allegro, and Verilog are registered trademarks of cadence design systems, Inc. Arm is a registered trademark of Arm ltd. All others are properties of their respective holders. 22010 03/11 mK/dm/PdF