Code No: R05321405 Set No.

1
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Explain about sign magnitude and 2’s complement approaches for representing
the fixed point numbers. Why 2’s complement is preferable.
(b) Give means to identify whether or not an overflow has occurred in 2s comple-
ment addition or subtraction operations. Take one example for each possible
situation and explain. Assume 4 bit registers.
(c) Distinguish between tightly coupled microprocessors and tightly coupled Mi-
croprocessors. [16]
2. Design a circuit to increment, decrement, complement and clear a 4 bit register
using RS flip-flops. Explain the control logic. [16]
3. (a) Why do we need subroutine register in a control unit? Explain. [8]
(b) Support or oppose the statement ? the control unit is a firmware. [8]
4. (a) How many bits are needed to store the result addition, subtraction, multipli-
cation and division of two n-bit unsigned numbers. Prove. [8]
(b) What is overflow and underflow? What is the reason? If the computer is
considered as infinite system do we still have these problems. [8]
5. (a) Explain how the Bit Cells are organized in a Memory Chip. [8]
(b) Explain the organization of a 1K x 1 Memory with a neat sketch. [8]
6. (a) What are the different types of I/O communication techniques? Give brief
notes.
(b) In the above techniques, which is the most efficient? Justify your answer.[8+8]
7. Explain the following in related with Vector Processing
(a) Super Computers
(b) Vector operations
(c) Matrix multiplication
(d) Memory interleaving. [4+4+4+4]
8. (a) Explain the working of 8 x 8 Omega Switching network.
(b) Explain the functioning of Binary Tree network with 2 x 2 Switches. Show a
neat sketch. [8+8]

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Code No: R05321405 Set No. 2
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Explain about sign magnitude and 2’s complement approaches for representing
the fixed point numbers. Why 2’s complement is preferable.
(b) Give means to identify whether or not an overflow has occurred in 2s comple-
ment addition or subtraction operations. Take one example for each possible
situation and explain. Assume 4 bit registers.
(c) Distinguish between tightly coupled microprocessors and tightly coupled Mi-
croprocessors. [16]
2. (a) Design a circuit transferring data from a 4bit register which uses D flip-flops
to another register which employs RS flip-flops. [8]
(b) What are register transfer logic languages? Explain few RTL statement for
branching with their actual functioning. [8]
3. (a) What is a pipeline register. What is the use of it? Explain in detail. [8]
(b) Why do we need some bits of current microinstruction to generate address of
the next microinstruction. Support with a live example. [8]
4. (a) Explain Booth’s algorithm with its theoretical basis. [8]
(b) Represent two n-bit unsigned numbers multiplications with a series of n/2-bit
multiplications. [8]
5. Explain the following:
(a) Magnetic Tape Systems
(b) Optical Disc
(c) DVD Technology. [5+5+6]
6. (a) What is daisy chaining? Explain with neat sketch.
(b) What is parallel priority interrupt method? Explain with neat sketch. [8+8]
7. Explain three segment instruction pipeline. Show the timing diagram and show the
timing diagram with data conflict. [16]
8. (a) Explain the working of 8 x 8 Omega Switching network.
(b) Explain the functioning of Binary Tree network with 2 x 2 Switches. Show a
neat sketch. [8+8]

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Code No: R05321405 Set No. 3
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Explain about sign magnitude and 2’s complement approaches for representing
the fixed point numbers. Why 2’s complement is preferable.
(b) Give means to identify whether or not an overflow has occurred in 2s comple-
ment addition or subtraction operations. Take one example for each possible
situation and explain. Assume 4 bit registers.
(c) Distinguish between tightly coupled microprocessors and tightly coupled Mi-
croprocessors. [16]

2. Design a circuit for parallel load operation into one of the four 4-bit registers from a
bus. Mention clearly control/selection bits and selection logic. Assume D flip-flops.
[16]

3. (a) Give the typical horizontal and vertical microinstruction formats. [8]
(b) Describe how microinstructions are arranged in control memory and how they
are interpreted. [8]

4. (a) Explain single precision and double precision calculations. In general how
many bytes are used for both and what is the precision we get. Give some
examples where double precision calculations are needed. [8]
(b) Explain how we can identify arithmetic overflow has occurred or not while
adding/subtracting two signed numbers. Draw the circuit for performing ad-
dition/substraction of two 4 bit numbers that checks the overflow. [8]

5. (a) Explain how the Bit Cells are organized in a Memory Chip. [8]
(b) Explain the organization of a 1K x 1 Memory with a neat sketch. [8]

6. What are the different modes of data transfer? Explain each mode in detail. [16]

7. Explain the following with related to the Instruction Pipeline

(a) Pipeline conflicts

(b) Data dependency
(c) Hardware interlocks
(d) Operand forwarding
(e) Delayed load
(f) Pre-fetch target instruction

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Code No: R05321405 Set No. 3
(g) Branch target buffer
(h) Delayed branch. [8×2=16]

8. (a) Explain the working of 8 x 8 Omega Switching network.

(b) Explain the functioning of Binary Tree network with 2 x 2 Switches. Show a
neat sketch. [8+8]

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Code No: R05321405 Set No. 4
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Find the actual number from its IEEE 754 representation.
Sign = 0
Exponent = 1000 0000
Mantissa = 1100 0000 0000 0000 0000 000 [6]
(b) What is meant by normalization in floating point representation? Why do we
need it? What is bias? What normalization is used in IEEE 754 standard?
[10]

2. (a) Design a circuit transferring data from a 4bit register which uses D flip-flops
to another register which employs RS flip-flops. [8]
(b) What are register transfer logic languages? Explain few RTL statement for
branching with their actual functioning. [8]

3. (a) Why do we need subroutine register in a control unit? Explain. [8]

(b) Support or oppose the statement ? the control unit is a firmware. [8]

4. (a) Represent two n-bit unsigned numbers multiplications with a series of n/2-bit
multiplications. [8]
(b) Explain single precision and double precision calculations. In general how
many bytes are used for both and what is the precision we get. Give some
examples where double precision calculations are needed. [8]

5. (a) How to implement 2K x 32 memory module using 512K x 8 static memory

chips? Show a neat sketch. [8]
(b) How many 128 x 8 RAM chips are needed to provide a memory capacity of
2048 bytes? [4]
(c) How many lines of address bus must be used to access 2048 bytes of memory?
[4]

6. Explain the following:

(a) Isolated Vs Memory mapped I/O

(b) I/O Bus Vs Memory Bus
(c) I/O Interface
(d) Peripheral Devices. [4+4+4+4]

7. Write short notes on the following:

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Code No: R05321405 Set No. 4
(a) Arithmetic pipeline
(b) Four segment instruction pipeline
(c) Timing diagram of instruction pipeline. [5+5+6]

8. (a) What is cache coherence? Explain. [5]

(b) What are the conditions for incoherence? [5]
(c) Explain the solutions to the cache coherence problem. [6]

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