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FSM Test Bench

This document defines an entity called blog_cg that instantiates another entity called seq_det. It defines signals for a clock, reset, sequence input, and detection valid output. A clock process generates a 10ns clock signal. A stimulus process applies a test sequence of 1s and 0s to the sequence input over multiple clock cycles and waits indefinitely.

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Vinod Arumugam
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0% found this document useful (0 votes)
256 views

FSM Test Bench

This document defines an entity called blog_cg that instantiates another entity called seq_det. It defines signals for a clock, reset, sequence input, and detection valid output. A clock process generates a 10ns clock signal. A stimulus process applies a test sequence of 1s and 0s to the sequence input over multiple clock cycles and waits indefinitely.

Uploaded by

Vinod Arumugam
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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LIBRARY ieee; USE ieee.std_logic_1164.

ALL; ENTITY blog_cg IS END blog_cg; ARCHITECTURE behavior OF blog_cg IS signal clk,reset,seq,det_vld : std_logic := '0'; constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.seq_det PORT MAP ( clk => clk, reset => reset, seq => seq, det_vld => det_vld ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process : Apply stim_proc: process begin seq <= '1'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '0'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '0'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '0'; wait for clk_period; seq <= '1'; wait for clk_period; wait; end process; END; the bits in the sequence one by one. --1 --11 --110 --1101 --11011 --110111 --1101110 --11011101 --110111010 --1101110101

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