FSM Test Bench
FSM Test Bench
ALL; ENTITY blog_cg IS END blog_cg; ARCHITECTURE behavior OF blog_cg IS signal clk,reset,seq,det_vld : std_logic := '0'; constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.seq_det PORT MAP ( clk => clk, reset => reset, seq => seq, det_vld => det_vld ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process : Apply stim_proc: process begin seq <= '1'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '0'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '0'; wait for clk_period; seq <= '1'; wait for clk_period; seq <= '0'; wait for clk_period; seq <= '1'; wait for clk_period; wait; end process; END; the bits in the sequence one by one. --1 --11 --110 --1101 --11011 --110111 --1101110 --11011101 --110111010 --1101110101