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Sequential Logic: Inel 4205 Logic Circuits SPRING 2008

The document discusses sequential logic and finite state machines. It covers state equations, Mealy and Moore machines, design procedures including state reduction and assignment, and provides examples of sequence detectors. Exercises are included to design circuits to detect specific sequences using Moore and Mealy state machines.

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Hanish Chowdary
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90 views

Sequential Logic: Inel 4205 Logic Circuits SPRING 2008

The document discusses sequential logic and finite state machines. It covers state equations, Mealy and Moore machines, design procedures including state reduction and assignment, and provides examples of sequence detectors. Exercises are included to design circuits to detect specific sequences using Moore and Mealy state machines.

Uploaded by

Hanish Chowdary
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CHAPTER 5

SEQUENTIAL LOGIC
INEL 4205 LOGIC CIRCUITS
SPRING 2008
STATE EQUATIONS OR
TRANSITION EQUATIONS

OUTPUT BOOLEAN EQUATION


/0 REPRESENTS THE OUTPUT
DURING THE PRESENT STATE
WITH THE GIVEN INPUT

MEALY FINITE STATE MACHINE (FSM) – OUTPUT IS A


FUNCTION OF PRESENT STATE AND INPUT
EXAMPLE:

1. FIND THE STATE TABLE


2. DRAW THE STATE DIAGRAM
MOORE FSM
OUTPUT IS A FUNCTION
OF PRESENT STATE ONLY
DESIGN PROCEDURE
STATE REDUCTION

STATES ARE APPLICATION-DEPENDANT.


THE NAMES GIVEN HERE (A,B,C,D,…)
ARE ARBITRARY.
IT IS ASSUMED THAT ONLY THE OUTPUT
RESPONSE TO A GIVEN SEQUENCE OF
INPUTS IS IMPORTANT.
SEQUENCE DETECTOR: CIRCUIT THAT DETECTS 3 CONSECUTIVE 1’S
IN A STRING OF BITS COMING THROUGH THE INPUT LINE
USING JK OR T FLIP-FLOPS
STATE ASSIGNMENT GUIDELINES

ASSIGN NEIGHBORING CODES IF STATES HAVE THE SAME

NEXT STATE (G1)

PREVIOUS STATE (G2)

OUTPUTS (G3)

PRIORITIZE STATE COMBINATIONS FOR WHICH G1, G2, G3


APPLY MORE THAN ONCE
SEQUENCE DETECTOR FOR 010 OR 1001
next output
present
s0
x=0 x1 x=0 x=1
0/0 1/0 s0 s1 s4 0 0
0/0 s1 s4 1/0
s1 s1 s2 0 0
1/0 1/0
0/0
1/0 s2 s3 s4 1 0
s2 s5

0/1 1/1 0/0 s3 s6 s2 0 0


1/0
s3 s6
0/0 0/0 s4 s5 s4 0 0

s5 s6 s2 0 0

s6 s1 s2 0 1
S3 & S5 ARE EQUIVALENT
SEQUENCE DETECTOR FOR 010 OR 1001 (CONT)

next output (S0,S1,S6), (S2, S4),


present
x=0 x1 x=0 x=1 (S0,S2,S4), (S1,S3,S6)
G1
s0 s1 s4 0 0
s1 s1 s2 0 0 (S1,S2), (S3,S4) G2 ✕ 2

s2 s3 s4 1 0 (S0, S1, S3, S4) G3

s3 s6 s2 0 0 OO O1 11 1O
0 s0 s1 s6 X
s4 s3 s4 0 0
1 s4 s2 X s3
s6 s1 s2 0 1 ONE POSSIBILITY
SEQUENCE DETECTOR FOR 010 OR 1001 (CONT)

Next output
present
x=0 x=1 x=0 x=1
s0 OOO OO1 1OO 0 0

s1 OO1 OO1 1O1 0 0

s2 1O1 11O 1OO 1 0


s3 11O O11 1O1 0 0
s4 1OO 11O 1OO 0 0
s6 O11 OO1 1O1 0 1
EXERCISE

DRAW THE STATE DIAGRAM FOR A CIRCUIT THAT DETECTS THE


SEQUENCE “0101” (LEFT-TO-RIGHT) USING

A MOORE FINITE STATE MACHINE (FSM)

A MEALY FSM
EXERCISE

FOR A CLOCKED SYNCHRONOUS STATE MACHINE WITH TWO


INPUTS, X AND Y, AND ONE OUTPUT, Z, THE OUTPUT SHOULD
BE 1 IF THE NUMBER OF 1 INPUTS ON X AND Y SINCE RESET IS
A MULTIPLE OF 4, AND 0 OTHERWISE. DRAW THE STATE
DIAGRAM FOR A

MOORE MACHINE

MEALY MACHINE
EXERCISE

DESIGN A CIRCUIT TO DETECT THE SEQUENCE


D0D1D2D3D4=01101, WHERE D0 IS THE FIRST BIT TO ARRIVE AT
INPUT “X”. THE OUTPUT “Y” SHOULD BE A LOGIC-1 FOR A FULL
CLOCK CYCLE FOLLOWING DETECTION OF THE SEQUENCE.

DRAW A STATE DIAGRAM

ASSIGN BINARY STATES

WRITE A STATE TABLE

FIND THE COMBINATIONAL CIRCUIT’S LOGIC EXPRESSIONS


IF D, JK AND T FLIP FLOPS WILL BE USED FOR THE 1ST, 2ND
AND 3RD STATE BITS, RESPECTIVELY

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