2x2 Array Multiplier

This Verilog code defines a 2x2 array multiplier module with inputs a and b that are 2-bit vectors and a 4-bit output y. It contains four AND gates to multiply the bits of a and b individually, two halfadder modules to add the partial products, and outputs the sum in y. The code also contains a module for a halfadder with inputs a and b, outputs for sum s and carry co, using a XOR gate for the sum and AND gate for the carry.

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2x2 Array Multiplier

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meera1121

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VERILOG CODE FOR A 2x2 ARRAY MULTIPLIER

~~ Meera.M.Nair ~~
module multiplier (a,b, y);
input [1:0] a, b;
output [3:0] y;
wire t1, t2, t3,t4;
and a1(y[0],a[0],b[0]);
and a2 (t1,a[1],b[0]);
and a3(t2,a[0],b[1]);
and a4(t3,a[1],b[1]);
halfadder ha0(t1,t2,y[1],t4);
halfadder ha1(t3,t4,y[2],y[3]);
endmodule Added Source File
module halfadder(a,b, s,co);
input a,b;
output s,co;
xor x1(s,a,b);
and a1(co,a,b);
endmodule

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2x2 Array Multiplier

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2x2 Array Multiplier

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VERILOG CODE FOR A 2x2 ARRAY MULTIPLIER

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