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Memory RAM, ROM and Memory Systems: Slides of Adam Postula Used

The document discusses different types of computer memory. It describes RAM as random access memory that can be read from or written to at any time by specifying an address. It provides details on the internal organization and timing of RAM chips. ROM is read-only memory where data cannot be changed. EPROM allows data to be erased and reprogrammed. Dynamic RAM uses capacitors that must be periodically refreshed to prevent data loss.

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maheshvarma876
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14K views

Memory RAM, ROM and Memory Systems: Slides of Adam Postula Used

The document discusses different types of computer memory. It describes RAM as random access memory that can be read from or written to at any time by specifying an address. It provides details on the internal organization and timing of RAM chips. ROM is read-only memory where data cannot be changed. EPROM allows data to be erased and reprogrammed. Dynamic RAM uses capacitors that must be periodically refreshed to prevent data loss.

Uploaded by

maheshvarma876
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 35

Lecture 19

MEMORY
RAM,ROM and memory
systems
Slides of Adam Postula used

12/8/2002 1
RAM -
Random Access Memory
◆ Each word in the RAM memory can be read by giving its
address and observing the data lines after some time.
◆ Each word can be re-written by giving its address,
presenting the new data and keeping it stable for some
time.
◆ Addressing can be random ( there are no requirements for
any sequence in addresses ) - hence Random Access
Memory.
◆ Storage matrix is usually very large and organised as a
square matrix of word cells.

12/8/2002 2
256x4 bit RAM
internal organisation
A0 row select
A1
32

32x4
32x4

32x4

32x4

32x4

32x4

32x4

32x4
A2
A3
A4

A5
= 32
column

4 4 4 4 4 4 4 4
select

A6 8
A7 column I/O

A square storage matrix (32 x 32) makes


an optimal design for the layout and delay minimisation.

12/8/2002 3
256x4 bit RAM
Common I/O data lines
A0 row select
A1
32

32x4
32x4

32x4

32x4

32x4

32x4

32x4

32x4
A2
A3
A4

A5
column

4 4 4 4 4 4 4 4
select

A6 8
A7 column I/O

D0 i/o
D1 i/o
D2 i/o
D3 i/o

CS WE
12/8/2002 4
256x4 bit RAM
Separate I/O data lines
A0 row select
A1
32

32x4
32x4

32x4

32x4

32x4

32x4

32x4

32x4
A2
A3
A4

A5
column

4 4 4 4 4 4 4 4
select

A6 8
A7 column I/O

Di0 Do0
Di1 Do1
Di2 Do2
Di3 Do3

CS WE
12/8/2002 5
Read RAM Timing
◆ READ CYCLE

WE

CS

Address

Data Out

12/8/2002 6
Read RAM Timing
◆ READ CYCLE

WE

CS

Address

Data Out

12/8/2002 7
Read RAM Timing
◆ READ CYCLE

WE

CS

Address

Data Out

12/8/2002 8
Read RAM Timing
◆ READ CYCLE

WE

CS

Address

TACS = 45ns
Data Out

TAA = 45ns

12/8/2002 9
Read RAM Timing
◆ READ CYCLE

WE

CS

Address

TACS = 45ns
Data Out

TAA = 45ns

12/8/2002 10
Read RAM Timing
◆ READ CYCLE

WE
TRC = 45ns (min)
CS

Address

TACS = 45ns( max)


Data Out

TAA = 45ns (max)

12/8/2002 11
Read RAM Timing
◆ READ CYCLE

WE
TRC = 45ns (min)
CS

Address

TACS = 45ns( max)


Data Out

TAA = 45ns( max)

12/8/2002 12
RAM Dynamic Parameters
◆ READ CYCLE

WE
TRC = 45ns (min)
CS

Address

TACS = 45ns( max) TOH = 5ns( min)


Data Out

TAA = 45ns( max) THZ = 10ns( max)

12/8/2002 13
Write RAM Timing
◆ WRITE CYCLE
TWP
WE
TCW
CS

Address
TWC

Data In DATA VALID

TDW TDH

Data Out Data Undefined

12/8/2002 14
Write RAM Timing
◆ WRITE CYCLE
WE

CS

Address

Data In DATA VALID

TDW TDH

Data Out Data Undefined

12/8/2002 15
Write RAM Timing
◆ WRITE CYCLE
TWP= 45ns (min)
WE
TCW= 45ns (min)
CS

Address

Data In DATA VALID

TDW TDH

Data Out Data Undefined

12/8/2002 16
Write RAM Timing
◆ WRITE CYCLE
TWP= 45ns (min)
WE
TCW= 45ns (min)
CS

Address
TWC

Data In DATA VALID

TDW = 15ns TDH = 5 ns

Data Out Data Undefined

12/8/2002 17
Read Only Memory - ROM
Vdd

word 0

word 1

word N

MOS transistor

Do0 Do1 DoN-1 DoN

12/8/2002 18
Read Only Memory - ROM
Vdd

word 0
A0
ADDRESS DECODER

Active high
A1 word 1 word lines

Active low
An
internal
word N data lines

No transistor

Do0 Do1 DoN-1 DoN

12/8/2002 19
Erasable Programmable Read Only
Memory - EPROM
Vdd

word 0
A0
ADDRESS DECODER

Active high
A1 word 1 word lines

Active low
An
internal
word N data lines

Programmable transistor

Do0 Do1 DoN-1 DoN

12/8/2002 20
DYNAMIC RAM MEMORY
word select

DYNAMIC MEMORY CELL

bit line

THE BASIC ELEMENT IS A CAPACITOR


THAT HOLDS THE STORED VALUE ONLY FOR A SHORT TIME.
THE STORED VALUE MUST BE 'REFRESHED" PERIODICALLY
TO PREVENT LOST OF DATA.

12/8/2002 21
DYNAMIC RAM MEMORY
word select

DYNAMIC MEMORY CELLs

0 bit line N bit line

STORE AND REFRESH OPERATION

Vcc 1 written refresh refresh refresh 0 written

high
low
0 stored 0 stored time (ms)
0V
4 8 12 16 20 24 28
12/8/2002 22
DYNAMIC RAM MEMORY
row address

row decoder
64 k bits =
latch

256 x 256

A0-A7 A0-A7 ( A8-A15 )


( A8-A15 ) column address latch

CONTROL row data latch


/RAS
/CAS data multiplexer/demultiplexer
/WE

Dout Din

12/8/2002 23
Dynamic RAM Timing
◆ RAS ONLY REFRESH CYCLE

Address Row Address

RAS

Load row-address restore row latch into


Read selected row selected row
and store in a row latch
to restore the read values

12/8/2002 24
Dynamic RAM Timing
◆ READ CYCLE
Address Row Address Column Addr

RAS

CAS
Load column-address
output enable DOUT, drive with selected bit output disable DOUT

DOUT
valid

12/8/2002 25
Dynamic RAM Timing
◆ WRITE CYCLE
Address Row Address Column Addr

RAS

WE

DOUT valid data

CAS
Load column-address
merge Din into selected column of row latch

12/8/2002 26
MEMORY SYSTEM
◆ Build a 128k x 8 static RAM memory system of RAM
chips 64k x 4bit.

A0 - A15 - address lines


A0 Dio0 Dio0 - Dio3 - input/output
tri-state data lines
Dio1
RW - read/write active low
Static
A15 CS - chip select active low
RAM Dio2
64k x4
CS RW Function
RW
Dio3 0 0 Read
CS 0 1 Write
1 x Dio0-Dio3 in TriState

12/8/2002 27
MEMORY SYSTEM 128k x8
A0 - A15

/CS 64k
x4
D0 - D3

/WE
MEMORY SYSTEM 64K x 4

12/8/2002 28
MEMORY SYSTEM 128k x8
A0 - A15

/CS 64k
x4
D0 - D3

/WE
MEMORY SYSTEM 64K x 8

64k
x4
D4 - D7

12/8/2002 29
MEMORY SYSTEM 128k x8
A0 - A15 D0 - D3

/CS 64k 64k


x4 x4
D0 - D3

/WE

D4 - D7
64k 64k
x4 x4
D4 - D7

12/8/2002 30
MEMORY SYSTEM 128k x8
A0 - A15 D0 - D3

/CS 64k 64k


x4 x4
D0 - D3

/WE

D4 - D7
64k 64k
x4 x4
D4 - D7

12/8/2002 31
MEMORY SYSTEM 128k x8
A0 - A15 D0 - D3

/CS = A16 64k 64k


x4 x4
D0 - D3

/WE

D4 - D7
64k 64k
x4 x4
D4 - D7

12/8/2002 32
MEMORY SYSTEM 128k x8
A0 - A15 D0 - D3

64k 64k
/CS = A16 = 0 x4 x4
D0 - D3

/WE 1

D4 - D7
64k 64k
x4 x4
D4 - D7

12/8/2002 33
MEMORY SYSTEM 128k x8
A0 - A15 D0 - D3

64k 64k
/CS = A16 = 1 x4 x4
D0 - D3

/WE 0

D4 - D7
64k 64k
x4 x4
D4 - D7

12/8/2002 34
What have we learnt?
◆ RAM - Random Access Memory allow to read/write data
at a randomly chosen address to the contrary of
a floppy disk where the data is stored and accessed in sequence.
◆ ROM - Read Only Memory allows to read data stored
(during programming) at a randomly chosen address.
◆ EPROM allows to program the contents of the memory and later
read it.Programming is much slower than reading.
◆ Dynamic RAM achieve the largest density and is the prevalent
technology for computer memories.
◆ Memory chips can be organised in memory systems of various
depth and width.

12/8/2002 35

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