Low Power

VLSI Design

Abdulla K P
 Power vs Energy

• For battery operated devices,

the distinction between power
and energy is critical.
• Power is the instantaneous
power in the device.
• Energy is the area under the
curve—the integral of power
Power vs Energy
 Power vs Energy
• The power used by a cell phone,
for example, varies depending
on the what it is doing—
whether it is in standby with the
cover closed, or open and the
display is powered up, or
downloading from the web.
 Dynamic Power and
Static Power
• The total power in CMOS devices

consists of dynamic power and

static power.

• Dynamic power is the power

consumed when the device is

 Dynamic Power and
Static Power
• Static power is the power

consumed when the device is

powered up but no signals are

changing value.

• In CMOS devices, static power

 Dynamic
Power - I
The first and primary source of

dynamic power consumption is

switching power—the power required

to charge and discharge the output

capacitance on a gate.
Dynamic Power - I
The energy per transition is given by:

Where CL is the load capacitance and Vdd is

the supply voltage. We can then describe the
dynamic power as:

Where ƒ is the frequency of transitions, Ptrans

is the probability of an output transition, and
ƒclock is the frequency of the system clock.
If we define

• We can also describe the dynamic

power with the more familiar
expression:

Note that switching power is not a

function of transistor size, but rather a
function of switching activity and load
capacitance. Thus, it is data
dependent.
 Dynamic Power - II
Short Circuit Current --- Crowbar
• In addition Current
to switching power,
internal power also contributes
to dynamic power.
• Internal power consists of the
short circuit currents that occur
when both the NMOS and PMOS
transistors are on as well as the
• If we add the expression for
internal power to our equation,
we can describe the dynamic
power as:

Where tsc is the time duration of

the short circuit current, and
Ipeak is the total internal
switching current (short circuit
 Dynamic Power - II

The short circuit current (often called

crowbar current)
• As long as the ramp time of the
input signal is kept short, the
short circuit current occurs for
only a short time during each
transition, and the overall
dynamic power is dominated by
the switching power.
• For this reason, we often
simplify the use the switching
• But there are occasions when
the short circuit current (often
called crowbar current) is of
interest. In particular, we will
discuss ways of preventing
excess crowbar current when we
talk about how to deal with the
There are a number of techniques at the
architectural, logic design, and circuit
design that can reduce the power for a
particular function implemented in a
given technology.
These techniques focus on the
voltage and frequency components
of the equation, as well as reducing
the data-dependent switching
activity.
There are a variety of architectural and
logic design techniques for minimizing
switching activity, which effectively lowers
switching activity for the gates involved.
• Because of the quadratic
dependence of power on
voltage, decreasing the supply
voltage is a highly leveraged
way to reduce dynamic power.
• But because the speed of a gate
decreases with decreases in
supply voltage, this approach
 Static Power
There are four main sources of
leakage currents in a CMOS gate
1. Sub-threshold Leakage (ISUB):
the current which flows from
the drain to the source current
of a transistor operating in the
weak inversion region.
2. Gate Leakage (IGATE): the
current which flows directly
from the gate through the
oxide to the substrate due to gate
 Static Power

3. Gate Induced Drain Leakage (IGIDL):

the current which flows from the
drain to the substrate induced by a
high field effect in the MOSFET drain
caused by a high VDG.
4. Reverse Bias Junction Leakage
(IREV): caused by minority carrier
drift and generation of electron/hole
pairs in the depletion regions.
Static Power
Sub-threshold leakage occurs when a CMOS
gate is not turned completely off. To a good
approximation, its value is given by

Where W and L are the dimensions

of the transistor, and Vth is the
thermal voltage kT/q (25.9mV at
This equation tells us that sub-threshold
leakage depends exponentially on the
difference between VGS and VT.

So as we scale VDD and VT down (to limit

dynamic power) we make leakage power
exponentially worse.
 There are several approaches to
minimizing leakage current.
1. One technique is known as
Multi-VT: using high VT cells
wherever performance goals
allow and low VT cells where
necessary to meet timing.
 The Conflict Between
Dynamic and Static
Power
The most effective way to reduce dynamic power is
to reduce the supply voltage.
Over the last fifteen years, as semiconductor
technology has scaled, VDD has been lowered from
5V to 3.3V to 2.5V to 1.2V.
The ITRS road map predicts that for 2008 and 2009
high performance devices will use 1.0V and low
power devices will use 0.8V.

ITRS  The International Technology Roadmap for

Semiconductors
• The trouble with lowering VDD is
that it tends to lower IDS, the on
or drive current of the
transistor, resulting in slower
speeds.
• If we ignore velocity saturation
and some of the other subtle
effects that occur below 90nm,
the IDS for a MOSFET can be
• Where μ is the carrier mobility,
Cox is the gate capacitance, VT
is the threshold voltage and VGS
is the gate-source voltage.
• From this it is clear that, to
maintain good performance, we
need to lower VT as we lower
VDD (and hence VGS).
• However, lowering the threshold
• Thus there is a conflict.
• To lower dynamic power we
lower VDD; to maintain
performance we lower VT; but
the result is that we raise
leakage current.
• Until now, this was a
reasonable process, since static
power from leakage current
Thank you