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VHDL Pgms

The document describes a decade counter and shift register circuit in VHDL and Verilog. The decade counter entity counts from 0 to 9 on each clock cycle and resets to 0 asynchronously when a reset signal is asserted. The shift register shifts the contents of an 8-bit signal vector by 1 bit on each clock cycle, taking the serial input on one end and outputting the last bit on the other end.

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prabha_vel
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© Attribution Non-Commercial (BY-NC)
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38 views

VHDL Pgms

The document describes a decade counter and shift register circuit in VHDL and Verilog. The decade counter entity counts from 0 to 9 on each clock cycle and resets to 0 asynchronously when a reset signal is asserted. The shift register shifts the contents of an 8-bit signal vector by 1 bit on each clock cycle, taking the serial input on one end and outputting the last bit on the other end.

Uploaded by

prabha_vel
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Decade Counter:

ibrary IEEE;                                                          --library definition


use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Counter is                                                    --entity definition


  port (
    clk:in std_logic;
    reset: in std_logic;
    q: out std_logic_vector(3 downto 0)
    );
end Counter;

architecture Counter of Counter is                         -- Architecture definition

begin
      process(clk,reset)                                           -- Process definition
   variable qtemp: std_logic_vector(3 downto 0);   -- temporary variable
for output q[3..0]
  begin
   if reset='1' then
    qtemp:="0000";                                               -- Reset asychroniously
   else
    if clk'event and clk='1' then                              -- Counting state
     if qtemp<9 then
      qtemp:=qtemp+1;                                         -- Counter increase
     else
      qtemp:="0000";                                             -- Return the zero state
     end if;
    end if;
   q<=qtemp;                                                      -- Output
    end if;
  end process;                                                      -- End Process
end Counter;                                                       -- End Architecture

Shift Register 8bit

VHDL Code
library ieee;
use ieee.std_logic_1164.all;

entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) = tmp(i);
end loop;
tmp(0) = SI;
end if;
end process;
SO = tmp(7);
end archi;

Verilog Code:
module shift (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;

always @(posedge C)
begin
tmp = tmp 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule

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