Homework Title: Design of handshake mode with 8255 using 8086 Course Code: ECE 212

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Handshaking refers to the process of Example – printer interface
communicating back and forth between two
From the data segment:
Intelligent devices
MYDATA DB “Ceva", CR, LF, "$"
• 8255 handles handshaking signals (a
PA EQU 300H ;port A
powerful built in features of the 8255)
PB EQU 301H ;port B
• Printers are good example for a device
PC EQU 302H ;port C
with handshaking capabilities
CWP EQU 303H ;control word
LF EQU OAH ;line feed
CR EQU ODH ;carriage return
From the code segment:
;control word PA=out mode 1
MOV AL, 10100000B
MOV DX, CWP
;issue control word
OUT DX, AL
;PC6= 1 for INTEa
PRINTER HANDSHAKING SIGNALS MOV AL, 00001101 B

1. A byte of data is presented to the data bus ; using BSR mode

of the printer. MOV DX, PC

OUT DX, AL

2. The printer is informed of the presence of ;SI = data address

a byte of data to be printed by activating its MOV SI, OFFSET MYDATA

STROBE input signal. Print the string using “Polling”

AGAIN:

3. Whenever the printer receives the data it MOV AH,[SI] ;get a character

informs the sender by activating an output CMP AH,'$' ;is it the end?

signal called ACK (acknowledge). JZ OVER ;if yes, exit

MOV DX,PC ;DX=302 port C address

4. The ACK signal initiates the process of BACK:

providing another byte of data to the printer. IN AL,DX ;get status byte from port C
AND AL,08 ;is INTRa high?
JZ BACK ;if no, keep checking • Port a
MOV DX,PA ; if yes, make DX=300 data
• Port b
port
MOV AL,AH ;addressand • Port c
OUT DX,AL ;send char to printer
o Port c upper
INC SI ;increment the data pointer
JMP AGAIN ;keep doing it o Port c lower
OVER: ... ;go back to DOS
operating modes of 8255A PPI :

8255 mode :  Two 8-bit ports (A and B)

 Two 4-bit ports (Cu and CL0

The 8255A is a widely used, programmable,  Data bus buffer

parallel I/O device.It can be  Control logic
programmed to transfer data under various
conditions, from simple I/O to interrupt I/O.
The intel 8255 has the following 3 modes of
It reduces the external logic normally operations which are selected by software :
needed to interface peripheral devices. The
• Mode 0-simply i/o
8255A/82C55A replaces a significant
percentage of the logic required to support a • Mode1- strobed i/o
variety of byte oriented input/output
interfaces. • Mode2 –bidirectional

it has 2 versions : The 8255 has two 8 bit ports and two 4 bit
ports. The RD#, WR#, A0 and A1 (Port
• INTEL8255
Select 0 and Port Select 1) signals are input
• INTEL 8255A-5 into the device. The Read/Write Control
Logic issues control words to the device
There are some differences in their electrical
Group A and Group B Controls. The Group
characteristics.its main function are to
A and Group B Controls, in turn, issue
interface peripheral devices to the
commands to the associated ports. The
microcomputer.it has three 8 bit ports
Control Groups are defined as:
namely
Control Group A: Port A and Port C upper MODE 1
(C7-C4).
• Simple I/O with handshaking capabilities
Control Group B: Port B and Port C lower
• Ports A and B can be used as input or
(C3-C0).
output ports with handshaking capabilities
• Handshaking signals are provided by the
The specifications for the peripheral device
bits of port C (the device provides the
are examined to determine the control and
handshaking
data signals which must be supported by the
Signals)
8255A/82C55A. The 8255A/82C55A is then
programmed to provide the correct I/O and
data paths.
input/output feature in Mode 0 for the
8255A PPI :
_ Outputs are latched
_ Inputs are not latched
_ Ports do not have handshake or interrupt
capability

output control signals used in 8255A PPI

 OBF _output Buffer Full
 ACK _Acknowledge
MODE 2
 INTR _Interrupt request
 INTE _Interrupt Enable
Bidirectional port A with handshaking
capabilities
MODE1: INPUT PROTS WITH
• Port A can be used as a bidirectional I/O
HANDSHAKING SIGNALS
port with handshaking capabilities whose
signals are
The 8255 can be programmed to receive
Provided by port C. (the device provides the
data through ports A and B using
handshaking signals)
handshaking signals through port C
 Mode 2 timing diagram

A - mode 2 and B - mode 1 input

BSR (BIT SET/RESET) MODE

A unique feature of port C is that the bits

can be controlled individually. BSR mode
allows one to set too high or low any of PC0
to PC7 as shown in Figure below.

EXAMPLE:
Program PC4 of the 8255 in the following
Figure to generate a pulse of 50 ms with
50% duty cycle.
 The signals are as follows:

SOLUTION: From the figure:

 A and B are configured as input

To program the 8255 in BSR mode,
ports
• bit D7 of the control word must be low.
 PORT A uses upper three signals
• For PC4 to be high, we need a control
word of ‘0xxx1001". PC3, PC4 and PC5.
 PORT B uses lower three signals
• Likewise, for low we would need
“0xxx1000" as the control word. PC0, PC1 and PC2.

• The x's are for "don't care" and generally

are set to zero.
MVI A,09H ; load the control byte (PC4=1)
OUT 93H ;set PC4 to high, sent to control
reg
CALL DELAY ;time for the high part of
pulse
MVI A,08H ;load the control byte (PC4=0)
OUT 93H ;set PC4 to low, sent to control
reg
CALL DELAY ;time for the low part of
STB STORBE
pulse
Active-low input signal.
• When an external peripheral device
INTR (INTRUPT REQUEST)
provides a byte of the data to an input port
(A or B), it informs the 8255 through the Active-high output signal to interrupt the
STB pin that PERIPHERAL HAS CPU.
TRANSMITTED and it can load (latch in)
the data into its internal register • If INTE =1 , STB’=1, IBF=1
• When IBF goes active, INTR is activated
• This signal goes low (active), stays low for (set to high) to inform the CPU that there is
a time, and goes back high. The amount of a byte
time it stays low depends on the device. Of data in the 8255.
• Either an interrupt or polling the status
word can be used to read the data from port
A or B.
• It is only when the CPU reads the data by
activating the RD (going low) signal of the
8255 that INTR becomes inactive (the
falling edge of RD makes INTR go low) The
RD signal from the CPU is of limited
duration and when it goes high, the 8255 in
The 8255 in response to strobe generates turn makes IBF inactive by setting it low.
IBF and INTR
• IBF informs the peripheral device that the
byte of data was latched by the 8255 and
IBF (INPUT BUFFER FULL)
transferred to the CPU as well.
Active-high output signal. • By receiving IBF, the external device
• In response to STB, the 8255 latches into knows it can send another byte to the 8255's
its internal register the data present at PA0- port
PA7 or PB0-PB7, and through IBF indicate A or port B.
that it has latched the data, but it has not • Then it sets low STB, and the process is
been read by the CPU yet repeated.
• To get the attention of the CPU to read the • Notice that INTR is set to one when all
data, IBF activates INTR (sets it high). three signals STB, IBF, and INTE are high.
 • INTEa can be set or reset through port C in
OFBA (OUTPUT BUFFER FULL FOR BSR mode since the INTEa flip-flop is
PORT A) controlled through PC6
Active-low signal going out of PC7 • INTEb is controlled by PC2 in BSR mode

• Indicate that the CPU has written a byte of STATUS WORD

data into port A, so the receiving peripheral
device can read it 8255 enables monitoring the status of
• OBFa must be connected to STROBE of signals INTR, OBF, and INTE for both ports
the receiving equipment (such as a printer) A and B
• This is done by reading port C into the
ACKA (ACKNOWLEDGE PORT A) accumulator and testing the bits
• This feature allows the implementation of
Active-low signal (Has limited duration) polling

• Received at PC6 of the 8255

• Indicates that the data at port A has been
picked up by the receiving device
• The 8255 in turn makes OBFa high, to
indicate that the data at the port is old data
• OBFa will not go low until the CPU writes
a new byte of data to port A.
INTRUPTS Vs POLLLING
INTEA (INTRUPT ENABLE FOR
PORT A) The CPU services various devices. There are
two ways for the CPU to provide service to
8255 can disable INTRa to prevent it from those devices: interrupts and polling.
interrupting the CPU • In the interrupt method, whenever any
• INTEa is an internal flip-flop designed to device needs its service, the device informs
mask (disable) INTRa the CPU by sending it an interrupt signal.
The CPU interrupts whatever it is doing and
serves the request for service.
• In polling, the CPU continuously monitors The 8288 is needed to decode the 8088's
a status condition and when the conditions status outputs since we are operating the
are met it will perform the service. 8088 in maximum mode. In addition to
• The advantage of interrupts is that the CPU generating the memory and io-port
can serve many devices (of course, not all at read/write signals the 8288 also controls the
the same time). Each device receives service bidirectional data bus driver (the 8286) and
from the CPU based on the priority assigned the lower address latch chip (the 8282).
to it. It can also ignore (mask) a device Since the upper address lines are not
request for service. multiplexed all we need to do is buffer them,
• The disadvantage of interrupts is that they hence the use of the LS244 octal buffer.
require much more hardware and software. Buffering the address and data lines is very
• In contrast, polling is cheap and requires important if future expansion of the system
minimal software, but it ties down the CPU. memory or i/o spaces is desired.
To avoid tying down the CPU, interrupts are
the preferred choice  The 8088 CPU runs from an 8284
driven by a 10 MHz crystal.
 EPROM: 2764 8K-bytes, E000 to
8088 Single Board Microcomputer FFFF
System Hardware
 RAM: 6264 8K-bytes, 0000 to 1FFF
The purpose of this document is to briefly  PARALLEL I/O: Two 8255's
describe the theory of operation behind the
8088 Single Board Microcomputer. The  Analog: port A (00) drives a 1408
system has been designed to meet the
DAC
following requirements:
 port B (01) reads the 0804 ADC
1) A sufficiently large memory (both RAM
and ROM)  port C (02) controls the 0804
 Control port (03)
2) Parallel i/o capabilities
 Digital port A (20)
3) Serial i/o capabilities
 port B (21)
4) Analog i/o capabilities  port C (22)

5) A maximum mode system  Control port (23)

 SERIAL I/O: 8251 with 1488/89 line
driver/receivers
  port (40) data
 port (41) Control/Status
 Since the 8088 will execute its first
instruction starting at address FFFF0
the equivalent address in our system
is FFF0 because we ignore the upper
4 address lines. This address
corresponds to address 1FF0 in the
EPROM and starting at this location
is the following code:
 which performs a long jump to the
start of the monitor (EPROM address
100, CS equal to 0E00).

REFERENCES:

1. www.wikipedia.com

2. www.ask.com

3. Book of microprocessor by Gonker

4. Book of microprocessor by B.ram