HITEC University Taxila

Department of Electrical Engineering

Assignment # 01
ASIC Design

Submitted To:
Mr Fahad Islam Chema

Submitted By:
Nisar Ahmed Rana
07-HITEC-EE-94
Q1 of Exercise 6.7: Test Bench:-
module sb(q,b,x,y,z); module sb_sbtb_v_tf();
output q,b; reg x,y,z;
input x,y,z; wire q,b;
wire x0,y0,z0,q1,q2,q3,q4,v1,v2,v3; sb s1(q,b,x,y,z);
not n1(x0,x); initial
not n2(y0,y); begin
not n3(z0,z); x=0;y=0;z=0;
and A1(q1,x0,y0,z); #500 $display("x=%b,y=%b,z=%b",x,y,z);
and A2(q2,x0,y,z0); x=0;y=0;z=1;
and A3(q3,x,y0,z0); #500 $display("x=%b,y=%b,z=%b",x,y,z);
and A4(q4,x,y,z); x=0;y=1;z=0;
or (q,q1,q2,q3,q4); #500 $display("x=%b,y=%b,z=%b",x,y,z);
and B1(v1,x0,z); x=0;y=1;z=1;
and B2(v2,x0,y); #500 $display("x=%b,y=%b,z=%b",x,y,z);
and B3(v3,y,z); x=1;y=0;z=0;
or (b,v1,v2,v3); #500 $display("x=%b,y=%b,z=%b",x,y,z);
endmodule x=1;y=0;z=1;
#500 $display("x=%b,y=%b,z=%b",x,y,z);
x=1;y=1;z=0;
#500 $display("x=%b,y=%b,z=%b",x,y,z);
x=1;y=1;z=1;
#500 $display("x=%b,y=%b,z=%b",x,y,z);
End
endmodule
Figure:-

Exercise 7.11 Test Bench:-

module Q11_Q1tb_v_tf();
Q1:- reg osc;
module Q11(osc); Q11 O(osc);
input osc; initial
endmodule begin
osc=1'b0;
forever #30 osc=~osc;
end
endmodule

Figure:-
Q2:- Test Bench:-
module Q2(clk); module Q2_Q2tb_v_tf();
input clk; reg clk;
endmodule Q2 a1(clk);
always
begin
#30 clk=1;
#10 clk=0;
end
initial
begin
clk=1'b0;
end
endmodule

Figure:-

5 z=#5 1'b0
Q3 undefine w=#20 {x,y,z};
Statement Executed 100 $finish
0 x=1'b0
10 y=#10 1'b1 Q5
15 z=#5 1'b0 x=0
35 w=#20 {x,y,z}; y=1
100 $finish z=1
w=0
Q4
Time Statement Executed Q6
0 x=1'b0 The finial value “w” is 1.
10 y=#10 1'b1

Q7 Test Bench:-
module Q2(q,d,clk,rst); module Q2_Q2tb_v_tf();
output reg q; reg clk;
input d,clk,rst; reg d;
always @ (posedge clk) reg rst;
if(~rst) begin wire q;
q<=1'b0; Q2 m(q,d,clk,rst);
end always
else begin #5 clk=~clk;
q<=d; initial
end begin
endmodule clk=1'b0;
d=1'b1;
rst=1'b0;
#5 rst=1'b1;
d=1'b0;
end
endmodule
Figures:-
Q8 Test Bench:-
module Q2(q,d,clk,rst); module Q2_Q2tb_v_tf();
output reg q; reg clk;
input d,clk,rst; reg d;
always @ (posedge clk,negedge rst) reg rst;
if(rst) begin wire q;
q<=1'b0; Q2 m(q,d,clk,rst);
end always
else begin #5 clk=~clk;
q<=~q; initial
end begin
endmodule clk=1'b0;
d=1'b1;
rst=1'b0;
#5 rst=1'b1;
end
endmodule
Figure:-

Q9:- Test Bench:-

module lssl(q,d,clk); module lssl_lssltb_v_tf();
output reg q; reg clk;
input d; reg d;
input clk; wire q;
always @ (clk or d) lssl m(q,d,clk);
begin always
if(clk) #5 clk=~clk;
q<=d; initial
end begin
endmodule clk=1'b0;
d=1'b0;
#5d=1'b1;
#5d=1'b0;
#5d=1'b1;
#5d=1'b0;
#5d=1'b1;
#5d=1'b0;
#5d=1'b1;
#5d=1'b0;
#5d=1'b1;
#5d=1'b0;
#5d=1'b1;
#5d=1'b0;
#5d=1'b1;
#5d=1'b0;
end
endmodule

Figure:-
Q 15:- Test Bench:-
module cllk(clk); module cllk_cllktb_v_tf();
input clk; reg clk;
endmodule cllk C(clk);
initial
begin
clk=1'b0;
forever
begin
#6 clk=1;
#4 clk=0;
end
end
endmodule

Figure:-