UNIT 3

COMBINATIONAL CIRCUIT
DESIGN
 VHDL CODES
 Encoder
 Decoder
 Multiplexer
 Demultiplexer
 Comparator
 Combinational circuits
 4 to 1 MULTIPLEXER CODE
ENTITY mux4to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC );
END mux4to1;
ARCHITECTURE Behavior OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w(0) WHEN "00",
w(1) WHEN "01",
w(2) WHEN "10",
w(3) WHEN OTHERS;
END Behavior;
 2—to-1 MUX as a PROCESS
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ( w0, w1, s )
BEGIN
IF s = '0' THEN
f <= w0 ;
ELSE
f <= w1 ;
END IF ;
END PROCESS ;
END Behavior ;
 2-to-4 binary decoder VHDL code
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(0 TO 3));
END dec2to4;
ARCHITECTURE Behavior OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
Enw <= En & w;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS;
END Behavior;
 Priority encoder VHDL code
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
z : OUT STD_LOGIC );
END priority;
ARCHITECTURE Behavior OF priority IS
BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00";
z <='0' WHEN w = "0000" ELSE '1';
END Behavior;
 2-to-4 binary decoder with CASE
ARCHITECTURE Behavior OF dec2to4 IS
BEGIN
PROCESS ( w, En )
BEGIN
IF En = '1' THEN
CASE w IS
WHEN "00" => y <= "1000" ;
WHEN "01" => y <= "0100" ;
WHEN "10" => y <= "0010" ;
WHEN OTHERS => y <= "0001" ;
END CASE ;
ELSE
y <= "0000" ;
END IF ;
END PROCESS ;
END Behavior;
 Demultiplexer VHDL code
ENTITY dmux8 IS
PORT(s : IN STD_LOGIC_VECTOR (2 downto 0);
d : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (0 to 7));
END dmux8;
ARCHITECTURE a OF dmux8 IS
SIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0);
BEGIN
inputs <= d & s;
 WITH inputs select
Y <= “01111111” WHEN “0000”,
“10111111” WHEN “0001”,
•••
•••
“11111111” WHEN others;
END a;
 VHDL 4-Bit Magnitude Comparator
ENTITY compare4 IS
PORT(a, b : IN INTEGER RANGE 0 to 15;
agtb, aeqb, altb : OUT STD_LOGIC);
END compare4;
ARCHITECTURE a OF compare4 IS
SIGNAL compare :STD_LOGIC_VECTOR (2 downto 0);
BEGIN
PROCESS (a, b)
BEGIN
IF a<b THEN
compare <= “110”;
ELSIF a = b THEN
compare <= “101”;
 ELSIF a > b
THEN
compare <= “011”;
ELSE
compare <= “111”;
END IF;
agtb <= compare(2);
aeqb <= compare(1);
altb <= compare(0);
END PROCESS
END a;
n-bit Comparator
this simple comparator has two n-bit inputs & three 1-bit
outputs

library ieee;
use ieee.std_logic_1164.all;
entity Comparator is generic(n: natural :=2);
Port (A:in std_logic_vector(n-1 downto 0); B:in std_logic_vector(n-1
downto 0);less:out std_logic; equal:out std_logic;greater:out std_logic);
end Comparator;
architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
 VHDL Code For HalfAdder
entity HalfAdder is
port(i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic;
o_c : out std_logic);
end HalfAdder ;
architecture main of HalfAdder is
component QuarterAdder
port(i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic);
end component;
begin
o_c <= i_a and i_b;
QuarterAdder port map( i_a, i_b, o_s);
end main;
 Full Adder VHDL code
Entity FullAdd is
port (i_a, i_b,i_c : in std_logic;
o_s,o_c : out std_logic);
End FullAdd;
Architecture main of FullAdd is
Begin
o_s<=i_c xor i_a xor i_b;
o_c<=(i_c and ( i_a or i_b)) or (i_a and i_b);
End main;
 VHDL code for a 1 bit Adder

 if c = ‘0’ then
if (a and b) = ‘1’ then
sum <= ‘0’;
carry <= ‘1’;
elsif (a or b) = ‘1’ then
sum <= ‘1’;
carry <= ‘0’
end if;
elsif c = ‘1’ then
if (a and b) = ‘1’ then
sum <= ‘1’;
carry <= ‘1’;
elsif (a or b) = ‘1’ then
sum <= ‘0’;
carry <= ‘1’;
end if;
end if;
 Combinational circuit
 A simple example of VHDL Structure Modeling -- we might define two
components in two separate files, -- in main file, we use port map statement to
instantiate -- the mapping relationship between each components -- and the entire
circuit.
 library ieee; -- component #1
use ieee.std_logic_1164.all;
entity OR_GATE is
port( X: in std_logic; Y: in std_logic; F2: out std_logic );
end OR_GATE;
architecture behv of OR_GATE is
begin
process(X,Y)
begin
F2 <= X or Y; -- behavior des.
end process;
end behv;
 library ieee; -- component #2
use ieee.std_logic_1164.all;
entity AND_GATE is
port( A: in std_logic; B: in std_logic; F1: out std_logic );
end AND_GATE;
architecture behv of AND_GATE is
begin
process(A,B)
begin
F1 <= A and B; -- behavior des.
end process;
end behv;
 library ieee; -- top level circuit
use ieee.std_logic_1164.all;
use work.all;
entity comb_ckt is
port( input1: in std_logic; input2: in std_logic; input3: in std_logic; output:
out std_logic );
end comb_ckt;
architecture struct of comb_ckt is
component AND_GATE is -- as entity of AND_GATE
port( A: in std_logic; B: in std_logic; F1: out std_logic );
end component;
component OR_GATE is -- as entity of OR_GATE
port( X: in std_logic; Y: in std_logic; F2: out std_logic );
end component;
signal wire: std_logic; -- signal just like wire begin
Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);
Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);
end struct;
REALIZATION OF CODE
CONVERTER USING D F/F
 VHDL code for BCD TO EXCESS3 code
converter

library ieee ;
use ieee.std_logic_1164.all ;
entity SM1_2 is
port(X, CLK: in bit; Z: out bit);
end SM1_2;

architecture Table of SM1_2 is

signal State, Nextstate: integer := 0;
begin
process(State,X) --Combinational Network
begin
case State is
when 0 =>
if X='0' then Z<='1'; Nextstate<=1; end if;
if X='1' then Z<='0'; Nextstate<=2; end if;
when 1 =>
if X='0' then Z<='1'; Nextstate<=3; end if;
if X='1' then Z<='0'; Nextstate<=4; end if;
when 2 =>
if X='0' then Z<='0'; Nextstate<=4; end if;
if X='1' then Z<='1'; Nextstate<=4; end if;
when 3 =>
if X='0' then Z<='0'; Nextstate<=5; end if;
if X='1' then Z<='1'; Nextstate<=5; end if;
when 4 =>
if X='0' then Z<='1'; Nextstate<=5; end if;
if X='1' then Z<='0'; Nextstate<=6; end if;
when 5 =>
if X='0' then Z<='0'; Nextstate<=0; end if;
if X='1' then Z<='1'; Nextstate<=0; end if;
when 6 =>
if X='0' then Z<='1'; Nextstate<=0; end if;
when others => null; -- should not occur
end case;
end process;
process(CLK) -- State Register
begin
if CLK='1' then -- rising edge of clock
State <= Nextstate;
end if;
end process;
end Table;
WAVEFORM FOR BCD TO EXCESS -3
 VHDL code for a Serial to Parallel
Converter

    
if clear = ‘0’ then
shift_reg <= “00000000”;
elsif (clock’event and clock = ‘1’) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;