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Opcode Fetch

The document summarizes the opcode fetch, memory read, and memory write cycles of the 8085 microprocessor. Opcode fetch involves placing the address on the address bus from T1-T3, transferring the opcode from memory to the instruction register at T3. Memory read places the address on the bus at T1-T2, then transfers data from memory to the data bus at T3. Memory write is similar but outputs data from the processor to memory at T3. All cycles involve incrementing the program counter and sampling signals like ready, hold, and halt at different times.

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33 views

Opcode Fetch

The document summarizes the opcode fetch, memory read, and memory write cycles of the 8085 microprocessor. Opcode fetch involves placing the address on the address bus from T1-T3, transferring the opcode from memory to the instruction register at T3. Memory read places the address on the bus at T1-T2, then transfers data from memory to the data bus at T3. Memory write is similar but outputs data from the processor to memory at T3. All cycles involve incrementing the program counter and sampling signals like ready, hold, and halt at different times.

Uploaded by

mekrishna_sharma
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
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Opcode fetch (OF):

 T1
o External: IO/M=0, S0=1, S1=1. Address on AD0-AD7 (upto T1) and A8-A15 (upto
T3). ALE is high.
o Internal: Reset-in sampled. HALT f/f sampled.
 T2:
o External: AD0-AD7 disappears. RD is low. Memory device puts data on data bus
AD0-7.
o Internal: PC incremented. Ready i/p is sampled at T2 rising edge (wait state added if
low). HOLD sampled, HLDA f/f set if HOLD is high and OF is completed.
 Wait state (optional):
o External: T2 levels of addr, data, and control lines maintained. No external ops.
o Internal: Samples Ready i/p at wait-state's rising edge. If low, adds another wait
state.
 T3:
o External: Data (opcode; this is OF) is transferred to instruction register. RD made
high.
o Internal: Takes opcode from data bus into instruction register and gives to decoder.
 T4:
o External: None
o Internal: Opcode decoded. Finds out whether to do T5 and T6, and number of bytes
of instruction. During T4 of 4T, HLDA f/f is sampled (if set, T4 is completed, buses
floated, HLDA high, HOLD state entered). During T4 of 6T, HOLD is sampled and
HLDA f/f is set if necessary.
 T5 and T6: Used only for CALL, CALL conditional, DCX, INX, PCHL, PUSH, SPHL, and RET
conditional.
o External: None
o Internal: Performs condition check, stack/register operations. Samples HLDA f/f (if
set, goes into hold mode after T6)

Memory Read (MR)

 T1:
o IO/M=0, S0=0, S1=1.
o addr->addrbus (ALE high) (In memory read, addr is given by instruction. In operand
fetch, addr is given by PC)
o HALT f/f sampled
o Other ops same as OF-1
 T2:
o RD made low. AD0-AD7 removed.
o Other ops same as OF-2
 Wait state: Same as OF-WS
 T3:
o data: memory->8085->internal data bus
o RD high
o If fetching operand, PC is incremented
o Same as OF-3 except data is not put in instruction register, and HLDA f/f is sampled.

Memory Write (MW)


 T1:
o IO/M=0, S0=1, S1=0.
o addr->addrbus (ALE high)
o Other ops same as MR-1
 T2:
o Ext: WR made low. AD0-AD7 removed.
o Int: Other ops same as OF-2
 Wait state: Same as OF-WS
 T3:
o data: 8085->memory location
o WR high
o Similar to OF-3

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