Solutions Manual

Using the product formula trigonometric identity,

7
9P ,P
7 ∫
3 DYJ - ( FRV ( φ 9 ± φ , ) ± FRV ( ωW  φ 9  φ , ) ) GW
-------------


Therefore,
9P ,P 9P ,P
3 DYJ -------------- FRV ( φ 9 ± φ , ) -------------- FRV ( θ )
 

7
--- ∫ , P VLQ ( ωW  φ , ) GW
 
2.37 , UPV
7


Using the double angle trigonometric identity,

7
,P  
, UPV ----- ∫ --- ± FRV [  ( ωW  φ , ) ] GW
7  


Therefore,

, P  7 ,P
, UPV ----- --- -----
7   

5 5
2.38 5  ------------------
- NΩ
5  5

5  --- VLQ ( πW )

9R --------------------
-9
5   5  L 
This is a sin wave with half the amplitude of the input with a period of 1s.

1 9S 9
2.39 ------S ------ ------------- 
1V 9V 9

2.40 RL = Ri = 100Ω for maximum power

2.41 The BNC cable is far more effective in shielding the input signals from electromagnetic
interference since no loops are formed.

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3.1 For Vi > 0, Vo = 0.

For Vi < 0, Vo = Vi.
The resulting waveform consists only of the negative "humps" of the original cosine wave.
Each hump has a duration of 0.5s and there is a 0.5s gap between each hump.

3.2
(a) output passes first (positive) hump only

(b) output passes second (negative) hump only

(c) output passes first (positive) hump only

(d) output passes second (negative) hump only

(e) output passes full first (positive) hump and 1/2-scale second hump

(f) output passes full wave

3.3 For Vi > 0, Vo = Vi.

For Vi < 0, Vo = -Vi.
The resulting waveform is a full wave rectified sin wave where there are two positive
"humps" for each period of Vi (0.5 sec).

3.4
(a) For Vi > 0.5V, Vo = 0.5V.
For Vi < 0.5V, Vo = Vi.
The resulting waveform is the original sine wave with the top halves of the positive
"humps" (above 0.5 V) clipped off.

(b) For Vi < -0.5V, Vo = -0.5V.

For Vi > -0.5V, Vo = Vi.
The resulting waveform is the original sine wave with the bottom halves of the
negative "humps" (below 0.5 V) clipped off.

3.5 Using superposition, Ohm’s Law, and current division,

9 -
, OHIW ----------------- ------
5 5
5  ----

 
,  OHIW ± --- ,  OHIW ± -------
 5

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--- , - 9 -
, OHIW ------ , , ----------------- ------
 OHIW 5 ULJKW 5 5
5  -------

5 -, 
, ULJKW ---------------- -------
5  5  ULJKW 5
-
,  ULJKW ,  ULJKW ± , ULJKW ------
5
- > 
, , OHIW  ,  ULJKW ------
5
- > 
, , OHIW  ,  ULJKW ------
5
, 

- > 
, , OHIW  ,  ULJKW ------
5

9 GLRGH 9 ± ,  5 --- 9 > 


For Vin > 0, 9 RXW --- 9

3.6  VLQ ( πW )
 LQ

For Vin < 0, 9 RXW 9 LQ  VLQ ( πW )

The positive "bumps" of the resulting waveform are half the amplitude (5 vs. 10) of the
original, and the lower bumps are the same.

3.7 In steady state dc, the capacitor is equivalent to an open circuit. Therefore, the steady state
current through the capacitor is 0 and the steady state voltage across the capacitor is Vout.
(a) For Vs=10V, the diode is forward biased and is equivalent to a short circuit.
Therefore, the equivalent resistance of the two horizontal resistors is R/2 and from
voltage division,
5 -9 --- 9
9 FDSDFLWRU 9 RXW ------------- V 9
5  V
----  5


(b) For Vs=−10V, the diode is reverse biased and is equivalent to an open circuit.
Therefore, the circuit simplifies to two series resistors and

9 FDSDFLWRU 5 -9 --- 9
9 RXW ------------- ± 9
55 V  V

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3.8 There are three possible states of the diodes. When only the left diode is forward biased,
9 RXW 9 + . When only the right diode is forward biased, 9 RXW 9 / . When both diodes
are reverse biased, 9 / < 9 RXW < 9 + . In this case, the circuit is a voltage divider and

5/ --- 9
9 RXW ------------------9
5 L  5 / LQ  LQ

The upper limit of this state is when 9 RXW 9+ 9 corresponding to 9 LQ 9 .

Vout remains at 5V when Vin increases above 10V. The lower limit of the double reverse
biased state is when 9 RXW 9/ ±  9 corresponding to 9 LQ ±  9 . Vout remains at
−5V when Vin decreases below −10V. It is not possible for both diodes to be reverse biased
at the same time in this circuit.
The resulting output signal Vout is a sin wave scaled by 1/2 with the peaks clipped off at
± 9 .

3.9
(a) output passes first (positive) hump only

(b) output is 5.1V over the whole input cycle

3.10 Use a resistor in series with the LED where:

9 ± 9 /('
, ---------------------------
5
The required resistance value is
( 9 ± 9 /(' )
5 ≥ -------------------------------
-
, PD[

9 -
(a) 5 ≥ -------------- Ω
P$

( 9 ± 9 )
(b) 5 ≥ -------------------------- Ω
P$

3.11 9( 9 ± 9 /(' ± 9 &( 9

9 LQ ( VDWXUDWLRQ ) 9 (  9 %( 9  9 9

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3.12
(a) For the LED to be ON, the transistor must be in saturation and
9% 9 /('  9 %( 9  9 9
When the LED is off, IB = 0 and

--- 9
9%
 LQ
So for the LED to be ON,|
9 LQ > 9 % 9

(b) When the transistor is fully saturated,

9% 9 /('  9 9 and 9 & 9 /('  9 9
and
9 ± 9 9
,& --------------------&- ------------- P$
Ω Ω
Assume
 -,
,% -------- P$
 &
If I1 is the current through the horizontal 1k resistor and I2 is the current through the
right 1k resistor, then
9%
, ,  ,% -------  P$ P$
N
and
9 LQ 9 %  ( N ),  9

3.13 When the transistor is in full saturation,

9 &( 9 and 9 %( 9
and
,&
, RXW ,%  ,& -,
-------- , &
 &
In the collector-to-emitter circuit,
9 RXW 9 V ± , & 5 & ± 9 &( , RXW 5 RXW
giving
9 ± , & ( N ) ± 9 , & ( N )

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Now we can solve for the collector and emitter currents:

9
,& ------------- P$
N
and
, RXW , & P$
Therefore,
9 RXW , RXW 5 RXW ( P$ ) ( N ) 9
and the minimum required input voltage is:
9 LQ 9 RXW  9 %(  , % 5 % 9  9  ( P$ ) ( N ) 9

3.14 1: a resistor (e.g., 1k) to limit the base current while ensuring the transistor is in full
saturation
2: 24 Vdc capable of at least 1A of current
3: power diode capable of carrying at least 1A for flyback protection
4: ground

3.15 A voltage source (e.g., 5V) and current limiting series resistor (e.g., 330 Ω) is required on
the LED side. On the phototransistor side, a pull-up resistor (e.g, 1k) and a voltage source
(e.g., 5V) is required on the collector lead and ground is required on the emitter lead.

3.16 1: nothing required

2: 24 Vdc capable of at least 1A of current
3: power diode capable of carrying at least 1A for flyback protection
4: ground

3.17 The type of BJT required is an npn and an additional resistor must be added in series with
the open collector output to pull up the voltage enough to bias the BE junction of the BJT.

3.18 The upper FET is a p-channel enhancement mode MOSFET and the lower is an n-channel
enhancement mode MOSFET. When Vin = 5V, the upper MOSFET doesn’t conduct but
the bottom one does, so Vout = 0V. When Vin = 0V, the upper MOSFET conducts but the
bottom one doesn’t, so Vout = Vcc.

3.19 The requirements are that


, G ( FRQW ) > $ and 3 G ( PD[ ) > , RQ 5 RQ 5 RQ
IRF530N is a good choice

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Solutions Manual

3.20
(a) cutoff

(b) ohmic

(c) saturation

(d) cutoff

18 Introduction to Mechatronics and Meaurement Systems